Cu CMP: Macro-scale Manufacturing for Nano-scale Quality Requirements

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1 Cu CMP: Macro-scale Manufacturing for Nano-scale Quality Requirements Jung-Hoon Chun Laboratory for Manufacturing and Productivity Massachusetts Institute of Technology Cambridge, MA April 23, 2009

2 Manufacturing in the US (2007 Federal Bureau of Economic Analysis Data) Output: 1.6 trillion dollars 20% of the world output 13.4% of the US GDP Slow growth rate/declining economic sector Weak in consumer goods Strong in durable and high value added goods High productivity and innovation driven manufacturing Laboratory for Manufacturing and Productivity

3 Nano-scale Science & Technology Understanding phenomena at nano-scale Utilizing nano-scale phenomena/behaviors Producing nano-scale features Laboratory for Manufacturing and Productivity

4 Metallization with Cu: Macro-scale Manufacturing for Nano-scale Quality Requirements Clean wafer Photoresist coating Exposure Development Etching Clean wafer Plating CMP Laboratory for Manufacturing and Productivity

5 Outline Extrusion Spin Coating Non-Uniform Planarization during Cu CMP Nano-Scale Scratching in Cu CMP Laboratory for Manufacturing and Productivity

6 Conventional Spin Coating a Ω (a) Deposition (b) Spin-up Ω 1 Ω 1 (c) Spin-off Laboratory for Manufacturing and Productivity

7 Problems with Spin Coating An initial coating layer is established using an inefficient coating method (~70% waste) Proper amount of photoresist to obtain specific coating thickness and uniformity is unpredictable o Photoresist is wasted if too much is applied o Incomplete coverage or defects occur if too little is applied Laboratory for Manufacturing and Productivity

8 Extrusion-Spin Coating Conventional Spin Coating Extrusion-Spin Coating Deposition: Deposit resist onto wafer Spin-up: Accelerate wafer to obtain initial coating thickness Deposition: Apply thin layer of resist by extrusion coating Spin-off: Spin at high speed to final thickness Spin-off: Spin at high speed to final thickness Laboratory for Manufacturing and Productivity

9 Experimental Apparatus Laboratory for Manufacturing and Productivity

10 Coating Thickness Profile 1 µm 100 mm Spin coated at 3000 RPM in 0% solvent concentrated environment: mm with 78 Å Spin coated at 3000 RPM in 100% solvent concentrated environment: mm with 12 Å Extrusion-Spin coated at 1500 RPM in 100% solvent concentrated environment: mm with 6 Å Laboratory for Manufacturing and Productivity

11 Cu CMP Process Surface Non-uniformity Laboratory for Manufacturing and Productivity

12 Polishing Stages: Feature and Wafer-Level Laboratory for Manufacturing and Productivity

13 Control Strategy for Dishing and Erosion Key model parameters: α, β and S Cu/Ox Approach: Cu SiO Laboratory for Manufacturing and Productivity

14 Face-up Chemical-Mechanical Polishing Avoid overpolishing by translating pad away from polished center region: Laboratory for Manufacturing and Productivity

15 Patterned Wafer Polishing Experiments SKW mm Cu/SiO 2 Test Wafer Laboratory for Manufacturing and Productivity

16 Patterned Wafer Polishing Experiments Dielectric Erosion Table: Dielectric erosion after face-up CMP. w (µm) Mean (nm) Std. Dev. (nm) Mean/h I Std. Dev./h I Laboratory for Manufacturing and Productivity

17 Patterned Wafer Polishing Experiments Cu Dishing Table: Cu dishing after face-up CMP. w (µm) Mean (nm) Std. Dev. (nm) Mean/h I Std. Dev./h I Wafer-scale variation is low. Once parameters are optimized, e.g. barrier slurry and stiffer pad with in-situ conditioning, dishing can be low across the entire wafer Laboratory for Manufacturing and Productivity

18 Patterned Wafer Polishing Experiments SKW mm Cu/SiO2 Test Wafer Feature-scale non-uniformity Laboratory for Manufacturing and Productivity

19 Controlling Feature-scale Non-uniformity Spin Coating Feature-scale non-uniformity is high for wide interconnects: Even though wafer-scale polishing is controlled by face-up polishing, dishing is still dependent on feature-scale non-uniformity. Must minimize α and h si to minimize dishing. Previous attempts to fill Cu trenches by electroplating were unsuccessful for wide structures, w > 10 µm. Can fill trenches by spin coating a layer of polymer, e.g. photoresist on the wafer prior to polishing. Ideal Actual Spin Coated Laboratory for Manufacturing and Productivity

20 Controlling Feature-scale Non-uniformity Spin Coating, Step Coverage Table: Interconnect step-heights after spin coating with SU-8 of various thicknesses. Step-height (nm) w (µm) No Coating h SU-8 = 1 µm h SU-8 = 2 µm h SU-8 = 4 µm Laboratory for Manufacturing and Productivity

21 Face-up Polishing Summary Laboratory for Manufacturing and Productivity

22 Summary Polishing experiments were conducted on patterned Cu wafers to validate wafer-scale uniformity. Material removal was fairly uniform across a 100-mm region. Erosion for all subdies was below 30 nm. Dishing ranged from 23 nm to 576 nm, increasing with linewidth, but variation was less than 35 nm for all subdies. Dishing can be reduced by minimizing feature-scale non-uniformity spin coating wafers with SU-8 photoresist improved feature-scale uniformity and reduced dishing Laboratory for Manufacturing and Productivity

23 Scratching in CMP 1 µm Source: Intel Low-k Dielectric Cu Laboratory for Manufacturing and Productivity

24 Thank You! Laboratory for Manufacturing and Productivity