CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI

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1 CMOS Technology Flow varies with process types & company N-Well CMOS Twin-Well CMOS STI Start with substrate selection Type: n or p Doping level, resistivity Orientation, 100, or 101, etc Other parameters

2 N-well CMOS (ON.5um) pmos transistors in n-well nmos transistors on substrate nmos transistor s body is always connected to lowest voltage of chip nmos is a three terminal device pmos body can be tied to voltages other than Vdd pmos is a four terminal device 0.35um and larger typically n-well

3 V DD M 2 V in V o M 1

4 Major n-well CMOS Steps

5 Major n-well CMOS Steps

6 Major n-well CMOS Steps

7 Major n-well CMOS Steps

8 Major n-well CMOS Steps

9 Major n-well CMOS Steps

10 Major n-well CMOS Steps

11 Major n-well CMOS Steps

12 A Twin-Well Process Flow Initial cleaning Growth of SiO 2 layer Deposition of Si 3 N 4 layer Spun photoresist layer

13 Apply mask 1 Photo process Dry etch of unprotected area

14 Strip photoresist Grow field oxide

15 Etch out Si 3 N 4, spin photoresist Apply mask 2, photo process, etch Boron implant, form P well for NMOS

16 Etch out photoresist, spin new layer Apply mask 3, photo process, etch N-type implant, form N well for PMOS

17 Etch out photoresist High temp drive-in to complete wells

18 Spin photoresist, apply mask 4 Photo process, etch Boron implant to adjust N-channel V T

19 Spin new photoresist, apply mask 5 Photo process, etch Arsenic implant to adjust P-channel V T

20 Remove photoresist, and thin oxide Grow gate oxide with precise thickness

21 Deposit polysilicon layer Phosphorous implant to heavily dope the poly

22 Spin photoresist Apply mask 6, photo process Plasma etch to remove poly

23 Remove old and spin new photoresist Apply mask 7, photo process N - -type implant

24 Remove old and spin new photoresist Apply mask 8, photo process P - -type implant

25 Remove photoresist Deposit a conformal layer of SiO 2

26 Anisotropically etch SiO 2 layer Form sidewall spacers by poly

27 Grow thin screen oxide Spin photo resist, apply mask 9 Arsenic implant to form drain, source

28 Photoresist, mask 10 Boron implant (P + ) for PMOS S & D

29 High-temp drive-in to activate implanted dopants and diffuse junction to their final depth

30 Unmasked etch to remove oxide from drain, source, and gate tops

31 Deposit titanium layer by sputtering

32 Titanium reacts in N 2 ambient Form TiSi 2 when in contact with Si Elsewhere form TiN

33 Spin photoresist Mask 11 to protect local interconnects Etch remaining TiN

34 Remove photoresist Deposit conforming SiO 2 layer

35 CMP (chemical-mechanical polish) Polish SiO 2 and planarize wafer surface

36 Spin photoresist Mask 12 for contact holes Etch SiO2 to expose poly or TiN

37 Deposit a thin TiN barrier/adhesion Deposit a W layer

38 CMP

39 Deposit Al, spin photoresist Mask 13 Plasma etch

40 Repeat several step for metal 2 with mask 14 and 15 Passivation layer, mask 16 for bonding pads

41 Relative size of different layers

42 Deep SubMicron Challenges Transistor sizes become very small But FOX lateral size cannot be reduced Depletion region between p-well and n- well not reduced Large area FOX depletion

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44 Shallow Trench Isolation Technology Allowing transistors to be spaced closer

45 Shallow Trench Isolation (STI) 1. Cover the wafer with pad oxide and silicon nitride. 2. First etch nitride and pad oxide. Next, an anisotropic etch is made in the silicon to a depth of 0.4 to 0.5 microns. 3. Grow a thin thermal oxide layer on the trench walls. 4. A CVD dielectric film is used to fill the trench. 5. A chemical mechanical polishing (CMP) step is used to polish back the dielectric layer until the nitride is reached. The nitride acts like a CMP stop layer. 6. Densify the dielectric material at 900 C and strip the nitride and pad oxide.

46 DSM CMOS Technology Deep wells good for substrate noise isolation

47 Resistors in STI DSM Diffused and/or implanted resistors. Well resistors. Polysilicon resistors. Metal resistors.

48 Poly-poly capacitors In older processes, you put the bottom plate on FOX

49 Metal-metal capacitors Very linear cap More expensive to make

50 Inductors

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65 Sub 100nm CMOS Technology State of the art is 22 nm 45 nm is in wide use for high speed 65 nm also in wide use for SoCs Grad students in our group have access to certain 45 nm and 65 nm technology Have designed in such technologies But analog transistors have min L = 1 um

66 65 nm CMOS Technology

67 Digital Viewpoint: Advantages Improved I on /I off Reduced gate capacitance Higher drive current capability Reduced interconnect density Reduction of active power Analog Viewpoint: More levels of metal Higher f T Higher capacitance density Reduced junction capacitance per g m

68 Disadvantages for analog Reduction in power supply resulting in reduced headroom Gate leakage currents Reduced small-signal intrinsic gains Increased linearity (IIP3) Noise and matching?? Reduced signal to noise ratio Anne-Johan Annema, et. Al., Analog Circuits in Ultra-Deep-Submicron CMOS, IEEE J. of Solid-State Circuits, Vol. 40, No. 1, Jan. 2005, pp

69 the Gate Leakage Problem

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