Conventional Bulk and Bulk+ Architectures for 45nm Node

Transcription

1 Conventional Bulk and Bulk+ Architectures for 45nm Node Frederic Boeuf STMicroelectronics, 85 rue Jean-Monnet, 3896 Crolles, France Abstract We discuss the possibility of using bulk architecture for 45nm node by a proper device design and the use of technological boosters. We also propose an alternative solution allowing the use of single metal with thin films, co-integrated with conventional bulk devices on bulk substrate. This solution defines a Bulk+ technology. Introduction Power management appears as an important issue for 45nm node. Indeed, following the.7 scaling rule for the MOSFET device parameter leads to a SiON oxide thickness hardly compatible with the leakage requirements of General Purpose Low Operation Power (GP) and Low Standby Power (LP) applications (Figure 1). This issue is well known, and the first solution looked at by industry was the use of High-K dielectric (such as HfO 2 or HfSiON). Unfortunately, these oxides suffers from several issues, such as mobility degradation and Fermi pinning [1]. Recently, the use of Si-rich HfSiON/Poly-Si together with buried conduction channel (counter doped) was proposed [2,3] in order to compensate the threshold voltage shift due to Fermi Pinning. Nevertheless, this leads to a strong DIBL making the control of nanometric devices difficult. Another solution is the use of metallic on High-K, where Fermi pinning phenomenon is negligible [4]. Nevertheless, in order to be able to correctly adjust devices threshold voltage for all kind of applications, workfunctions of metallic s should be identical to those of n + and p + doped poly-si. This makes necessary the use of two different metallic s [5] for nmos and devices, leading to complex integration scheme and reliability issues. In order to design devices for 45nm we propose a different strategy consisting in minimizing the scaling of oxide as proposed in [6,7] by keeping either Poly-Si or Single Metal Gate. In the first case, the subsequent loss on device speed performance is evaluated to 2%. Therefore, smart optimisation of device must be performed in order to compensate this speed degradation due to the static leakage reduction. This conventional Bulk approach is compatible with consumer electronics applications where a very low-cost is a major driver. Jg (A/cm2) 1.E+4 1.E+3 1.E+2 1.E+1 1.E+ 1.E-1 1.E-2 1.E-3 Regular SiON scaling for GP45nm GP PNO (.9V) GP65nm GP EXP DATA LP EXP. DATA MASTAR regular SiON scaling for LP45nm LP65nm LP PNO (1.2V) CETinv (Å) Figure 1 :Gate leakage trend as a function of CETinv for Plasma Nitrided oxides. A regular scaling of the 65nm node CET to 45nm using poly-si electrode lead to an excessive leakage current. In the second case, a single mid-gap electrode (or close to mid-gap) is used in combination with a fully depleted thin-film channel. This ensures the adjustment of threshold voltage for both GP and LP applications and allows a better scaling of total capacitance, by suppression of poly-depletion effects. A major point in this approach is the co-integration of regular bulk devices, in order to ensure a full compatibility of the analog and I/O platform. The Silicon On Nothing (SON) architecture is a promising candidate in this perspective, defining a Bulk+ architecture. In this paper we show examples of conventional Bulk optimisation using Strain-Silicon, advanced USJ and Bulk+ integration for 45nm node (Figure 2.) Conventional Bulk Bulk+ Architecture Advanced junctions SiON oxide Stressed- Poly- Strained- Liner Strained- Liner Localized BOX Figure 2 : Schematic view of bulk and bulk+ architectures Bulk optimisation for 45nm node TOSI- SiON oxide 1

2 In order to compensate performance reduction due to stack limited scaling, the use of cumulated strained-silicon options is mandatory. For electrons, uni-axial tensile stress is known to allow performance improvement. This stress can be induced by a tensile nitride liner, used as Contact Etch Stop Layer (CESL) [8] as shown in Figure 3. This layer creates tensile zones near the edge and a compressive zone in the center of the MOSFET channel. For short devices, the tensile zones on the edge are overlapping, leading to a device with a complete tensile channel. As a result nmos performance is improved by 1~15%. For holes mobility improvement, compressive liner can be used and co-integrated with tensile liner [11]. Nevertheless, a lower cost solution can be used for GP/LP application. Indeed, a closer look on the band structure of holes reveals anisotropy of the Heavy-Holes (HH) subband (Figure 4). In particular, HH are lighter in the (1) direction. As a result, using (1) channel for devices leads to 15% improvement on the drive current (Figure 5) <11> <1> nmos Log(Ioff) A/µm % unstrained Ion (norm) +2% Strained Liner combination Figure 3 : Tensile strained-channel MOSFET (Lg=3nm) created using stressed-nitride layer as Contact Etch Stop Layer The use of this techniques can lead to a hole mobility degradation, and may require an additional Ge implantation in the CESL layer on [9] to relax channel stress. Other techniques can be used to induce stress in MOSFET channel by process, such as Stress Memory Technique. This technique consist in a poly- Si re-crystallization under a stressed capping layer by using S/D anneal [1], and leads to an improved nmos performance (6~1%). Depending on used materials, it can be necessary to remove the capping layer on the before performing the S/D anneal. An interesting point is that CESL and SMT layers effects are additive. In Figure 5, 2% improvement on nmos performance is obtained by the combination of SMT and CESL. Energy (ev) (1) (11) Γ SO LH HH Wave Vector k/(2π/a) Figure 4 : Valence band structure of Si computed using a 6x6 Lutinger Hamiltonian. Figure 5 : nmos and performance improvement using lowcost mobility boosters. 15% drive current improvement is obtained on by using (1) channel. 2% improvement on nmos drive current is obtained by using a combination of strained liners. Integration of these conventional strained bulk devices with Lg=3nm (Figure 6) has been successfully demonstrated into a.334µm² SRAM bit-cells representative of 45nm node design rules [12].Besides mobility improvement, a performant junction scaling is also mandatory in order to achieve good control of the Short Channel Effects. Shared Contact Pull-up Vdd 6nm 3nm Pull-up Figure 6 : TEM Cross section of a.334µm² SRAM bit-cell for 45nm node Ultra short non-diffusing anneals are a promising candidates to realize both improvement of SCE control 2

3 and dopant activation enhancement. As shown on Figure 7, the combination of these new techniques (LSA or Flash Annealing) with spike annealing allows improving the nmos () performance by 11% (6%) respectively. Without spike annealing the DIBL effect can be significantly reduced for both nmos and [13]. nothing. The tunnel is then filled with dielectric, allowing the creation of a local Burried Oxide (BOX). 1.E-5 Vdd=.9V PMOS NMOS Ioff (A/µm) 1.E-6 1.E 1.E +6% RTA +11% RTA+Ultra short Anneal Figure 7 : Performance improvement is obtained by using ultra-fast S/D anneal in combination with regular spike RTA. Bulk+ for 45nm node Using of a modulated mid-gap metal in combination with fully depleted thin film is a way to obtain a regular capacitance scaling (though poly-depletion suppression) without static leakage degradation (i.e. by keeping the same oxide thickness than in 65nm node), and adjusted threshold voltages for both GP and LP applications. First, mid-gap metal s can be achieved by the use of the Totally Silicided (ToSi) process [14] using either CoSi2 or NiSi (Figure 8). If CoSi2-ToSi s are mid-gap, NiSi-ToSi workfunction can be modulated through the use of ionimplantation. Depending on the dopdant type and dose, it has been shown that workfunction could be adjusted toward n + type or p + type [15].As a result, workfunction can be modulated by +/- 3meV around the mid-gap, allowing threshold voltage adjustement for LP and GP devices on FD films. Next, the realisation of FD device on bulk substrates has been successfully demonstrated by using the Silicon On Nothing (SON) technique [16-17]. Main device process-steps are described in Figure 9. After STI patterning, a SiGe Selective Epitaxial Growth (SEG) is performed followed by a Si SEG. This last layer defines the future conduction channel of the SON device. After patterning, a junction recess is performed in order to access to the SiGe buried layer. Then, a selective removal of the SiGe is performed, leading to an empty tunnel under the. At this stage, the channel stands above Figure 8 : Example of different ToSi s : NiSi/Bulk (right) CoSi2/Bulk+ (left) Finally, junctions are re-filled using a Si SEG. As a result, the device morphology reveals a fully depeled channel with a local BOX. Figure 1 show the comparison of Lg=45nm poly-/sion devices integrated with bulk and SON process. Using thin films allows improving DIBL and SS and also using lightly doped channel. Moreover, using thin films allows a lower channel implantation, leading to a reduction of the junction leakage by 1 decade. This makes the SON suitable for LP options. Figure 9 : main process steps of SON module I (A/µm) 1,E-2 1,E-3 1,E-4 1,E-5 1,E-6 1,E 1,E 1,E 1,E-1 1,E-11 1,E-12 1,E-13 1,E-14 Bulk DIBL=185mV Vd=1.2V Vd=.1V Junction Leakage -,2,2,4,6,8 1 1,2 Vg(V) I (A/µm) 1,E-2 1,E-3 1,E-4 1,E-5 1,E-6 1,E 1,E 1,E 1,E-1 1,E-11 1,E-12 1,E-13 Vd=1.2V Bulk+ (SON) Reduced DIBL =75mV Vd=.1V Improved SS Junction Leakage -1 Vg=V 1,E-14 -,2,2,4,6,8 1 1,2 Vg(V) Figure 1 : Bulk versus Bulk+ (SON) sub-threshold characteristics. Subthreshold slope and DIBL are improved by using thin films. 3

4 In addition, an important point of the Bulk + platform is the easy co-integration with standard bulk devices, mainly for analog and I/O application where thin film are not desired. Indeed, this allows the re-use of existing libraries and participates to the low cost of the technology. In order to achieve this co-integration, a hardmask is deposited on the bulk zone prior to the SEG to avoid the SiGe growth. Then no local BOX is created on these devices leading to regular bulk devices fabrication (Figure 11). SRAM using Bulk+ process : (SiGe epi) Conventional Bulk I/Os (no SiGe epi) Si Channel BOX Si Channel Figure 11 : Co-integration of bulk and bulk+ on the same chip is possible with SON module, by using a simple hardmask before SiGe SEG. Finally, the combination of the ToSi process with the SON process allows fabricating Bulk+ devices with adjusted threshold, scaled inversion capacitance, and improved subthreshold characteristics Conclusion Using technological boosters, Bulk architecture is still a good candidate for low-cost consumer electronics products. Performance improved Bulk+ platform can be achieved by using combination of mid gap metal by ToSi process and Silicon On Noting technology. Acknowlegment Author would like to thank Stephane Monfray, and Fabrice Payet from STMicroelectronics, as well as Anaud Pouydebasque and Markus Müller from Philips Semiconductor for their contribution. This work was also partially supported by the European Project IST-NanoCMOS. References [1] C. Hobbs et al., VLSI 23, pp 9-1 [2] H.C.H Wang et al, IEDM 24, p161 [3] N. Kimizuka et al., VLSI 25, p218 [4] S. Samavedam et al, IEDM 23, pp37-31 [5] S. Samavedam et al, IEDM 22, pp 433 [6] P. Bai et al., IEDM 24, pp [7] F. Boeuf et al.,iedm 24, pp [8] A. Shimizu et al., IEDM 21, p433 [9] F. Bœuf et al, SSDM 4, pp [1] K. Ota et al., IEDM 22, p 27 [11] H.S. Yang et al., IEDM 24, p175 [12] F. Boeuf et al., VLSI 25, p13 [13] A. Pouydebasque et al., IWJT 25 [14] B. Tavel et al. IEDM 21, p825 [15] D. Aime et al., IEDM 24, p 87 [16] S. Monfray et al., IEDM 21, p645 [17] S. Monfray et al., IEDM 24, p 635 4

5 1 Acknowledgement 2 45nm Conventional Bulk and Bulk+ Architectures Frédéric BOEUF Advanced Devices, Project Manager STMicroelectronics Claude Ortolland, Franck Arnaud, Claire Gallon, Claire Fenouillet-Beranger, Anne Vandooren, Markus Müller, Fabrice Payet, Alexandre Mondot, Stephane Monfray, Arnaud Pouydebasque,Benjamin Dumont, Melanie Szczap, Pascal Gouraud, Jerome Todeschini, Laurent Pain, Marcel Broekaart, Catherine Chaton, Pierre Morin, Veronique Dejonghe. frederic.boeuf@st.com F.Bœuf, COE Workshop 25, September 16 th, Hiroshima (J) Outline 3 Introduction 4 Introduction Conventional Bulk Definition for 45nm node Device Optimization Strategy Electrical Results 45nm node 6T-SRAM demonstration E-beam processing Electrical results Bulk+ Definition for 45nm node ToSi process Silicon On Nothing (SON) Process for Bulk+ Co-Integration of Bulk with Bulk+ Conclusion Different targets for different products High Performance applications (MPU,CPU,VPU ) Optimization strategy speed i.e. small Lg and high Ion Leakage is relaxed Low Power applications (mobile, cell-phone.) Optimization strategy Power dissipation i.e. small Ioff and high integration density (low cost products) Ion is relaxed Introduction 5 Introduction 6 Boosters for High Performance applications Strain-Silicon for enhanced mobility Dual Metal Gate for low Vth nmos and High-K with small EOT <1nm? (Sugii et al. SSDM 25) FD-Double architecture for SCE control Boosters for Low Power applications Strain-Silicon for enhanced mobility Single Mid gap Metal Gate for high Vth in nmos and High-K with small EOT >1.4nm FD-Single architecture for SCE control At 45nm node, Performance Boosters for Low Power needs to be choosen Hypothesis : keep SiON oxide This work 1. Conventional approach : Optimization strategy for 45nm Bulk platform 2. Advanced Approach : Definition of a Bulk+ platform based on thin-film/mg devices

6 Conventional Bulk for 45nm Node 7 Jg (A/cm2) 1,E+4 1,E+3 1,E+2 1,E+1 1,E+ 1,E-1 1,E-2 1,E-3 Gate Oxide Shrink Limitation Regular scaling GP (.9V) GP EXP DATA LP EXP. DATA MASTAR PN Oxide LP (1.2V) CETinv (Å) IGate,off (na/µm) CET 2Å CET 19Å CET 18Å min leakage (HVT),8,85,9,95 1 Vdd (V) 8 GP : CET 19 Å V dd =.85V (low leakage) and V dd =1-1.2V (high speed) LP : CET 25Å V dd =1.2V Strain-Si Si Technique compatibility with LP? SRBs - Si x Ge 1-x Junction leakage SiGe band Gap Default density Substrate-based based Rotated Sub. Process-based Liners SiGe SEG no yes yes yes 2-25% Gain on pfet 2-25% Gain on nfet Junction leakage? Cost? 9 Process Induced Strain Flow PNO + Poly-Si Gate Amorphization Gate patterning SD extension Low temp. D-Shape Spacer SD implantation SMT layer deposition SD Annealing SMT layer removal SiProtect formation NiSi PIS Level 1 Tensile CESL Ge implantation (pfet) Metal1 PIS Level 2 1 Level 1 : Stress Memory Technique pfet nfet Stressed liner deposition (oxide+nitride) 1,2 Selective etch on (see next slide) 11 Ioff (LogA/µm) Level 1 (SMT) : Electrical Impact -6 GP nmos device Vdd=1V no SMT layer +6% nmos with SMT 12 SD Anneal (RTA). Modification of poly-recrystalisation SMT removal. Tensile stress created in the nmos channel 1 Ota et al., IEDM 22 2 Chen et al., VLSI 24,8,9 1 1,1 1,2 1,3 1,4 normalized Ion (µa/um) (F. Boeuf et al., IEDM 24) SMT layer SMT removal on

7 Level 2 : Contact Etch Stop Layer 13 Tensile CESL optimization 14 Tensile Liner Tensile area in MOS channel Log(Ioff) (A/µm) -6 GP nmos, L=3nm Vdd=1V std CESL +1% tensile CESL,8,9 1 1,1 1,2 1,3 1,4 normalized Ion (A/µm) 115 nm Tensile CESL 3nm 5nm Ion =cst Liner optimisation for SRAM integration Prev. work 12nm 5nm 35nm this. work Stress MPa Same Ion improvement with reduced Thickness Impact of CESL on (11) channel 15 (1) Channel improves Hole mobility 16 masking Ge implantation for stress relaxation 1.E Heavy hole effective mass is lighter in (1) than in (11) 25% increase of mobility nmos (F. Boeuf et al., SSDM 24) Ioff (A/µm) +7% 3X thickness 3X thickness + Ge I2 1X thickness 1.E Energy (ev) (1) SO LH HH Γ Wave Vector k/(2π/a) (11) E (ev) [1] Si valence band computed by k.p hamiltonian [11] [1] and supress longitudinal stress effect! Id linear Variation [%] (1) (11) (11) channel (1) channel Not sensitive to STI Stress -1,1 1 1 Lsd distance Gate to STI [µm] 17 Log (Ioff) A/µm Strained-Si Si CMOS integration <11> +15% <1> Ion (norm) Log(Ioff) A/µm nmos unstrained Ion (norm) +2% Strained Liner combination 18

8 Junction Optmization 19 Plasma Doping (PLAD) 2 Ion@Ioff=constant Gate Length shrink efficiency shows an optimum on I on at a given I off Depending on Xj channel doping needed to keep good SCE will degrade channel mobility Xj=15nm Xj=2nm 65nm DATA MASTAR Lmin@Ioff=constant Rsheet (Ohm/sq) Low temperature spike anneal allows shallow junction for As Poly-depletion issues? Lower Rs achiveable? As B Max. Max Xj (nm) Vt/ Lg (V/nm) Improved SCE control on nmos and - 45% - 51% NMOS PMOS PLAD ULE Vdd=.9V Lg (nm) (B. Dumont et al., ESSDERC 25) Ioff (Log A/µm) -5-6 Lower pocket dose allows performance 4% improvement on nmos Vdd=.9V Lg = 4nm 4% PLAD ULE Ultra Short Anneal Integration 21 45nm Bulk Device Morphology 22 Ioff (A/µm) 1.E-5 1.E-6 1.E 1.E Vdd=.9V PMOS +6% RTA NMOS +11% RTA+Ultra short Anneal Tensile CESL NiSi 3nm 3nm (1) channel TEM cross-section of device 3nm length 3nm D-Shape spacer 5nm contacts Boosters 1 channel for drive current enchancement Highly tensile CESL for nmos drive current enchancement GP MOS : Electrical Results 23 Low Power Devices (L=45nm) 24 nmos Log (Ioff (na/µm)),5,5 482µA/µm 3nA/µm 1145µA/µm 3nA/µm Log (Ioff (na/µm)) µA/µm 3pA/µm nmos 6µA/µm 3pA/µm 45 nm LP devices CET 25Å 5 1 Vth (V),6,4,2, -,2 -,4 -,6 -,8 LP nmos LP,5V 1,2V Lpoly (nm)

9 Conventional Platform Definiton Design OD PO CO M1 Density 65nm kg/cm² Pitch (nm) 45nm 13 ~14 115~13 14~15 125~135 PO-CO 45 3~35 N + /P ~15 1 Arnaud et al., VLSI 4 2X 16 kg/cm² Platform needs to be compatible with 45nm design Linear scaling factor Surfacic density 2X 6T-SRAM bit-cells for 65nm node.69µm² -.499µm² 6T-SRAM bit-cells for 45nm node.35µm² -.25µm² 25 HD.334µm² SRAM bit-cell Design Endcap:7 38 Main Design Rules CO:7 Pitch Line/space N+/P+: 11 PO:45 M1:7 88 OD /8 PO /8 CO 16 7/9 M1 14 7/7 PO-CO 35 n+/p UHD.248µm² SRAM bit-cell Design 27 E-beam Lithography Capability for R&D Validation 28 Smaller Endcap:5 34 smaller CO:7 reduced N+/P+: 95 PO:45 73 Main Design Rules Pitch Line/space OD /8 PO /8 CO 14 5/9 M1 13 7/6 PO-CO 35 n+/p % of values with overlay with [-23,+23nm] Nb of measurements X Y % Overlay value (nm) CD Litho(nm) Linearity Control must be corrected for SRAM patterning CD Design(nm) E-beam Proximity Correction (EBPC) 29 OD Patterning 3 Top view after e-beam lithography Top view after STI Module Insufficient overlap Corrected pattern.248µm² Bit-cell.248µm² Bit-cell 55nm

10 31 Advanced Gapfill Process Top view after e-beam lithography Iso No SiN clipping 348nm 32 Gate level patterning Top view after Gate Etch.248µm² Bit-cell.248µm² Bit-cell <7nm 3nm No Low Density Area 45nm PU PG PD Frédéric BOEUF, COE workshop 25, September 16th, Hiroshima (J) Frédéric BOEUF, COE workshop 25, September 16th, Hiroshima (J) 33 Contact and M1 Patterning 34 Going towards 32nm with e-beam Top view after M1 etch OD of.178µm² 6T SRAM Bit-cell OD of.124µm² 6T SRAM Bit-cell 7nm Shared contact E-beam lithography 6nm.248µm².248µm² Frédéric BOEUF, COE workshop 25, September 16th, Hiroshima (J) Frédéric BOEUF, COE workshop 25, September 16th, Hiroshima (J) µm² SRAM functionnality Measured butterfly caracteristic Shared Vdd=.9;1.;1.2V Silicon 8 Pull-up Pull-up Vout (mv) Vout (V).8 3nm 6 1 Contact 6nm 8 1nm contact Vdd Shared Vdd Vout (mv) TEM cross section of a.334µm² SRAM bit-cell.248µm² SRAM bit-cell 3nm.4 Pull-up 4 2 Vdd=1. V 19mV 6 5 Vin (mv) 4 5nm Pull-up Vdd=1. V.248µm² Vin (V).8 (F. Boeuf et al., VLSI 25) Frédéric BOEUF, COE workshop 25, September 1.2 TEM cross section of a.248µm² SRAM bit-cell 5 Vin (mv) (F. Boeuf et al., VLSI 25) 16th, Hiroshima (J) Frédéric BOEUF, COE workshop 25, September 16th, Hiroshima (J) 1 1

11 Cell size [µm²] Historical Trend of SRAM bit-cells size nm 45nm 32nm TSMC, SOI IMEC, Tri/ SOI Our conventional BULK Current investigation IBM, SOI 37 Intermediate Summary Conventional 45nm compatible bulk platform achieved Gate oxide scaling limited Dual mobility enhancement technique used Strained-liner combination for nmos (SMT/CESL) (1) conduction channem for Integration in 45nm node 6T-SRAM cell achieved e-beam lihography is cost effective Remaining issues Improvingperformance while keeping reasonnable static leakage for Low Power application Reducing junction leakage for LSTP 38 Bulk+ + for 45nm node 39 CET Shrink Poly Depletion Metal Gate ToSi MG V th adjust? SCE/Xj Thin Film Devices (FD) + φ ms I/O Integration Bulk Wafers SON Bulk+ Platform Junc. Leak Objectives Correction of Conventional Bulk weakness: Improving CET scaling of conventionnal bulk Improving SCE control Improving Junction leakage Integration of Thin-film devices with a single metal on bulk substrate Mid-gap + thin-film = adjusted Vth for Low Power application Improved SCE (lower DIBL) Low doped channel (better mobility) 4 From Bulk to Bulk + 41 Totally Silicided Gate (ToSi) 42 Strained- Liner Stressed poly-gate Strained- Liner ToSi- CoSi2-ToSi (mid-gap) MOSFET integration Tavel et al., IEDM 21 NiSi-ToSi workfunction modulation Aime et al., IEDM 24 Advanced junctions SiON oxide Bulk + ToSi module + SON module Localized BOX Bulk + SiON oxide substrate CoSi 2 Work Function (ev) Poly undoped B P As As + P 3.8 Si Si conduction conduction band band N+ poly P+ Poly 5.2 Si valence Si valence band band 5.4 FD film workfunction Required for LP

12 CMP Less - approach NiSi-ToSi 4nm ToSi Gate Module Ioff (na/µm) 1 1 Functionnal Bulk LP Devices Bulk/TOSI Tox=17A Vdd=1.2V Bulk/Strain, The «Silicon On Nothing» (SON) Technology (S. Monfray et al., IEDM 21) STI Selective mono-si epitaxy TEOS Spacer cleaning Si Selective SiGe epitaxy Selective epitaxial growth TEOS spacer S Si Selective isotropic removal of SiGe D 44 Si Tunnel filled with with Dielectric Dielectric Si Device Morphology 45 SON subthreshold behavior 46 1.E-2 1.E-3 Bulk Vd=1.2V 1.E-2 1.E-3 Bulk+ (SON) Vd=1.2V 1.E-4 1.E-5 Vd=.1V 1.E-4 1.E-5 Vd=.1V 1.E-6 1.E-6 Improved SS I (A/µm) 1.E 1.E 1.E I (A/µm) 1.E 1.E 1.E Reduced DIBL 1.E-1 1.E-11 1.E-12 Junction Leakage 1.E-1 1.E-11 1.E-12 Junction Leakage -1 Vg=V 1.E-13 1.E-13 (S. Monfray et al., IEDM 24) 1.E Vg(V) 1.E Vg(V) Benefic effect on IDsat 47 Co-Integration of Bulk and Bulk + 48 Id (A/µm) 1.2E-3 1.E-3 8.E-4 6.E-4 4.E-4 2.E-4 Bulk+(SON) 3% Bulk Bulk+/SON allows a better drivebility due to better subthreshold slope Reduced doping allows reduced effective field improved mobility SRAM using Bulk+ process : (SiGe epi) Conventional Bulk I/Os (no SiGe epi) Si Channel BOX Si Channel.E+.5 1 Vd (V)

13 Combination of ToSi with SON 49 Conclusion 5 ToSi Gate (CoSi 2 ) 55nm Conduction Channel Tsi= 5nm Localized BOX Idrain (A/µm) 1.E-3 1.E-4 1.E-5 1.E-6 1.E 1.E 1.E 1.E-1 1.E-11 1.E-12 Metal 4 orders of magnitude in Ioff Poly-Si Gate Vg (V) Bulk architecture can be scaled down to 45nm node for Low Cost application Gateoxidescalingisslow down Strain-Si can compensate performance loss Junction can be scaled using ultra-fast anneal Issue : junction leakage? Bulk+ + architecture is proposed to solve bulk issue while keeping substrates and co-integration of bulk I/O (IP reuse) Single Metal mid-gap with Thin Film devices = Good Vth adjustement for Low Power applications and regular 45nm CET scaling Junction leakage and scaling issues are solved Co-integration with bulk I/O is demonstrated