Background Statement for SEMI Draft Document 5252 REVISION TO SEMI M With Title Change to: SPECIFICATIONS FOR SILICON ANNEALED WAFERS

Transcription

1 Background Statement for SEMI Draft Document 5252 REVISION TO SEMI M With Title Change to: SPECIFICATIONS FOR SILICON ANNEALED WAFERS Notice: This background statement is not part of the balloted item. It is provided solely to assist the recipient in reaching an informed decision based on the rationale of the activity that preceded the creation of this document. Notice: Recipients of this document are invited to submit, with their comments, notification of any relevant patented technology or copyrighted items of which they are aware and to provide supporting documentation. In this context, patented technology is defined as technology for which a patent has issued or has been applied for. In the latter case, only publicly available information on the contents of the patent application is to be provided. Background information SEMI M The document was modified and updated for the technology nodes 90nm, 65nm, 45nm, 32nm, and 22nm. To accommodate these technology nodes, Additions were made to Table R1-1, and Tables R1-2 and R1-3 have been added. The document was reviewed by AW Japan & NA Task Forces. It was approved for ballot by the NA Silicon Wafer committee in Santa Clara, CA in Oct for review at SEMICON West The ballot results will be reviewed by the Int l Annealed Wafer TF and adjudicated by NA Silicon Wafer Committee during their meetings in San Francisco, CA, in July 2012 during SEMICON West. Check for the latest schedule. For question, please contact Dinesh Gupta / STA dgupta@pacbell.net Kevin Nguyen / SEMI tel (+1) ; fax (+1) ; knguyen@semi.org Note: Additions are indicated in red and deletions are indicated by strikethrough.

2 SEMI Draft Document 5252 REVISION TO SEMI M With Title Change To: GUIDE FOR SPECIFYING SPECIFICATIONS FOR SILICON ANNEALED WAFERS 1 Purpose 1.1 A number of device manufacturers utilize silicon annealed wafers to gain improved device characteristics. This guide specification provides information for developing specifications for silicon annealed wafers used to fabricate semiconductor devices and integrated circuits. 2 Scope 2.1 This guide specification covers dimensional, electrical, chemical, and structural properties of silicon annealed wafers for 180 nm, 130 nm, 90 nm, (Table R1-1), 65 nm, 45 nm, 32 nm, (Table R1-2), and 22 nm (Table R1-3) device technology generations. 2.2 Based on the guidance herein, the user of the guide can generate specifications for silicon annealed wafers. 2.3 One of the reasons for using annealed wafers is to allow a reduction in the crystal originated pits (COP), also sometimes known as crystal originated particles, near the top surface region of the wafer. The width of the denuded zone (DZ) free of bulk micro defects (BMD) is also an important parameter. NOTICE: SEMI Standards and Safety Guidelines do not purport to address all safety issues associated with their use. It is the responsibility of the users of the Documents to establish appropriate safety and health practices, and determine the applicability of regulatory or other limitations prior to use. 3 Referenced Standards and Documents 3.1 SEMI Standards and Safety Guidelines SEMI M1 Specifications for Polished Single Crystal Silicon Wafers SEMI M35 Guide for Developing Specifications for Silicon Wafer Surface Features Detected by Automated Inspection SEMI M45 Specification for 300 mm Wafer Shipping System SEMI M53 Practice for Calibrating Scanning Surface Inspection Systems Using Depositions of Monodisperse Polystyrene Latex Sphere on Unpatterned Semiconductor Wafer Surfaces SEMI M58 Test Method for Evaluating DMA-Based Particle Deposition Systems and Processes SEMI M59 Terminology for Silicon Technology SEMI MF81 Test Method for Measuring Radial Resistivity Variation on Silicon Wafers SEMI MF391 Test Methods for Minority-Carrier Diffusion Length in Extrinsic Semiconductors by Measurement of Steady-State Surface Photovoltage SEMI MF523 Practice for Unaided Visual Inspection of Polished Silicon Wafer Surfaces SEMI MF951 Test Method for Determination if Radial Interstitial Oxygen Variation in Silicon Wafers SEMI MF1239 Test Methods for Oxygen Precipitation Characteristics of Silicon Wafers by Measurement of Interstitial Oxygen Reduction SEMI MF1530 Test Method for Measuring Flatness, Thickness, and Total Thickness Variation on Silicon Wafers by Automated Noncontact Scanning SEMI MF1535 Test Method for Carrier Recombination Lifetime in Silicon Wafers by Noncontact Measurement of Photoconductivity Decay by Microwave Reflectance SEMI MF1617 Test Method for Measuring Surface Sodium, Aluminum, Potassium, and Iron on Silicon and Epi Substrates by Secondary Ion Mass Spectroscopy SEMI MF1726 Practice for Analysis of Crystallographic Perfection of Silicon Wafers SEMI MF1727 Practice for Detection of Oxidation Induced Defects in Polished Silicon Wafers SEMI MF1809 Guide for Selection and Use for Etching Solutions to Delineate Structural Defects in Silicon Page 1 Doc SEMI

3 SEMI T3 Specification for Wafer Box Labels SEMI T7 Specification for Back Surface Marking of Double-Side Polished Wafers with a Two-Dimensional Matrix Code Symbol 3.2 ANSI Standards 1 ANSI/ASQC Z1.4 Sampling Procedures and Tables for Inspection by Attributes ANSI/EIA 556-B Outer Shipping Container Bar Code Label Standard 3.3 ASTM Standards 2 ASTM D523 Standard Test Method for Specular Gloss ASTM E122 Standard Practice for Choice of Sample Size to Estimate the Average Quality of a Lot or Process 3.4 ISO Standard 3 ISO Surface Chemical Analysis Determination of Surface Elemental Contamination on Silicon Wafers by Total Reflection X-Ray Fluorescence Spectroscopy (TXRF) on silicon wafers by total reflection X-ray fluorescence spectroscopy (TXRF) 3.5 JEITA Standards 4 EM-3508 Test method for bulk micro defect density and denuded zone width in annealed silicon wafers EM-3509 Sample preparation method for minority carrier diffusion length measurement in silicon wafers by surface photovoltage method 3.6 JIS Standards 5 H 0609 Test Methods of Crystalline Defects in Silicon by Preferential Etch Techniques H 0614 Visual Inspection for Silicon Wafers with Specular Surfaces Z 8741 Specular Glossiness Method of Measurement NOTICE: Unless otherwise indicated, all documents cited shall be the latest published versions. 4 Terminology 4.1 Most general terms, acronyms, and symbols relating to silicon technology are defined in SEMI M Terms specific to commonly-used annealed wafers are defined as follows: annealed wafer wafer that has a defect (COP) free zone near the surface resulting from high temperature annealing under a neutral or reducing atmosphere argon annealed wafer annealed wafer produced under argon atmosphere hydrogen annealed wafer annealed wafer produced under hydrogen atmosphere. 5 Ordering Information 5.1 Purchase orders for silicon annealed wafers furnished to this guide shall include the appropriate order entry information from Table 1, Polished Wafer Specification Format for Order Entry, in SEMI M1. All information in Part 1, General Information, and the following items from Part 2, Polished Wafer or Substrate, shall be included: Growth Method Crystal Orientation Conductivity Type 1 American National Standards Institute, New York Office: 25 West 43rd Street, New York, NY 10036, USA. Telephone: , Fax: , Website: 2 ASTM International, 100 Barr Harbor Drive, West Conshohocken, Pennsylvania , USA. Telephone: , Fax: , Website: 3 International Organization for Standardization, ISO Central Secretariat, 1, rue de Varembé, Case postale 56, CH-1211 Geneva 20, Switzerland. Telephone: ; Fax: Website: 4 Japanese Electronic and Information Technology Industries Association (JEITA). Tokyo Chamber of Commerce and Industry Building 2-2, Marunouchi 3-chome, Chiyoda-ku, Tokyo , Japan. Website: 5 Japanese Industrial Standards, Available through the Japanese Standards Association, 1-24, Akasaka 4-Chome, Minato-ku, Tokyo , Japan. Telephone: ; Fax: Website: Page 2 Doc SEMI

4 2-1.5 Dopant Nominal Edge Exclusion Co-dopant in Crystal Wafer Surface Orientation Resistivity (Center point) Radial Resistivity Variation Oxygen Concentration/Calibration Factor Radial Oxygen Variation Carbon Concentration (Background) Lineage Twin Boundary Swirl Wafer ID Marking Front Surface Thin Films Extrinsic Gettering Backseal Diameter Edge Profile Thickness Total Thickness Variation (TTV) Edge Chips Edge Chips (Back Surface) Brightness (Gloss) (Back Surface) Scratches (Macro) (Back Surface) Table 1 Silicon Wafer Specification Format for Order Entry, Part 5 Annealed Wafers ITEM SPECIFICATION MEASUREMENT METHOD 5-1. ANNEALING CONDITIONS Annealing Atmosphere [ ]Hydrogen; [ ]Argon; [ ]Other: (specify) 5-2. POST-ANNEAL WAFER PREPARATION CHARACTERISTIC Edge Surface Condition [ ]Ground; [ ]Etched; [ ]Polished A 5-3. POST-ANNEAL DIMENSIONAL CHARACTERISTICS Warp [ ] µm; max. [ ]SEMI MF657; [ ]SEMI MF1390; [ ]Other: Flatness, Site Acronym #2 : [ ] [ ] [ ] [ ] Value: Not greater than [ ]µm Site Size mm mm % Usable Area [ ]Include partial sites; [ ]Do not include partial sites Offset: x = [ ] mm, y = [ ] mm 5-4. POST-ANNEAL FRONT SURFACE CHEMISTRY Surface Metal Contamination [ ]SEMI MF1530; [ ]Other: (specify) Page 3 Doc SEMI

5 ITEM SPECIFICATION MEASUREMENT METHOD Sodium [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]Other: (specify) Aluminum [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]Other: (specify) Potassium [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]ISO (TXRF); [ ]Other: (specify) Chromium [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]ISO (TXRF); [ ]Other: (specify) Iron [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]ISO (TXRF); [ ]Other: (specify) Nickel [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]ISO (TXRF); [ ]Other: (specify) Copper [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]ISO (TXRF); [ ]Other: (specify) Zinc [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]ISO (TXRF); [ ]Other: (specify) Other Surface Metals (List Separately) Calcium [ ]Not greater than [ 10 ]atoms/cm 2 [ ]ICP/MS; [ ]AAS; [ ]SEMI MF1617 (SIMS); [ ]ISO (TXRF); [ ]Other: (specify) 5-5. POST-ANNEAL FRONT SURFACE INSPECTION CHARACTERISTICS Slip [ ]None; [ ]Other: (specify) [ ]SEMI MF1809; [ ]JIS H 0609; [ ]Other: (specify) Oxidation Induced Stacking Faults (OSF) [ ]None; [ ]Not greater than [ ] per cm 2 Test Cycle: [ ]SEMI MF1727; [ ]JIS H 0609; [ ]Other: (specify) Observation Method: [ ]SEMI MF1726; [ ]JIS H 0609; [ ]Other: (specify) Scratches Macro [ ]None; Total Length = [ ]mm [ ]SEMI MF523; [ ]JIS H 0614; [ ]SSIS; #3 [ ]Other: (specify) Scratches Micro [ ]None; [ ]Total Length = [ ]mm [ ]SEMI MF523; [ ]JIS H 0614; [ ]SSIS; #3 [ ]Other: (specify) Haze [ ]None; [ ]Other: (specify) [ ]SEMI MF523; [ ]JIS H 0614; [ ]SSIS; #3 [ ]Other: (specify) Page 4 Doc SEMI

6 ITEM SPECIFICATION MEASUREMENT METHOD Localized Light Scatterers (Total LLS) Localized Light Scatterers (COP only) Size: [ ] µm (LSE) Count: [ ] [ ] per [ ]SEMI MF523; [ ]JIS H 0614; [ ]SSIS; #3 wafer; [ ] per cm 2 [ ]Other: (specify) Size: [ ] µm (LSE) Count: [ ] [ ] per wafer; [ ] per cm 2 Size: [ ] µm (LSE) Count: [ ] [ ] per [ ]SEMI MF523; [ ]JIS H 0614; [ ]SSIS; #3 wafer; [ ] per cm 2 [ ]Other: (specify) Other Front Surface Defects Terracing, Surface microroughness, Nanotopography, and other attributes as discussed between supplier and customer 5-6. POST- ANNEAL BACK SURFACE INSPECTION CHARACTERISTICS As discussed between supplier and customer Contamination/Area [ ]None; [ ]Other: (specify) [ ]SEMI MF523; [ ]JIS H 0614; [ ]Other: (specify) Other Back Surface Defects Support-related back surface defects as discussed between supplier and customer 5-7. OTHER POST-ANNEAL CHARACTERISTICS As discussed between supplier and customer Bulk Iron (Fe) [ ]Not greater than [ ] 10 [ ] atoms/cm 3 [ ]SEMI MF391; [ ]SEMI MF1535; [ ] JEITA EM-3509; [ ]Other: (specify) Depth of BMD Denuded Zone [ ]more than [ ] µm Test Cycle: SEMI MF1239 [ ]A, [ ]B Other: (specify) Determination of DZ Depth [ ] JEITA EM- 3508; Other: (specify) BMD Density Range [ ] 10 [ ] to [ ] 10 [ ] Unit Unit: [ ]cm 2 ; [ ]cm Other Post-Anneal Characteristics Surface boron depletion, dissolved hydrogen in the case of hydrogen annealed wafer, post-annealed oxygen, and silicon nitride precipitates and defects in the case of nitrogen-doped silicon may be discussed between supplier and customer. Test Cycle: SEMI MF1239 [ ]A, [ ]B; Other: (specify) Determination of BMD Density [ ] JEITA EM-3508; Other: (specify) As discussed between supplier and customer. #1 If specified as polished, this term is meant to imply a surface condition and not a particular processing technique. If desired, a quantitative measure of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength) range. Because a standardized test method has not yet been developed for this metric, both values and test procedures, including sampling plan and detrending procedures, shall be agreed upon between supplier and customer. #2 Flatness Acronyms are defined in the Flatness Decision Tree in Appendix 1 of SEMI M1. #3 In today s technology, it may be possible to inspect for some of these items using automated surface scanning inspection systems (SSIS). Such systems should be calibrated according to SEMI M53 using polystyrene latex spheres deposited in accordance with SEMI M58. Some indication of the defects separable by such instruments is provided in SEMI M35; however, a standard test procedure has yet to be developed. Application of automated inspection with the use of an SSIS must be agreed upon between supplier and customer. 5.2 Purchase orders furnished to this guide shall also include the items shown in Table 1 for the finished annealed wafers, and other items as agreed between supplier and customer. 5.3 In addition, the purchase order must indicate the test method to be used in evaluating each of those items for which alternate test procedures exist. 5.4 The following items must also be included in the purchase order: Lot acceptance procedures Certification (if required) Packing and shipping container labeling requirements Page 5 Doc SEMI

7 6 Requirements for Specifying Silicon Annealed Wafers 6.1 Table R1-1 provides a guide for specifying polished silicon annealed wafers for the 180 nm, 130 nm, and 90 nm technology generations. A parameter not listed in this table need not be specified. 6.2 It is also essential to specify appropriate test methods in each case. Defaults for test method selection are given in The line items with numbers beginning with 2- are listed in Part 2 of the Silicon Wafer Specification Format for Order Entry, SEMI M1, Table 1. The line items with numbers beginning with 5- are listed in Part 5 of this format, included herein as Table 1. 7 Sampling 7.1 Unless otherwise specified, ASTM practice E122 shall be used to define the sampling plan. When so specified, appropriate sample sizes shall be selected from each lot in accordance with ANSI/ASQC Z1.4. Each quality characteristic shall be assigned an acceptable quality level (AQL) or lot tolerance percent defective (LTPD) value in accordance with ANSI/ASQC Z1.4 definitions for critical, major, and minor classifications. If desired and so specified in the contract or order, each of these classifications may alternatively be assigned cumulative AQL or LTPD values. Inspection levels shall be agreed upon between the supplier and the purchaser. 8 Test Methods 8.1 Measurements shall be made or certifiable to one of the SEMI, ASTM, JEITA, or JIS, test methods for the item as selected from the Silicon Wafer Specification Format for Order Entry, Parts 2 and 5, located in Table 1 of SEMI M1 and Table 1 herein, respectively, and specified in the purchase order. 8.2 If several different standard test methods for an item are commonly used within a region, it is particularly important that the applicable method of test be identified in the purchase order. 8.3 If no method of test is specified in the purchase order and if standard test methods from different geographic regions are available, the default method shall be a method in common usage for the region of the purchaser of the wafer. 8.4 If no standard test method for an item is available, the test procedure to be used must be agreed upon between supplier and customer. 8.5 Information about the various test methods cited is provided in Related Information 2 of SEMI M1 together with information about some additional test methods no longer in wide use throughout the industry. 9 Certification 9.1 Upon request of the purchaser in the contract or order, a manufacturer s or supplier s certification that the material was manufactured and tested in accordance with this specification, together with a report of the test results, shall be furnished at the time of shipment. 9.2 In the interest of controlling inspection costs, the supplier and the customer may agree that the material shall be certified as capable of meeting certain requirements. In this context, capable of meeting shall signify that the supplier is not required to perform the appropriate tests in 7. However, if the customer performs the test and the material fails to meet the requirement, the material may be subject to rejection. 10 Product Labeling 10.1 The wafers supplied under these specifications shall be identified by appropriately labeling the outside of each box or other container and each subdivision thereof in which it may reasonably be expected that the wafers will be stored prior to further processing. Identification shall include as a minimum the nominal diameter, conductivity type, dopant, orientation, resistivity range, and lot number. The lot number, either (1) assigned by the original manufacturer of the wafers, or (2) assigned subsequent to wafer manufacture but providing reference to the original lot number, shall provide easy access to information concerning the fabrication history of the particular wafers in that lot. Such information shall be retained on file at the manufacturer s facility for at least one month after that particular lot has been accepted by the customer Alternatively, if agreed upon between supplier and customer, one of the box labeling schemes in SEMI T3 shall be used and the information listed in 10.1 that is not included on the label shall be retained in the supplier s database for at least one month after that particular lot has been accepted by the customer. Page 6 Doc SEMI

8 10.3 Wafers of 300 mm diameter shall be shipped in packages labeled in accordance with SEMI M Packing and Shipping Container Labeling 11.1 Special packing requirements shall be subject to agreement between the supplier and customer. Otherwise, all wafers shall be handled, inspected, and packed in such a manner as to avoid chipping, scratches, and contamination and in accordance with the best industry practices to provide ample protection against damage during shipment Wafers of 300 mm diameter shall be shipped in accordance with SEMI M Unless otherwise indicated in the purchase order, all outside wafer shipping containers shall be labeled in accordance with ANSI/EIA 556-B. Page 7 Doc SEMI

9 RELATED INFORMATION 1 GUIDE FOR SPECIFYING POLISHED SILICON ANNEALED WAFERS FOR VARIOUS TECHNOLOGY GENERATIONS FOR THE 180 nm 130 nm AND 90 nm TECHNOLOGY GENERATIONS NOTICE: This Related Information is not an official part of SEMI M57 and was derived from the work of the global Silicon Wafer Technical Committee. This Related Information was approved for publication by full letter ballot procedures on September 12, Table R1-1 Guide for Specifying Polished Silicon Annealed Wafers for the 180 nm, 130 nm, and 90 nm Technology s Item PRE-ANNEAL STATE (POLISHED WAFER) 2-1 GENERAL CHARACTERISTICS 180 nm Technology 130 nm Technology Growth Method Cz or MCz Cz or MCz Cz or MCz Crystal Orientation (100) (100) (100) Conductivity Type p-type p-type p-type Dopant Boron Boron Boron Nominal Edge Exclusion 3 mm 32 mm 2 mm Co-dopant in Crystal None, Nitrogen and/or Carbon (as agreed between supplier & customer) Wafer Surface Orientation On-orientation: 0.00 ± ELECTRICAL CHARACTERISTICS Resistivity (Center point) None, Nitrogen and/or Carbon (as agreed between supplier & customer). On-orientation: 0.00 ± Radial Resistivity Variation #1 20% 20% 20% 2-3 CHEMICAL CHARACTERISTICS Oxygen Concentration/ Calibration Factor 90 nm Technology None, Nitrogen and/or Carbon (as agreed between supplier & customer). On-orientation: 0.00 ± Radial Oxygen Variation #2 ±10%, 10 mm from the edge ±10%, 10 mm from the edge ±10%, 10 mm from the edge Carbon Concentration (Background #3 ) 2-4 STRUCTURAL CHARACTERISTICS 0.5 ppma 0.5 ppma 0.5 ppma Lineage None None None Twin Boundary None None None Swirl None None None 2-5 WAFER PREPARATION CHARACTERISTICS Wafer ID Marking SEMI T7 plus optional and customer SEMI T7 plus alphanumeric mark. optional alphanumeric mark Front Surface Thin Films None None None Extrinsic Gettering None None None Backseal None None None SEMI T7 plus optional alphanumeric mark. Page 8 Doc SEMI

10 Item 2-6 DIMENSIONAL CHARACTERISTICS 180 nm Technology 130 nm Technology 90 nm Technology Diameter mm± 0.20 mm mm ± 0.20 mm # mm ± 0.20 mm # Edge Profile Thickness 725 µm ± 20 µm (Notched type wafers) or 675 µm ± 15 µm (Flatted type wafers) Total Thickness Variation (TTV) 2-8 FRONT SURFACE INSPECTION CHARACTERISTICS 775 µm ± 20 µm 775 µm ± 20 µm 10 µm, max 10 µm, max 10 µm, max Edge Chips None None None 2-9 BACK SURFACE INSPECTION CHARACTERISTICS Edge Chips None None None Brightness (Gloss) Not Specified 0.80 # # # Scratches (macro) cumulative length 5-1 ANNEALING CONDITIONS Annealing Atmosphere Hydrogen, Argon, or Other (as agreed between supplier & customer). POST-ANNEAL STATE 5-2 POST-ANNEAL WAFER PREPARATION CHARACTERISTIC Edge Surface Condition Acid Etched or Polished #6 (as agreed between supplier & customer). 5-3 POST ANNEAL DIMENSIONAL CHARACTERISTICS 0.25 diameter 0.25 diameter 0.25 diameter Hydrogen, Argon, or Other (as agreed between supplier & customer). Acid Etched or Polished #6 (as agreed between supplier & customer) Warp 75 µm 100 µm #7 100 µm #7 Hydrogen, Argon, or Other (as agreed between supplier & customer). Acid Etched or Polished #6 (as agreed between supplier & customer) Site Flatness #8 SFQR 180 nm SFQR 130 nm SFQR 90 nm 5-4 POST-ANNEAL FRONT SURFACE CHEMISTRY #9 (Surface Metal Concentration) Sodium cm cm cm Aluminum cm cm cm Potassium cm cm cm Chromium cm cm cm Iron cm cm cm Nickel cm cm cm Copper cm cm cm Zinc cm cm cm Calcium cm cm cm POST-ANNEAL FRONT SURFACE INSPECTION CHARACTERISTICS Slip Oxidation-Induced Stacking Faults Scratches (macro) None None None Page 9 Doc SEMI

11 Item 5.4 Scratches (micro) total length 180 nm Technology Haze None by Bright Light Inspection. 130 nm Technology 90 nm Technology 0.25 diameter 0.25 diameter 0.25 diameter None by Bright Light Inspection. None by Bright Light Inspection Total Localized Light Scatterers, cm nm LSE 90 nm LSE 90 nm LSE Localized Light Scatterers (COP only), cm Other Front Surface Defects # POST-ANNEAL BACK SURFACE INSPECTION CHARACTERISTICS Contamination/Area Other Back Surface Defects # POST-ANNEAL OTHER CHARACTERISTICS Bulk # Depth of BMD Denuded #13 Zone BMD Density # Other Characteristics #14 #1 Test in accordance with SEMI MF81, Plan B. #2 Test in accordance with SEMI MF951, Plan A1, A2, or A3, as agreed between supplier and customer. #3 The value of background carbon concentration is valid only if the crystal is not intentionally co-doped with carbon (see Item 2-1.7). #4 200 mm diameter wafers may be used, as agreed between supplier #5 Gloss as measured in accordance with ASTM Test Method D 523 or JIS Z 8741 with visible illumination at a 60 angle of incidence referenced to a mirror polished silicon wafer front surface. This metric may not describe the back surface finish adequately to establish detectability of small localized light scatterers (LLSs). If it is necessary to detect LLSs smaller than 0.25 µm LSE, another quantitative measure of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength) range. Because a standardized test method has not yet been developed for this metric, both values and test procedures shall be agreed upon between supplier and customer. #6 If specified as polished, this term is meant to imply a surface condition and not a particular processing technique. If desired, a quantitative measure of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength) range. Because a standardized test method has not yet been developed for this metric, both values and test procedures, including sampling plan and detrending procedures, shall be agreed upon between supplier and purchaser. #7 Warp corrected for gravitational effects. However, warp is not an adequate wafer shape specification for all applications. #8 Determine in accordance with SEMI MF1530 with the following set up parameters: Site size, 26 mm 8 mm; x-offset = 0 mm; and either % usable area = 100% with full sites only or % usable area 95% with partial sites included, as per agreement between supplier and customer. SFQR with a site size of 26 mm 8 mm is approximately equal to SFSR with a site size of 26 mm 32 mm. The smaller site allows more coverage of the FQA than the larger site. The value of site flatness is taken from the ITRS Starting Materials Table. #9 Surface metal measurement variations can be significant. Measurement results are frequently larger than the actual value. Processes are normally controlled with median values to reduce the impact of the measurement variation. #10 Haze, Terracing, Surface micro-roughness, Nanotopography, shallow pits, and other attributes. #11 Back surface defects that relate to the support (such as, chuck etc.) provided to the back surface of the wafer. #12 Bulk iron (Fe) may be characterized by SPV technique. For details, refer to SEMI MF391 or JEITA EM-3509 of sample preparation method for minority carrier diffusion length measurement. 6 6 The development of Sample preparation method for minority carrier diffusion length measurement in silicon annealed wafer by surface photovoltage method (JEITA EM-3509) by JEITA Silicon Technologies Committee is hereby acknowledged. Page 10 Doc SEMI

12 #13 Test method in accordance with JEITA EM Depth of BMD Denuded Zone ( 5-7.2) is used in the same sense as Width of BMD Denuded Zone. #14 Surface boron depletion, dissolved hydrogen in the case of hydrogen annealed wafer, post-annealed oxygen, silicon nitride precipitates and defects in the case of nitrogen-doped silicon. Table R1-2 Guide for Specifying Polished Silicon Annealed Wafers for the 65 nm, 45 nm, and 32 nm Technology s Item PRE-ANNEAL STATE (POLISHED WAFER) 2-1 GENERAL CHARACTERISTICS 65 nm Technology 45nm Technology Growth Method Cz or MCz Cz or MCz Cz or MCz Crystal Orientation (100) (100) (100) Conductivity Type p-type p-type p-type Dopant Boron Boron Boron Nominal Edge Exclusion 2 mm3 mm 2 mm 2 mm Co-dopant in Crystal None, Nitrogen and/or Carbon (as agreed between supplier & customer).none, Nitrogen and/or Carbon (as agreed between supplier & customer) Wafer Surface Orientation On-orientation: 0.00 ± 1.00 Onorientation: 0.00 ± ELECTRICAL CHARACTERISTICS None, Nitrogen and/or Carbon (as agreed between supplier & customer). On-orientation: 0.00 ± nm Technology None, Nitrogen and/or Carbon (as agreed between supplier & customer). On-orientation: 0.00 ± Resistivity (Center point) Customer Specified Customer Specified Customer Specified Radial Resistivity Variation #1 20% 20% 20% 2-3 CHEMICAL CHARACTERISTICS Oxygen Concentration/ Calibration Factor Radial Oxygen Variation #2 ±10%, 10 mm from the edge Carbon Concentration (Background #3 ) 2-4 STRUCTURAL CHARACTERISTICS Customer Specified Customer Specified Customer Specified ±10%, 10 mm from the edge 0.5 ppma 0.5 ppma 0.5 ppma Lineage None None None Twin Boundary None None None Swirl None None None 2-5 WAFER PREPARATION CHARACTERISTICS Wafer ID Marking SEMI T7 plus optional alphanumeric mark. SEMI T7 plus optional alphanumeric mark Front Surface Thin Films None None None Extrinsic Gettering None None None Backseal None None None ±10%, 10 mm from the edge SEMI T7 plus optional alphanumeric mark. 7 The development of Test method for bulk micro defect density and denuded zone width in annealed silicon wafers (JEITA EM-3508) by JEITA Silicon Technologies Committee is hereby acknowledged. Page 11 Doc SEMI

13 Item 2-6 DIMENSIONAL CHARACTERISTICS 65 nm Technology 45nm Technology 32 nm Technology Diameter mm ± 0.20 mm # mm ± 0.20 mm # mm ± 0.20 mm # Edge Profile Customer Specified Customer Specified Customer Specified Thickness 775 µm ± 20 µm 775 µm ± 20 µm 775 µm ± 20 µm Total Thickness Variation (TTV) 2-8 FRONT SURFACE INSPECTION CHARACTERISTICS 4 µm, max 3 µm, max 3 µm, max Edge Chips None None None 2-9 BACK SURFACE INSPECTION CHARACTERISTICS Edge Chips None None None Brightness (Gloss) 0.80 # # # Scratches (macro) cumulative length 5-1 ANNEALING CONDITIONS Macro (None), Micro (Cumulative length 10% of wafer diameter) Annealing Atmosphere Hydrogen, Argon, or Other (Customer Specified) POST-ANNEAL STATE 5-2 POST-ANNEAL WAFER PREPARATION CHARACTERISTIC Edge Surface Condition Acid Etched or Polished #6 (as agreed between supplier & customer). 5-3 POST ANNEAL DIMENSIONAL CHARACTERISTICS Macro (None), Micro (Cumulative length 10% of wafer diameter) Hydrogen, Argon, or Other (Customer Specified) Acid Etched or Polished #6 (as agreed between supplier & customer) Warp 100 µm #7 100 µm #7 100 µm #7 Macro (None), Micro (Cumulative length 10% of wafer diameter) Hydrogen, Argon, or Other (Customer Specified) Acid Etched or Polished #6 (as agreed between supplier & customer) Site Flatness #8 SFQR 65 nm SFQR 45 nm SFQR 32 nm 5-4 POST-ANNEAL FRONT SURFACE CHEMISTRY #9 (Surface Metal Concentration) Sodium cm cm cm Aluminum cm cm cm Potassium cm cm cm Chromium cm cm cm Iron cm cm cm Nickel cm cm cm Copper cm cm cm Zinc cm cm cm Calcium cm cm cm POST-ANNEAL FRONT SURFACE INSPECTION CHARACTERISTICS Slip (Customer Specified) (Customer Specified) (Customer Specified) Oxidation-Induced Stacking (Customer Specified) (Customer Specified) (Customer Specified) Faults Scratches (macro) None None None 5.4 Scratches (micro) total length Haze None by Bright Light Inspection diameter 0.10 diameter 0.10 diameter None by Bright Light Inspection. None by Bright Light Inspection. Page 12 Doc SEMI

14 Item 65 nm Technology 45nm Technology Total Localized Light 90 nm LSE 0.50 cm 65 nm Scatterers #10, cm 2 LSE 32 nm Technology 0.50 cm 65 nm LSE Localized Light Scatterers (COP only), cm 2 (Customer Specified) (Customer Specified) (Customer Specified) Other Front Surface Defects #10 (Customer Specified) (Customer Specified) (Customer Specified) 5-6 POST-ANNEAL BACK SURFACE INSPECTION CHARACTERISTICS Contamination/Area (Customer Specified) (Customer Specified) (Customer Specified) Other Back Surface Defects #11 (Customer Specified) (Customer Specified) (Customer Specified) 5-7 POST-ANNEAL OTHER CHARACTERISTICS Bulk #12 (Customer Specified) (Customer Specified) (Customer Specified) Depth of BMD Denuded #13 (Customer Specified) (Customer Specified) (Customer Specified) Zone BMD Density #13 (Customer Specified) (Customer Specified) (Customer Specified) Other Characteristics #14 (Customer Specified) (Customer Specified) (Customer Specified) #1 Test in accordance with SEMI MF81, Plan B. #2 Test in accordance with SEMI MF951, Plan A1, A2, or A3, as agreed between supplier and customer. #3 The value of background carbon concentration is valid only if the crystal is not intentionally co-doped with carbon (see Item 2-1.7). #4 200 mm diameter wafers may be used, as agreed between supplier #5 Gloss as measured in accordance with ASTM Test Method D 523 or JIS Z 8741 with visible illumination at a 60 angle of incidence referenced to a mirror polished silicon wafer front surface. This metric may not describe the back surface finish adequately to establish detectability of small localized light scatterers (LLSs). If it is necessary to detect LLSs smaller than 0.25 µm LSE, another quantitative measure of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength) range. Because a standardized test method has not yet been developed for this metric, both values and test procedures shall be agreed upon between supplier and customer. #6 If specified as polished, this term is meant to imply a surface condition and not a particular processing technique. If desired, a quantitative measure of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength) range. Because a standardized test method has not yet been developed for this metric, both values and test procedures, including sampling plan and detrending procedures, shall be agreed upon between supplier and purchaser. #7 Warp corrected for gravitational effects. However, warp is not an adequate wafer shape specification for all applications. #8 Determine in accordance with SEMI MF1530 with the following set up parameters: Site size, 26 mm 8 mm; x-offset = 0 mm; and either % usable area = 100% with full sites only or % usable area 95% with partial sites included, as per agreement between supplier and customer. SFQR with a site size of 26 mm 8 mm is approximately equal to SFSR with a site size of 26 mm 32 mm. The smaller site allows more coverage of the FQA than the larger site. The value of site flatness is taken from the ITRS Starting Materials Table. #9 Surface metal measurement variations can be significant. Measurement results are frequently larger than the actual value. Processes are normally controlled with median values to reduce the impact of the measurement variation. #10 Hazes, Terracing, Surface micro-roughness, Nanotopography, shallow pits, and other attributes. #11 Back surface defects that relate to the support (such as, chuck etc.) provided to the back surface of the wafer. #12 Bulk iron (Fe) may be characterized by SPV technique. For details, refer to SEMI MF391 or JEITA EM-3509 of sample preparation method for minority carrier diffusion length measurement. 8 #13 Test method in accordance with JEITA EM Depth of BMD Denuded Zone ( 5-7.2) is used in the same sense as Width of BMD Denuded Zone. #14 Surface boron depletion, dissolved hydrogen in the case of hydrogen annealed wafer, post-annealed oxygen, silicon nitride precipitates and defects in the case of nitrogen-doped silicon. 8 The development of Sample preparation method for minority carrier diffusion length measurement in silicon annealed wafer by surface photovoltage method (JEITA EM-3509) by JEITA Silicon Technologies Committee is hereby acknowledged. 9 The development of Test method for bulk micro defect density and denuded zone width in annealed silicon wafers (JEITA EM-3508) by JEITA Silicon Technologies Committee is hereby acknowledged. Page 13 Doc SEMI

15 Table R1-3 Guide for Specifying Polished Silicon Annealed Wafers for the 22 nm Technology PRE-ANNEAL STATE (POLISHED WAFER) 2-1 GENERAL CHARACTERISTICS Growth Method Cz or MCz Crystal Orientation (100) Conductivity Type p-type Dopant Boron Nominal Edge Exclusion 2 mm Item 22 nm Technology Co-dopant in Crystal None, Nitrogen and/or Carbon (as agreed between supplier & customer).none, Nitrogen and/or Carbon (as agreed between supplier & customer) Wafer Surface Orientation On-orientation: 0.00 ± 1.00 On-orientation: 0.00 ± ELECTRICAL CHARACTERISTICS Resistivity (Center point) Customer Specified Radial Resistivity Variation #1 20% 2-3 CHEMICAL CHARACTERISTICS Oxygen Concentration/ Calibration Factor Customer Specified Radial Oxygen Variation #2 ±10%, 10 mm from the edge Carbon Concentration (Background #3 ) 0.5 ppma Lineage None Twin Boundary None Swirl None 2-5 WAFER PREPARATION CHARACTERISTICS Wafer ID Marking SEMI T7 plus optional alphanumeric mark Front Surface Thin Films None Extrinsic Gettering None Backseal None Edge Surface Condition Polished Back Surface Condition Polished 2-6 DIMENSIONAL CHARACTERISTICS Diameter mm ± 0.20 mm # Primary Flat/Notch Orientation <110> ± 1º Edge Profile Customer Specified Thickness 775 ± 20µm GBIR 3µm max 2-9 BACK SURFACE INSPECTION CHARACTERISTICS Edge Chips None Brightness (Gloss) 0.80 #5 Page 14 Doc SEMI

16 Item 22 nm Technology Scratches Macro (None), Micro (Cumulative length 10% of wafer diameter) 5-1 ANNEALING CONDITIONS Annealing Atmosphere Hydrogen, Argon, or Other (Customer Specified) POST-ANNEAL STATE 5-2 POST-ANNEAL WAFER PREPARATION CHARACTERISTIC Edge Surface Condition Polished #6 (customer Specified) 5-3 POST ANNEAL DIMENSIONAL CHARACTERISTICS Warp #7 100 µm Site Flatness #8 SFQR 22 nm 5-4 POST-ANNEAL FRONT SURFACE CHEMISTRY #9 (Surface Metal Concentration) Sodium cm Aluminum cm Potassium cm Chromium cm Iron cm Nickel cm Copper cm Zinc cm Calcium cm POST-ANNEAL FRONT SURFACE INSPECTION CHARACTERISTICS Slip Customer Specified Item 22 nm Technology Oxidation-Induced Stacking Faults Customer Specified Scratches (macro) None Scratches (micro) total length 0.10 diameter Haze None by Bright Light Inspection Total Localized Light Scatterers #10, cm Localized Light Scatterers (COP only), cm cm 32 nm LSE Customer Specified Other Front Surface Defects Customer Specified Scratches (macro) None 5-6 POST-ANNEAL BACK SURFACE INSPECTION CHARACTERISTICS Contamination/Area Customer Specified Other Back Surface Defects #11 Customer Specified 5-7 POST-ANNEAL OTHER CHARACTERISTICS Bulk #12 Customer Specified Depth of BMD Denuded #13 Zone Customer Specified BMD Density #13 Customer Specified Other Characteristics #14 Customer Specified Page 15 Doc SEMI

17 #1 Test in accordance with SEMI MF81, Plan B. #2 Test in accordance with SEMI MF951, Plan A1, A2, or A3, as agreed between supplier and customer. #3The value of background carbon concentration is valid only if the crystal is not intentionally co-doped with carbon (see Item 2-1.7). #4 200 mm diameter wafers may be used, as agreed between supplier #5 Gloss as measured in accordance with ASTM Test Method D 523 or JIS Z 8741 with visible illumination at a 60 angle of incidence referenced to a mirror polished silicon wafer front surface. This metric may not describe the back surface finish adequately to establish detectability of small localized light scatterers (LLSs). If it is necessary to detect LLSs smaller than 0.25 µm LSE, another quantitative measure of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength) range. Because a standardized test method has not yet been developed for this metric, both values and test procedures shall be agreed upon between supplier and customer. #6If specified as polished, this term is meant to imply a surface condition and not a particular processing technique. If desired, a quantitative measure of surface finish may optionally be indicated by specifying the rms microroughness over a specified spatial frequency (or wavelength) range. Because a standardized test method has not yet been developed for this metric, both values and test procedures, including sampling plan and detrending procedures, shall be agreed upon between supplier and purchaser. #7 Warp corrected for gravitational effects. However, warp is not an adequate wafer shape specification for all applications. #8 Determine in accordance with SEMI MF1530 with the following set up parameters: Site size, 26 mm 8 mm; x-offset = 0 mm; and either % usable area = 100% with full sites only or % usable area 95% with partial sites included, as per agreement between supplier and customer. SFQR with a site size of 26 mm 8 mm is approximately equal to SFSR with a site size of 26 mm 32 mm. The smaller site allows more coverage of the FQA than the larger site. The value of site flatness is taken from the ITRS Starting Materials Table. #9 Surface metal measurement variation can be significant. Measurement results are frequently larger than the actual value. Processes are normally controlled with median values to reduce the impact of the measurement variation. #10The counts are from the ITRS table. The count may be transformed to a count at another size using ISO , which uses the equation: count per wafer at x nm = (count per wafer at y nm)*(y nm/x nm) The count may include other structural defects that are not correctly sized by current generation SSISs. #11Back surface defects that relate to the support (such as, chuck etc.) provided to the back surface of the wafer. #12 Bulk iron (Fe) may be characterized by SPV technique. For details, refer to SEMI MF391 or JEITA EM-3509 of sample preparation method for minority carrier diffusion length measurement. 10 #13 Test method in accordance with JEITA EM Depth of BMD Denuded Zone ( 5-7.2) is used in the same sense as Width of BMD Denuded Zone. #14 Surface boron depletion, dissolved hydrogen in the case of hydrogen annealed wafer, post-annealed oxygen, silicon nitride precipitates and defects in the case of nitrogen-doped silicon. 8 The development of Sample preparation method for minority carrier diffusion length measurement in silicon annealed wafer by surface photovoltage method (JEITA EM-3509) by JEITA Silicon Technologies Committee is hereby acknowledged. 11 The development of Test method for bulk micro defect density and denuded zone width in annealed silicon wafers (JEITA EM-3508) by JEITA Silicon Technologies Committee is hereby acknowledged. Page 16 Doc SEMI

18 NOTICE: Semiconductor Equipment and Materials International (SEMI) makes no warranties or representations as to the suitability of the Standards and Safety Guidelines set forth herein for any particular application. The determination of the suitability of the Standard or Safety Guideline is solely the responsibility of the user. Users are cautioned to refer to manufacturer s instructions, product labels, product data sheets, and other relevant literature, respecting any materials or equipment mentioned herein. Standards and Safety Guidelines are subject to change without notice. By publication of this Standard or Safety Guideline, SEMI takes no position respecting the validity of any patent rights or copyrights asserted in connection with any items mentioned in this Standard or Safety Guideline. Users of this Standard or Safety Guideline are expressly advised that determination of any such patent rights or copyrights, and the risk of infringement of such rights are entirely their own responsibility. Page 17 Doc SEMI