INTEGRATED-CIRCUIT TECHNOLOGY

Transcription

1 INTEGRATED-CIRCUIT TECHNOLOGY 0. Silicon crystal growth and wafer preparation 1. Processing Steps 1.1. Photolitography 1.2. Oxidation 1.3. Layer Deposition 1.4. Etching 1.5. Diffusion 1.6 Backend: assembly, test 2. Bipolar Technology 3. CMOS Technology 1

2 CRYSTAL GROWTH Czochralski Process is a Technique in Making Single-Crystal Silicon A Solid Seed Crystal is Rotated and Slowly Extracted from a Pool of Molten Si Requires Careful Control to Give Crystals Desired Purity and Dimensions 2

3 silicon wafer Wafer Slicing & Polishing p+ silicon substrate The silicon ingot is grown and individual wafers are sliced. The silicon ingot is sliced into individual wafers, polished, and cleaned. 3

4 Photoresist Coating Processes photoresist field oxide p- epi p+ substrate Photoresists Negative Photoresist * Positive Photoresist * Other Ancillary Materials (Liquids) Edge Bead Removers * Anti-Reflective Coatings * Adhesion Promoters/Primers (HMDS) * Rinsers/Thinners/Corrosion Inhibitors * Contrast Enhancement Materials * Developers TMAH * Specialty Developers * Inert Gases Ar N 2 4

5 Exposure Processes photoresist field oxide p- epi p+ substrate Expose Kr + F 2 (gas) * Inert Gases N 2 5

6 1. Photolitography Basic Concept Photolitography Basic Concept 6

7 Photolitography using positive photoresist 7

8 The simplest method of producing an oxide layer consists of heating a silicon wafer in an oxidizing atmosphere. 8

9 Oxidation of the silicon surface 9

10 Times required to grow 0.1µm of oxide on (III) silicon Ambient 800 C 900 C 1000 C 1100 C 1200 C Dry O 2 30h 6h 1.7h 40min 15min Wet O 2 1.7h 20min 6min Silicon Melting Point, 1410 C 10

11 Selective SiO 2 growth, using local oxidation 11

12 Vapor deposition. PVD (a) and CVD(b). 12

13 Metal 1 Chemical Vapor Deposition (CVD) Dielectric insulator layer 2 Metering Pump Inert Mixing Gas CVD Dielectric O 2 O 3 TEOS * TMP * n-w ell p-w ell p-channel transistor n-channel transistor p+ substrate TEOS Source Chemical Reactions Si(OC 2 H 5 ) O 3 SiO CO + 3 CO H 2 O Process Conditions (ILD) Flow Rate: 100 to 300 sccm Pressure: 50 Torr to Atmospheric LPCVD Chamber Transfer Chamber Direct Liquid Injection Vaporizer Process Gas Gas Inlet Wafer RF Power Exhaust * High proportion of the total product use 13

14 Epitaxy and mechanisms of defect formation in the epitaxial layer 14

15 Epitaxial Silicon Deposition silicon wafer p- silicon epi layer p+ silicon substrate Susceptor Gas Input Lamp Module Chemical Reactions Silicon Deposition: HSiCl 3 + H 2 Si + 3 HCl Process Conditions Flow Rates: 5 to 50 liters/min Temperature: 900 to 1,100 degrees C. Pressure: 100 Torr to Atmospheric Quartz Lamps Wafers Silicon Sources SiH 4 H 2 SiCl 2 HSiCl 3 * SiCl 4 * Dopants AsH 3 B 2 H 6 PH 3 Etchant HCl Carriers Ar H 2 * N 2 Exhaust * High proportion of the total product use 15

16 Wet etching. 16

17 Dry etching. 17

18 gate linew idth n-w ell p-w ell p-channel transistor n-channel transistor p+ substrate Conductor Etch source-drain areas gate oxide Chemical Reactions Silicon Etch: Si + 4 HBr SiBr H 2 Aluminum Etch: Al + 2 Cl 2 AlCl 4 Process Conditions Flow Rates: 100 to 300 sccm Pressure: 10 to 500 mtorr RF Power: 50 to 100 Watts Polysilicon Etches HBr * C 2 F 6 SF 6 * NF 3 * O 2 Aluminum Etches BCl 3 * Cl 2 Diluents Ar He N 2 Cluster Tool Configuration Wafers RIE Chamber Transfer Chamber Exhaust * High proportion of the total product use Etch Chambers Transfer Chamber Loadlock Gas Inlet Wafer RF Power 18

19 Contact locations n-w ell p-w ell p-channel transistor n-channel transistor p+ substrate Dielectric Etch Cluster Tool Configuration Wafers Chemical Reactions Oxide Etch: SiO 2 + C 2 F 6 SiF 4 + CO 2 + CF CO Process Conditions Flow Rates: 10 to 300 sccm Pressure: 5 to 10 mtorr RF Power: 100 to 200 Watts RIE Chamber Etch Chambers Transfer Chamber Loadlock Gas Inlet Plasma Dielectric Etches CHF 3 * CO 2 CF 4 O 2 C 2 F 6 SF 6 C 3 F 8 SiF 4 CO * Diluents Ar He N 2 Transfer Chamber Exhaust * High proportion of the total product use Wafer RF Power 19

20 Diffusion mechanism 20

21 Representative junction depths, in microns (10 20 atoms/cm 3 source, atoms/cm 3 background, 15min predeposition, 1h drive-in) Dopant 950 C 1000 C 1100 C 1200 C Boron Phosphorus Antimony Arsenic

22 Diffusion of dopants through a window in the SiO 2 layer. 22

23 Ion Implantation Focus Beam trap and gate plate Neutral beam and beam path gated junction depth Gases Ar AsH 3 B 11 F 3 * He N 2 PH 3 SiH 4 SiF 4 GeH 4 phosphorus (-) ions n-w ell p- epi p-channel transistor p+ substrate Solids Ga In Sb Liquids Al(CH 3 ) 3 photoresist mask Process Conditions Flow Rate: 5 sccm Pressure: 10-5 Torr Accelerating Voltage: 5 to 200 kev field oxide Neutral beam trap and beam gate Resolving Aperture Y - axis scanner X - axis scanner Equipment Ground 180 kv Acceleration Tube 90 Analyzing Magnet Terminal Ground Wafer in wafer process chamber Ion Source 20 kv * High proportion of the total product use 23

24 Chemical Mechanical Planarization (CMP) n-w ell p-w ell p-channel transistor n-channel transistor p+ substrate Process Conditions (Oxide) Flow: 250 to 1000 ml/min Particle Size: 100 to 250 nm Concentration: 10 to 15%, 10.5 to 11.3 ph Process Conditions (Metal) Flow: 50 to 100 ml/min Particle Size: 180 to 280 nm Concentration: 3 to 7%, ph Backing (Carrier) Film Polyurethane Pad Polyurethane Pad Conditioner Abrasive CMP (Oxide) Silica Slurry * KOH * NH 4 OH H 2 O CMP (Metal) Alumina * FeNO 3 Head Sweep Slide Load/Unload Station Wafer Handling Robot & I/O Wafer Wafer Carrier Polishing Pad Platen Polishing Head Pad Conditioner Carousel Platen * High proportion of the total product use. 24 Slurry Delivery

25 Electrical Test Probe Metal 2 bonding pad nitride n-well p-well p-channel transistor n-channel transistor p+ substrate Defective IC Individual integrated circuits are tested to distinguish good die from bad ones. 25

26 Good chips are attached to a lead frame package. Die Cut and Assembly 26

27 Die Attach and Wire Bonding lead frame gold wire bonding pad connecting pin 27

28 Chips are electrically tested under varying environmental conditions. Final Test 28

29 2. Bipolar Technology Diffusion of the buried layer. Segment of the mask (a) and cross-section of the npn transistor (b) after the diffusion. 29

30 Island formation. Segment of the mask (a) and cross-section of the npn transistor (b) after diffusion of the p-type isolation. 30

31 Transistor base p-type diffusion. Segment of the mask (a) and cross-section of the npn transistor (b) after base diffusion 31

32 Emitter diffusion. Segment of the mask (a) and cross-section of the npn transistor (b) after emitter diffusion. 32

33 Layout (a) and cross-section of the complete npn transistor (b). 33

34 3. CMOS Technology Active regions in the n-well CMOS inverter. Edges of active regions in the mask (a) and cross-section of the inverter (b). 34

35 Polysilicon region in the n-well CMOS inverter. Window in the mask (a) and cross-section of the inverter (b). 35

36 Implantation of n-channel transistor drain and source. Window in the n-select mask (a) and cross-section of the inverter (b). 36

37 CMOS inverter. Composite layout (a), cross-section (b), and electrical diagram (c). 37

38 References 1. W. Maly, Atlas of IC Technologies, Benjamin/Cummings Publications, Conrad T. Sorenson, Semiconductor Manufacturing Technology: Semiconductor Manufacturing Processes, MME%20Modules/Manufacturing%20Module/Manufac%20Overview.p pt 3. Young Soon Song. et. al., EE Semiconductor Electronics Design Project. Silicon Manufacturing, 38