(12) United States Patent (10) Patent No.: US 8,102,006 B2

Transcription

1 UOO B2 (12) United tate Patent (10) Patent No.: U 8,102,006 B2 Zhou (45) Date of Patent: Jan. 24, 2012 (54) DIFFERENT GATE OXIDE THICKNEE 6,475,862 B1 * 1 1/2002 Ando ,264 FOR DIFFERENT TRANITOR IN AN 3.k R 2. Male - ww. aegawa INTEGRATED CIRCUIT 6,602,751 B2 * 8/2003 Oohahi ,275 6,711,538 B1 3, 2004 O i et al. (75) Inventor: Xianfeng Zhou, Meridian, ID (U) 6,734,113 B1* 5/2004 t a ,794,708 B2 * 9/2004 Mori ,314 (73) Aignee: Micron Technology, Inc., Boie, ID 6,816,432 B2 * 1 1/2004 Feurleet al , (U) 6,906,954 B2 6/2005 hukuri et al. 7,030,012 B2 4, 2006 Divakaruni et al. (*) Notice: ubject to any diclaimer, the term of thi 78. E: 39: he al. patent i extended or adjuted under 35 7,091,079 B2 * 8/2006 Chen et al /199 U..C. 154(b) by 0 day. 7,118,974 B2 * 10/2006 Chen et al ,287 7,214,590 B2 5/2007 Lim et al. 7, B2 11/2007 Lee et al. (21) Appl. No.: 12/851,278 7,348,245 B2 3/2008 hinohara et al. 7,351,632 B2 4/2008 Viokay et al. (22) Filed: Aug. 5, ,428, 167 B2 9/2008 hukuri et al. 7,511,331 B2 * 3/2009 Anezaki ,315 (65) Prior Publication Data 7,790,544 B2 * 9/2010 Zhou , / A1 11/2002 Mauoka U 2010/O A1 Nov. 25, 2010 (Continued) Related U.. Application Dat e pplication Uata FOREIGN PATENT DOCUMENT (62) Diviion of application No. 1 1/387,707, filed on Mar. EP 1 OO5 O79 11, , 2006, now Pat. No. 7,790,544. (Continued) (51) Int. Cl. HOIL 2L/70 ( ) Primary Examiner Alonzo Chambli (52) U.. Cl , / /E (74) Attorney, Agent, or Firm Dicktein hapiro LLP 257/E29.04; 257/E29.051; 257/E ABTRACT (58) Field of Claification earch... None (57) ee application file for complete earch hitory. An integrated circuit and gate oxide forming proce are dicloed which provide a gate tructure that i imple to (56) Reference Cited integrate with conventional fabrication procee while pro U.. PATENT DOCUMENT viding different gate oxide thicknee for different trani tor within the integrated circuit. For a flah memory, which 5,723,355 A * 3/1998 Chang et al ,275 may utilize the invention, the different gate oxide thicknee 5. k A 1858 EMet al. may be ued for lower Voltage tranitor, memory array A * Carn et al ,264 tranitor, and higher Voltage tranitor. 6, 198,140 B1* 3/2001 Muramoto et al ,392 6,274,430 B1 8, 2001 Janet al. 11 Claim, 12 Drawing heet -50 f 100 f000 f f f {- UBTRATE MEMORY i2 VAREA HVAREA AREA ff

2 U 8,102,006 B2 Page 2 U.. PATENT DOCUMENT 2006/ A1 9, 2006 Kim et al. 2003/ A1 6/2003 Kobayahi FOREIGN PATENT DOCUMENT 2004/ A1 2/2004 Mauoka ck 2005, A1 2/2005 Kim et al. JP O A * 12/ / A1* 3/2005 Layman et al /199 P , / A1 11, 2005 Lee * cited by examiner

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15 1. DIFFERENT GATE OXDE THICKNEE FOR DIFFERENT TRANITOR IN AN INTEGRATED CIRCUIT CRO-REFERENCE TO RELATED APPLICATION Thi application i a diviional of U.. patent application er. No. 1 1/387,707, filed on Mar. 24, 2006, now U.. Pat. No. 7,790,544 the ubject matter of which i incorporated in it entirety by reference herein. FIELD OF THE INVENTION Thi invention relate generally to the fabrication of emi conductor device and, more pecifically, to a method of forming gate oxide tructure. BACKGROUND OF THE INVENTION emiconductor memory device for toring data can typi cally be categorized a either Volatile memory device or nonvolatile memory device. Volatile memory device loe their tored data when their power upplie are interrupted; nonvolatile memory device, however, retain their tored data even when their power upplie are interrupted. There are variou type of nonvolatile memorie including e.g., electri cally programmable read only memorie (EPROM), and electrically eraable programmable read only memorie (EE PROM). One type of EEPROM device i a flah EEPROM device (alo referred to a flah memory'). Nonvolatile memory device e.g., flah memory, have become widely ued for torage application. A conventional flah memory device include a plurality of memory cell, each cell having a floating gate covered with an inulating layer. Below the floating gate i another inulating layer andwiched between the floating gate and the cell ub trate. Thi inulating layer i an oxide layer and i often referred to a the tunnel oxide. The ubtrate contain doped ource and drain region, with a channel region dipoed between the ource and drain region. In one conventional proce for forming flah memory, memory cell and low Voltage logic tranitor (e.g., MO FET) hare the ame gate oxide a memory cell tranitor in order to implify the proce and reduce fabrication cot. The thickne of thi gate oxide typically i between 70-90A to maintain proper data retention for the memory cell trani tor. However, thi gate oxide thickne limit the perfor mance of the logic tranitor which ideally hould have a thinner gate oxide for high performance. A flah memory alo typically ha high Voltage tranitor which require a thicker gate oxide than that ued for the memory cell and logic tranitor. A thinner gate oxide for the logic tranitor would require a triple oxide thickne proce that include a 30-50A thick gate oxide for logic tranitor, a 70-90A thick gate oxide a tunnel oxide for memory cell, and a A thick gate oxide for high Voltage tranitor. Fabricating gate oxide having there different thicknee not only increae the complexity of the proce flow, but alo introduce tunnel oxide quality concern becaue, baed on the exiting con ventional multiple oxide procee, one ha to grow a tunnel oxide in everal oxidation tep with many patterning and reit trip tep in between. BRIEF UMMARY OF THE INVENTION The invention relate to a gate oxide tructure and a pro ce for forming the gate tructure in an integrated circuit U 8, 102,006 B having different oxide thicknee correponding to different type of tranitor in the integrated circuit. In one exemplary embodiment, the invention provide different gate oxide thicknee for the tranitor in low voltage area, the high Voltage area and the memory array area of a memory device to better tailor tranitor performance. The inventive method and reulting tructure are particularly uitable for fabricating flah memory device. BRIEF DECRIPTION OF THE DRAWING The foregoing and other advantage and feature of the invention will become more apparent from the detailed decription of exemplary embodiment provided below with reference to the accompanying drawing in which: FIG. 1 i a diagram illutrating an exemplary flah memory cell; FIG. 2 how a cro ectional view of gate tructure for different tranitor of a non-volatile memory device con tructed in accordance with an exemplary embodiment of the invention; FIG.3 how a cro ectional view of a ubtrate during an early fabrication tage in accordance with the exemplary embodiment of the invention; FIG. 4 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 3; FIG. 5 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 4; FIG. 6 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 5; FIG. 7 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 6; FIG. 8 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 7: FIG. 9 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 8: FIG. 10 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG.9; FIG. 11 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 10; FIG. 12 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 11; FIG. 13 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 12; FIG. 14 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 13; FIG. 15 how a cro ectional view of a ubtrate at an early fabrication tage in accordance with another exemplary embodiment of the invention; FIG.16 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 15: FIG. 17 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 16; FIG. 18 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 17: FIG. 19 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 18; FIG. 20 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 19: FIG. 21 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 20; FIG. 22 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG. 21; FIG. 23 how a cro ectional view of the ubtrate at a fabrication tage ubequent to FIG.22; and

16 3 FIG. 24 how a proceor ytem incorporating at leat one gate tructure contructed in accordance with the exem plary embodiment of the invention. DETAILED DECRIPTION OF THE INVENTION In the following detailed decription, reference i made to the accompanying drawing which form a part hereof, and in which i hown by way of illutration pecific embodiment by which the invention may be practiced. It hould be under tood that like reference numeral repreent like element throughout the drawing. Thee exemplary embodiment are decribed in ufficient detail to enable thoe killed in the art to practice the invention. It i to be undertood that other embodiment may be utilized, and that tructural, logical and electrical change may be made without departing from the pirit and cope of the preent invention. The progreion of proceing tep decribed i exemplary of embodiment of the invention; however, the equence of tep i not limited to that et forth herein and may be changed a i known in the art, with the exception of tep necearily occurring in a certain order. The term ubtrate' i to be undertood a including all form of emiconductor wafer and ubtrate including, ili con, ilicon-on-inulator (OI), ilicon-on-apphire (O). doped and undoped emiconductor, epitaxial layer of ili con upported by a bae emiconductor foundation, and other emiconductor tructure. Furthermore, when reference i made to a ubtrate in the following decription, previou proce tep may have been utilized to form region or junc tion in or above the bae emiconductor tructure or foun dation. In addition, the emiconductor need not be ilicon baed, but could be baed on other emiconductor, for example, ilicon-germanium, germanium, or gallium ar enide. The invention i decribed below with repect to forming gate oxide tructure for different type of tranitor employed in a flah memory, however, the invention i not limited to flah memory and may be ued to fabricated any integrated circuit where different gate oxide thicknee may be deired for different type of tranitor. FIG. 1 illutrate an exemplary flah memory cell 50 hav ing a gate tructure. The cell 50 ha a tack-gate configuration and comprie a ubtrate 52 that may be doped with a p-type dopant to form a p-type ubtrate 52. Alternatively, the ub trate 52 may be doped with an n-type dopant to forman-type ubtrate 52, if o deired. The cell 50 include ource and drain region 54, 56 formed within the ubtrate 52. If the ubtrate 52 ha been doped with a p-type dopant, then the ource and drain region 54, 56 are created by implanting the ubtrate 52 with an n-type dopant to form N-- region 54, 56. If, on the other hand, the ubtrate 52 ha been doped with a n-type dopant, then the ource and drain region 54, 56 are created by implanting the ubtrate 52 with an p-type dopant to form P+ region 54, 56. The ource region 54 i paced apart from the drain region 56 to form a channel region 58 between the ource and drain region 54, 56. A tunnel oxide layer 60 i located on the urface of the ubtrate 52. The tunnel oxide layer 60 com prie a dielectric material uch a e.g., ilicon dioxide, over the urface of the ubtrate 52. A floating gate 62 i formed over the tunnel oxide 60. The floating gate 62 i a conductive material and may be e.g., polyilicon. An inulating layer 64 i poitioned on top of the floating gate 62. The inulating layer 64 comprie a dielec tric material uch a e.g., ilicon dioxide. The control gate 66 i formed over the inulating layer 64. The control gate 66 i U 8, 102,006 B a conductive layer and may be a polyilicon layer. In flah memory integrated circuit, memory cell having the general tranitor contruction illutrated in FIG. 1 are employed along with low Voltage logic tranitor and high Voltage power tranitor, both of which have ource/drain region in the ubtrate, and a gate tructure between the ource/drain region which include a gate oxide, and a control gate over the gate oxide. Method of forming different gate oxide thicknee for the memory array tranitor, low Voltage tranitor and high voltage tranitor i now decribed with reference to FIG FIG. 2 i a implified cro ectional view of gate tructure for different tranitor in different region of a flah memory device contructed in accordance with the exemplary embodiment of the invention decribed below. FIG. 2 how gate tructure for memory cell tranitor, low Voltage logic tranitor (LV area), and high Voltage power tranitor (HV area). FIG. 2 illutrate the gate tructure ubequent to the fabrication tage hown in FIG but prior to the remaining fabrication tage ued to complete the formation of the tranitor. A hown in FIG. 2, low voltage logic tranitor have a gate tructure compriing a gate oxide layer 170, a polyilicon control gate layer 150, and an over lying nitride layer 140. The high voltage tranitor have a gate tructure compriing a gate oxide layer 420, a polyilicon control gate layer 160 and a nitride layer 1000, and the memory array tranitor compriing a gate oxide layer 840, floating gate layer 850 and nitride layer The gate oxide 170 i the thinnet gate oxide and may have a thickne in the range of about 30 A to about 50A, the gate oxide 420 i the thicket gate oxide and may have a thickne in the range of about 350 A to about 400A, and the memory array gate oxide 840 ha a thickne between that of gate oxide 170 and gate oxide 420 and may have a thickne in the range of about 70 A to about 90 A. FIG illutrate the fabrication tage for forming the FIG.2 tranitorgate tructure in accordance with one embodiment of the invention. Referring now to FIG. 3, a ubtrate 52 compriing a memory array area 110, a high voltage (HV) area 120 and a low voltage (LV) area 130 i illutrated. Typically, a acrificial oxide layer (not hown), uually a thin layer of ilicon diox ide, i an initial oxide layer depoited on the urface of the ubtrate 52 and then removed from the urface of the ub trate 52. ubequent to the removal of the acrificial oxide layer, a layer of gate oxide 170 i depoited or grown and then a layer of polyilicon 150 i depoited over the gate oxide layer 170. A nitride hard mak layer 140 i depoited over the layer of polyilicon 150. Referring to FIG. 4, a layer of photoreit 210 i electively depoited above nitride hard mak layer 140 in a region over the low voltage area 130, leaving the layer above the high Voltage and memory array area 120, 110 expoed and uncovered. Referring to FIG. 5, a reactive ion etch (RIE) i ued to remove the nitride hard mak layer 140 and the polyilicon layer 150 and gate oxide layer 170 from over the high voltage and memory array area 120, 110. Afterward, the photoreit 210 (FIG. 4) i removed. Referring to FIG. 6, a gate oxide layer 420 i thermally grown over the HV and memory array area 120, 110, while the remaining nitride hard mak 140 protect the remaining polyilicon layer 150 and gate oxide layer 170 above the LV area 130. The nitride hard mak layer 140 i next removed from over the low voltage area 130 uing a wet or dry etch (FIG. 7). till referring to FIG. 7, photoreit 630 i elec tively applied above polyilicon layer 150 and gate oxide layer 420 in the high voltage and low voltage area 120, 130 expoing the gate oxide 420 over the memory array. Then, a wet or dry etch i conducted to remove the gate oxide layer

17 5 420 from above the memory array area 110. A hown in FIG. 8, the gate oxide layer 420 from above the memory array area 110 i removed, a i the photoreit 630 (FIG. 7). A thin gate oxide layer 840 i next grown above the memory array area 110 a hown in FIG. 9. A a reult of growing the thin gate oxide layer 840, expoed gate oxide layer 420 will continue to thicken. Meanwhile, the gate oxide layer above the low voltage area 130 continue to be protected by the polyilicon layer 150. In addition, oxide layer 860 i grown on the polyilicon layer 150 in the low voltage area 130. ubequently, a layer of polyilicon 870 i depoited above all of the gate oxide layer 170, 840, 860 to form a floating gate for the memory array tranitor. Referring to FIG. 10, a photoreit 1050 i formed above the urface of polyilicon layer 870 in the high voltage and memory array area 120, 110. A a reult, the layer 150, 170, 860, 870 above the low voltage area 130 are left expoed. Referring to FIG. 11, the polyilicon layer 870 and the oxide layer 860 are removed from above the low voltage area 130 uing dry or wet etch method. The photoreit layer 1050 i alo removed. Next, a nitride layer 1000 i depoited a a CMP top layer above the urface of polyilicon layer 150, gate oxide layer 420, and polyilicon layer 870, a hown in FIG. 12. The remaining fabrication tep for fabrication of the tran itor in the low Voltage area, high Voltage area and memory array area follow conventional technique which are briefly decribed in connection with FIG. 13 and 14. A hown in FIG. 13, the nitride layer 1000 i removed by any etching method known in the art. Then, a mak 80 i ued to protect the low Voltage and high Voltage area. An inter-poly dielec tric layer 64, typically an oxide-nitride-oxide (ONO) and wich layer, i depoited in the memory array area 110 above the floating gate polyilicon layer 870. Referring back to FIG. 1, a control gate polyilicon layer 66 i electively depoited above the inter-poly dielectric layer 64, above which a metal ilicide 68 i electively formed. After mak 80 i removed, the blanket depoited tranitorgate layer in the low Voltage, high Voltage and memory array area are patterned to form individual tranitor gate. Trench TI iolation region 86 are formed to iolate tranitor and ource/drain region 88 and inulating idewall 82 and gate oxide or nitride cap 84 are formed for the tranitor, a hown in FIG. 14. The entire tructure i then covered by another oxide layer 72, typically BPG, and planarized by CMP. The BPG layer 72 i contact patterned and etched and then filled with either a heavily doped polyilicon or tungten to form conductor to the tran itor. The invention provide different gate oxide thicknee for the tranitor in low voltage area 130, the high voltage area 120 and the memory array area 110 to better tailor tranitor performance. In the illutrated embodiment, the tranitor in the low voltage area have the thinnet gate oxide 170, e.g., about 30 A to about 50 A, with the gate oxide 840 in the memory array tranitor being thicker, e.g., about 70 A to about 90A, and the gate oxide 420 of the high voltage tran itor being the thicket, e.g., about 350 A to about 400 A. A modified embodiment of the invention i next decribed with reference to FIG Referring to FIG. 15, a ubtrate 52 compriing a memory array area 1320, a high voltage area 1330 and a low voltage area 1340 i illutrated. An initial depoited or grown acri ficial oxide layer (not hown) i removed and a thingate oxide layer 1350 i depoited or grown. ubequently, a polyilicon layer 1300 and a nitride hard mak layer 1310 are depoited above the thin gate oxide layer Referring to FIG. 16, photoreit material 1460 i applied above the nitride hard mak layer 1310 that i depoited above U 8, 102,006 B both the low voltage and memory array area 1340, Uing a wet or dry etch, the nitride hard mak layer 1310, polyilicon layer 1300 and gate oxide layer 1350 are removed from above the high voltage area 1300, a hown in FIG. 17. after which, the photoreit 1460 i removed. A gate oxide layer 1670 i thermally grown in the high voltage area 1330, while the nitride hard mak layer 1310 protect the low volt age and memory array area 1340,1320, a hown in FIG. 18. Referring to FIG. 19, nitride hard mak layer 1310 (i.e., from above the polyilicon layer 1300 of the low voltage and memory array area) i removed uing a wet or dry etch. However, a mentioned above, it hould be appreciated that the invention i not limited to removing the nitride hard mak layer 1310 uing a dry or wet etch, but that any type of etching method known in the art can be ued to remove the nitride. Referring to FIG. 20, a photoreit 1880 i applied above polyilicon layer 1300 above the low voltage area 1340 and gate oxide layer 1670 to protect the layer. The mak i ued to etch polyilicon layer 1300 in the memory array area Once the etch i complete, the photoreit 1880 i removed. Referring to FIG. 21 and 22, gate oxide layer 1350 i elec tively wet or dry etched from above the memory array area 1320, while receing the gate oxide layer 1670 formed above the high voltage area 1330 to planarize the urface. Then, referring to FIG. 23, a gate oxide layer 2080 i grown above the memory array area. A a reult of growing of gate oxide layer 2080, gate oxide layer 1670 will thicken and rie and the gate oxide layer 2080 will alo grow over polyilicon layer 13OO. A layer of polyilicon 2090 i then depoited above gate oxide layer 1670,2080. The reulting tructure i very imi lar to that illutrated in FIG. 9. Accordingly, the remaining fabrication tage of the gate tructure follow the proce flow decribed with reference to FIG The initial advantage of the decribed embodiment i that the proce i baed on a conventional flah proce and thu, the overall integration of the proce i imple and compatible with exiting fabrication procee. The thinner gate oxide layer which can be achieved for the low voltage logic area of the ubtrate permit fabrication of higher performance logic tranitor. The memory array tunnel oxide layer i kept intact and hence no degradation of the memory array performance will occur. FIG. 24 i a block diagram of a proceor-baed ytem 2200 utilizing a flah memory device 2240 contructed in accordance with the invention. That i, the flah memory device 1240 i formed by the method decribed and illu trated above. The proceor-baed ytem 2200 may be a computer ytem, a proce control ytem or any other y tem employing a proceor and aociated memory. The y tem 2200 include a central proceing unit (CPU) 2270, e.g., a microproceor, that communicate with the flah memory 2240 and an I/O device 2210 over abu It mut be noted that the bu 2280 may be a erie of bue and bridge com monly ued in a proceor-baed ytem, but for convenience purpoe only, the bu 2280 ha been illutrated a a ingle bu. A econd I/O device 2220 i illutrated, but i not nece ary to practice the invention. The proceor-baed ytem 2200 alo include random acce memory (RAM) device 2230 and may include a read-only memory (ROM) device (not hown), and peripheral device uch a a floppy dik 2260 and a compact dik (CD) ROM drive 2250 that alo communicate with the CPU 2270 over the bu 2280 a i well known in the art. It hould be noted that the method of the invention are applicable to formation of any type of integrated circuit where

18 7 three different tranitorgate oxide thicknee are decribed, including integrated circuit memory device including, for example, flah memory. The procee and device decribed above illutrate pre ferred method and typical device of many that could be ued and produced. The above decription and drawing illutrate embodiment, which achieve the object, feature, and advantage of the preent invention. However, it i not intended that the preent invention be trictly limited to the above-decribed and illutrated embodiment. Any modifica tion, though preently unforeeeable, of the preent invention that come within the pirit and cope of the following claim hould be conidered part of the preent invention. What i claimed a new and deired to be protected by Letter Patent of the United tate i: 1. An integrated circuit compriing: at leat three tranitor having repective gate oxide lay er, a firt tranitor having a firt gate oxide layer thick ne, a econd tranitor having a econd gate oxide layer thickne, and a third tranitor having a third gate oxide layer thickne, aid econd tranitor being between aid firt and third tranitor and aid third thickne being between aid firt and econd thick nee, wherein aid third tranitor i above at leat a portion of a memory array region, and wherein aid third gate oxide layer thickne i about 70A to about 90A. 2. The integrated circuit of claim 1, wherein aid firt gate oxide layer thickne i about 30A to about 50A. 3. The integrated circuit of claim 1, wherein aid econd gate oxide layer thickne i about 350A to about 400A. 4. The integrated circuit of claim 1, wherein aid firt gate oxide layer thickne i about 30A to about 50A, aid third gate oxide layer thickne i about 70Ato about 90A, and aid econd gate oxide layer thickne i about 350A to about 400A. U 8, 102,006 B The integrated circuit of claim 1, wherein aid integrated circuit i a flah memory device. 6. A flah memory device compriing: a lower Voltage tranitor area; a memory array tranitor area, and a higher Voltage tranitor area with each area having a gate oxide thickne, wherein aid lower Volt age tranitor area ha a gate oxide layer thickne of about 30A to about 50A, aid memory array tranitor area ha a gate oxide layer thickne of about 70A to about 90A, and aid higher Voltage tranitor area ha a gate oxide layer thickne of about 350A to about 400A. 7. A ytem compriing: a proceor coupled to an integrated circuit, aid integrated circuit compriing: at leat three tranitor having repective gate oxide lay er, a firt tranitor having a firt gate oxide layer thick ne, a econd tranitor having a econd gate oxide layer thickne, and a third tranitor having a third gate oxide layer thickne, aid econd tranitor being between aid firt and third tranitor and aid third thickne being between aid firt and econd thick nee, wherein aid third tranitor i above at leat a portion of a memory array region, and wherein aid third gate oxide layer thickne i about 70A to about 90A. 8. The ytem of claim 7, wherein aid firt gate oxide layer thickne i about 30A to about 50A. 9. The ytem of claim 7, wherein aid econd gate oxide layer thickne i about 350A to about 400A. 10. The ytem of claim 7, wherein aid firt gate oxide layer thickne i about 30A to about 50A, aid third gate oxide layer thickne i about 70A to about 90A, and aid econd gate oxide layer thickne i about 350A to about 400A. 11. The ytem of claim 7, wherein aid integrated circuit i a flah memory device. k k k k k