via into the critical line above. A 20% resistance increase defines the failure of the test structure.

Transcription

1 Electromigration and Stressmigration Failure Mechanism Studies in Copper Interconnects Armin H. Fischer and Alexander von Glasow Reliability Methodology, Infineon Technologies AG, Munich Abstract Electromigration (EM) and stressmigration (SM) are serious wear-out mechanisms, limiting the lifetime of ULSI copper interconnect systems. This paper will summarize comprehensive EM and SM studies with respect to the failure modes, kinetics and lifetime projection. It will be shown, that microstructural as well as layout-specific features play a key role for both mechanisms. Bimodal EM failure scenarios were found on various types of via-line structures. A strong correlation was revealed between the observed failure mode and microstructural properties at the via-to-line-transition. The influence of specific processes on the occurrence and the kinetics of "early" EM failure modes will be discussed. Two examples demonstrate how sensitive the stressmigration behavior is influenced by changes in the microstructure either due to recrystallization or the recovery of crystal defects. Based on kinetic studies, a lifetime model will be proposed. In additon, data will be presented showing the effect of geometrical aspects on the SM failure rate. Electromigration Data Electromigration was investigated on samples of dual damascene (DD) interconnects from a 0.18µm technology with a TaN/Ta liner and a SiN-cap layer. The stress tests were carried out in a temperature range from 175 to 350 C using current densities from 9 to 25mA/µm 2. Both, vialine structures with "narrow" lines (0.28µm width = via diameter) and "wide" lines with a fully landed via (width 0.76µm >> via diameter) were tested. Two current directions have to be distinguished: "downstream" with electron flow from the via into the critical metal line underneath and "upstream" where the electrons flow from an uncritical metal level through the via into the critical line above. A 20% resistance increase defines the failure of the test structure. Fig.1 Failure modes observed on upstream-stressed vias before process optimization: a) via-voiding: voids at the via bottom (early mode); b) trench-voiding: voids in the line and the upper part of the via (late mode). Often, bimodal EM failure distributions are observed on upstream-stressed copper lines terminated with a dual damascene via. Here, two different modes can cause a resistance increase: 1) early mode: voiding at the via bottom since the via liner serves as an effective diffusion barrier, suppressing copper migration from the metal line underneath into the via and enabling material depletion inside the via ("via-voiding", Fig.1a); 2) late mode: voiding in the metal line including the upper part of the via ("trench-voiding", Fig.1b). The resulting failure distribution appears with two distinct branches, where the first branch corresponds to the early and the second branch to late EM failure mechanism (Fig.2). Fig.2 Bimodal distributions usually observed on upstreamstressed vias before process optimization (narrow line). The medium time to failure (MTF) of each failure mechanisms is determined by fitting the measured bimodal distribution by a superposition

2 of two lognormal distributions [1]. Current density exponent (n) and activation energy (Ea) can then be calculated separately for both modes (Fig.3). While the activation energies were found to be almost identical for via- and trench-voiding (0.86eV and 0.83eV), a considerable smaller n- value is obtained for the early mode (n=1.1) in comparison to n=1.6 for the late mode. Fig.4 Failure times measured on upstream-stressed vias with a single SiN and a dual SiN/SiO 2 -cap layer. Fig.3 Current density exponents and activation energies obtained on upstream-stressed vias for via-voiding (early mode) and trench-voiding (late mode) respectively. The impact of local defects in the vialiner on the "upstream" failure scenario is demonstrated in the following. Two different samples were investigated: The first sample with a single SiN-cap layer shows a monomodal distribution with trench-voiding only i.e. no viavoiding failures are observed (Fig.4). In contrast, the cap layer of the second sample consists of a SiN/SiO 2 bi-layer (Fig.5). On those samples, bimodal distributions are obtained with a distinct early branch (Fig.4). About 25% of the sample failed due to voiding in the lower part of the via (Fig.5a). However, in contrast to the via-failure in Fig.1a the void nucleates not at the via bottom but at the dual-cap interface. All later failures can be attributed to the trench-voiding mechanism coinciding with the distribution of the single SiNcap sample. The occurrence of early fails is a result of preexisting voids in the Cu at the bi-layer before electrical stress. This defectivity is caused by an undercut that develops at the interface during via etch (Fig.6). As long as the liner deposition process does not take advantage of re-sputtering, the liner can not cover this edge. Finally, the missing liner yields voids during copper plating, allowing a preferred nucleation of EM voids and hence early failures during electrical stress. intermetal SiO 2 2nd cap layer SiO 2 1st cap layer SiN Cu metal line Fig.5 Failure modes observed on upstream-stressed vias with dual-cap layer. a) early mode: voiding at the cap layer interface; b) Late mode: voiding in the line and the upper part of the via. 2nd cap layer 1st cap layer Fig.6 Specimen with a dual-cap layer before electrical stress. The via-liner does not cover the edge at the dual-cap layer interface leading to pre-existing voids and eventually causing early failures under electrical stress. A bimodal EM failure scenario is not limited to upstream-stressed dual damascene vias. It can also be found during downstream stress, on interconnects with wide lines. These structures turned out to be sensitive with respect to changes in microstructural properties of the copper surface or the SiN-cap layer, respectively. In one particular case a bimodality was observed dependent on the applied pre-clean before liner deposition. Here, bimodal failure distributions were found on samples subjected to an "aggressive" pre-clean A with about % early failures (Fig.7).

3 via/m1 interface (Fig.10). In contrast, a smooth interface is obtained using a less intense preclean B i.e. less power and different gas species (Fig.10). On those samples the early failure mode is completely suppressed (Fig.7). Fig.7 Failure distributions of downstream-stressed vias measured on samples with two different pre-clean processes: pre-clean A yields bimodal distributions (a,b,c), pre-clean B monomodal distributions (d). Cu V1 Ta / TaN Cu M1 Fig.10 Samples subjected to pre-clean A show a thin granular copper layer in M1 at the via-liner/m1 interface. Pre-clean B yields a smooth interface. Fig.8 Failure modes observed on samples subjected to preclean A: a) early mode yields slit-like voids at the via/m1 interface; b) late mode shows large voids in the M1-volume under the via. Fig.9 Current density exponents and activation energies determined on samples of pre-clean A for the early and the late failure mode (wide lines, downstream stress). The early mode is characterized by small slit-like voids between the via and the metal line (Fig.8a). In contrast, much larger voids in the interconnect volume correspond to the late mode (Fig.8b). In analogy to the bimodality of upstream-stressed vias, the current density exponent of the early mode (n=1.1) was found to be smaller than that of the late mode (n=1.5), whereas the activation energies (0.9eV) are almost identical for both downstream failure modes (Fig.9). A local microstructural damage of the copper surface was found to be the root cause of the bimodality (Fig.10). The "aggressive" treatment of the free copper surface during pre-clean A yields a thin "granular" copper layer at the The difference in the current density exponents between pre-clean A (granular surface) and preclean B (smooth surface) shows again the key role of the microstructure for EM kinetics. Obviously, the granular microstructure allows an enhanced void nucleation and a faster migration along the thin layer under the via. Since the via is fully landed on the wide metal line (i.e. no liner redundancy) a small slit-like void is sufficient to produce a large resistance increase and hence an early EM failure. Deviations from a single lognormal failure distribution do not need to be necessarily the consequence of different physical failure modes. They can also be caused by variations of interconnect features within the sample such as cross-section or via-diameter. This situation should be illustrated in the following. Due to lithography and trench etch issues some specimens within the wafer show a pronounced line thinning under the via (Fig.11). During downstream stress metal lines with a small local cross-section tend to fail earlier in comparison to those with less pronounced line thinning because of larger current densities and smaller material reservoir. The resulting failure distribution can be misinterpreted as bimodal, since the early failures appear similar to an early mode. However, in this case the EM failure scenario is the result of one

4 and the same physical failure mechanism. The resulting failure distribution becomes shallow due to geometrical variations within the sample. The shape factor cannot be used for lifetime extrapolation without correction [2]. Fig.11 "Arteficial" broadening of EM distribution due to line thinning under the via. The resulting distribution appears "bimodal", but the "early branch" (dotted circle) is not the result of an additional failure mode. and POR5 the early failure mode is completely suppressed - all failures are exclusively due to trench-voiding. The main reason for this behavior was found to be the optimization of the liner process resulting in smoother liners, with a more homogeneous edge and sidewall coverage. Stressmigration Data Stressmigration tests were carried out on copper metallizations from a 0.13 and a 0.18µm technology, electroplated into SiO 2 trenches, using TaN/Ta liners and SiN-caps. The growth of stress-induced voids was monitored by the resistance drift during high temperature storage (HTS) in a temperature range from 200 to 300 C. Two types of via-chains were investigated: meshtype test structures and plate structures (Fig.13). In addition to an integration scheme with a pure copper build (Cu-Cu(DD)), mesh-structures are available also with a Cu-W-Al stack (Fig.14). Fig.12 Evolution of EM failure distributions during process development (upstream, 300 C, 25mA/µm 2 ). Each process improvement (POR1 to POR5) yields steeper distributions and an increase of the medium failure time. As a general observation, a remarkable "evolution" in the EM behavior of upstreamstressed via-line structures was recognized during the development of different copper technologies. To illustrate this, failure times were merged from a large number of samples even from different metal levels, wafers and lots representing different stages of process development from POR1 to POR5, respectively (Fig.12). Since early hardware shows typically two different failure modes, the merged distributions cover a large range of failure times from 1hr to 1,000hrs. With more and more process maturity the failure times are shifted towards higher values, the shape of the distributions become steeper and the percentage of early fails is decreased. For POR4 Fig.13 Chains of meshes and plates used for SM tests. The chain segments are linked over single vias to narrow lines. A mesh consists of 100µm long lines of 0.28µm width. Fig.14 Metal stacks used for stressmigration tests. In the following, we discuss two different mechanisms for vacancy generation which have the potential to provoke stress-induced voids in copper DD interconnects. In the first example, copper metallizations were annealed at two different temperatures after the plating process. The sample subjected to a high temperature anneal contains significantly larger grains compared to the sample annealed at a 20K lower temperature (Fig.15). In addition the low-t sample shows a center to edge effect, with

5 even smaller grains at the wafer edge (Fig.15). During HTS a resistance increase up to 6% is observed on the low-t sample, whereas the high- T sample shows only a slight negative drift (Fig.16). An analysis revealed that the resistance increase in the low-t sample is caused by voids inside the DD via (Fig.16). Fig.15 Left: Distributions of grain sizes (D) for different post plating anneals before HTS. The high-t anneal yields larger grains. Right: The low-t sample shows a center to edge effect, with smaller grains at the wafer edge. are generated (Fig.17). The released vacancies are captured by stress gradients of the mesh-type test structure and driven towards the via. Eventually, they nucleate at the via bottom, form voids and cause a resistance increase. In contrast, the microstructure of the high-t sample is already stable before the test. Even the high temperature storage does not yield a further change of the grain size. Hence, no vacancies are released and no stressvoids are observed. A remarkable correlation between resistance increase (i.e. stressvoiding rate) and the initial grain size was observed on the low-t sample. Here, a significant higher drift at the wafer edge (Fig.17) was found to be corresponding to smaller initial grain sizes. Obviously, the smaller the initial grain size the larger the amount of vacancies that are released during HTS. Fig.16 Left: Resistance drifts measured on mesh-type test structure during HTS at 225 C. Right: stress-induced voids found in low-t samples inside DD vias after HTS. Fig.18 Relative resistance drift measured at 275 C on pure metal lines without vias (0.28µm width, total line length in the centimeter range). Fig.17 Left: Grain size (D) in low-t sample is increasing after HTS. Right: On the low-t sample larger resistance drifts are obtained at the wafer edge, correlating with smaller grain sizes at those chip positions (Fig.15). The occurrence of stress-induced voids is a result of an unstable copper microstructure in the low-t sample with its small grains in the initial stage. During HTS, larger grains are developed by recrystallization or grain growth, and vacancies Fig.19 Relative resistance drift measured at 275 C on mesh-type test structures linked over DD vias to narrow metal stripes underneath. In a second example, copper DD metallizations are treated by two different precleans (PC) before SiN-cap layer deposition. Preclean A differs from B in terms of the gas species and its flow. In addition, the applied power of the plasma process is considerable smaller, i.e. "less aggressive" in comparison to pre-clean B.

6 Samples treated by pre-clean A turned out not to be affected by stressvoiding. Here, the resistance of both, "pure" metal lines without vias and mesh-type test structures with DD-vias (which are usually very sensitive to SM effects) was found to be constant during HTS (Fig.18, 19). However, the impact of PC B is two-fold: 1) a resistance drop down to -4% on metal lines without vias; 2) a resistance increase on meshtype structures with DD-vias (Fig.18, 19). pre-clean A pre-clean B The distributions are lognormal in the lowtemperature range (mode 2), but show two distinct branches for temperatures >225 C. The early branch (mode 1) becomes more and more pronounced with increasing temperature. Fig.21 Failure distributions ( R/R=1%) obtained on meshtype structures with Cu-W-Al stack are bimodal for stress temperatures >225 C. The early branch (mode 1) becomes more pronounced with higher storage temperature. Fig.20 Right: Crystal defects in bulk copper after treatment by pre-clean B (dark dots in the region marked by arrow). Left: Pre-clean A does not affect bulk crystal structure. The resistance drop obtained on pure metal lines indicates the recovery of crystal defects during HTS. As revealed by TEM (Fig.20), metal lines of pre-clean B show a large number of defects in the bulk copper (probably dislocation rings or precipitations). In contrast, the crystal structure remains unaffected for pre-clean A. We assume that during recovery vacancies are generated and driven towards the via by the stress gradients present in mesh-type structures. Eventually, the vacancies are accumulated inside the DD-via. Since large stress gradients are absent in structures without vias, no SV failures are obtained on pure metal lines. Here, the resistance drops due to the recovery of the crystal lattice. Kinetic studies were performed to investigate the temperature dependence of the SM behavior. The SM failure time of a specimen is defined by the time until a certain resistance increase R/R is obtained. Failure times obtained on mesh-type test structures with Cu-W-Al stack show a steady reduction with higher stress temperature (Fig.21). Fig.22 Voids found in the copper level near the W-plug after 1,000hrs at 275 C. Early failures (mode 1) correspond to large voids in the interconnect volume; Later failures (mode 2) are due to small voids at the Cu/SiN interface. Bimodal SM distributions are fitted underlying a superposition of two log-normal distributions. The medium failure times of both modes follow quite well a straight line in an Arrhenius plot (Fig.24). The corresponding activation energy is 1.4eV for mode 1 and 0.9eV for mode 2. For both modes the voiding occurs in the copper level next to the W-plug. However, the void shape is different (Fig.22). Early failures are characterized by large voids occupying a whole line segment; failures of the late branch show smaller voids along the Cu/SiN interface. The differences in activation energy and void shape indicate different diffusion mechanisms: Volume-like voiding and Ea=1.4eV suggest grain boundary diffusion as dominant mechanism for mode 1; Slit-like voids in the upper part of the Cu-line and a smaller activation energy (0.9eV) support interface diffusion along the cap layer as main migration pathway for mode 2 [3].

7 In contrast to the bimodal failure scenario of mesh-type test structures with Cu-W-Al stack, failure distributions gathered on the same structures with Cu-Cu(DD) build turned out to be monomodal within the investigated temperature range from 225 to 275 C (Fig.23). The failure times obtained at 225 C are about 5x larger compared to Cu-W-Al, indicating that Cu(DD)- designs are more robust with respect to wear-out by stressmigration. Slit-like voids along the SiN interface were found in the mesh level next to the DD-via (Fig.23). Again, the medium failure times follow a straigt line in an Arrhenius plot (Fig.24). Although the value of the activation energy (1.2eV) tends more to the value of grain boundary diffusion, it still fits in the range of values reported for SiN interface diffusion [4]. Supported by the failure analysis we assume interface diffusion as dominant migration pathway for Cu-Cu(DD). then defined by the time until a certain amount of failures (CDF max ) is accumulated using a lognormal failure distribution. However, it should be noted that the use of eqn.(1) presupposes, that the diffusion mechanisms acting at high stress conditions are still the same for lower operation conditions - this was not verified by studies in this paper. Fig.24 SM failure times ( R/R=1%) obtained on meshtype test structures with Cu-W-Al and Cu-Cu(DD) stacks. stack / mode Ea [ev] t C t C Cu-W-Al mode yrs 5 yrs Cu-W-Al mode yrs 2 yrs Cu-Cu(DD) yrs 38 yrs Tab.1 Lifetimes (t EOL ) calculated for operation temperature 100 and 125 C ( R/R=1%, CDF max =1ppm). Fig.23 Failure times ( R/R=1%) on mesh-type structures with Cu-Cu(DD) build are distributed lognormal within a temperature range from 225 to 275. Only one failure mode was found leading to small voids at the Cu-SiN interface. Based on the data presented in this study, the medium stressmigration failure times depend exponentially on the stress temperature (Tstr) for both Cu-W-Al stack and Cu-Cu(DD) build within the investigated temperature range: MTF ~ exp( Ea / k T str ) (1) Obviously, there is a fundamental difference to the temperature dependence observed on Al(Cu) interconnects, where SM failure times reach a distinct minimum at C [5, 6]. To calculate the stressmigration-limited lifetime, eqn.(1) was used to transform failure times from stress to operation temperature. The lifetime is The lifetimes obtained with this method (Tab.1) are considerable larger for the Cu-Cu(DD) build. For 100 C and 125 C they are far above a typical 10yrs target. In contrast, the lifetime for Al-W- Cu stacks is close to a 10yrs-target for 100 C but below target for 125 C operation temperature. The influence of geometrical aspects on the SM behavior was investigated on structures with square-shaped plates connected over single DD-vias to narrow links in the metal level underneath (Fig.13). The test module contains five different plate areas from 4x4 to 20x20µm 2 each with six different vias sizes from 1.0x down to 0.76x of the nominal diameter. The failure frequency was found to be increasing with both, increasing plate size and decreasing via-diameter respectively (Fig.25). The plate size effect can obviously be related to the increase of the "active volume" in bigger plates [7,9]. Since the plates serve as a vacancy

8 reservoir, more and more free vacancies are provided with increasing metal volume. If a stress gradient is present within this volume all those vacancies at a distance smaller then their respective diffusion path length from the via have the potential to contribute to the voiding process inside the DD-via. For the via-size effect two different aspects have to be considered: 1) the same void volume yield larger resistance increases in vias with smaller diameter and 2) the stress gradients around the via and hence the driving force is possibly be larger if the plate is connected by smaller vias to the metal link underneath. Fig.25 Resistance failures ( R/R=20%) obtained on plate structures with DD via after 1,000hrs at 275 C. The number of failures is increasing with increasing plate area (NxNµm 2 ) and decreasing via diameter (1=1.0x; 2=0.92x; 3=0.88x; 4=0.84x; 5=0.80x; 6=0.76x nominal via size). Conclusion Microstructural properties and geometrical aspects turned out to play the key role for both, stressvoiding and electromigration behavior. The EM failure scenario was found to be dependent on the local microstructure at the transition between via and metal line, which are closely related to liner deposition and pre-clean process. "Early" failure modes turned out to have not only smaller failure times but also decreased current density exponents, indicating that those failures are due to void-growth rather than void nucleation [8]. It was shown that the occurrence of "weak" failure mechanisms can be suppressed when using appropriate processes. Stress-induced voiding in copper interconnects was observed in metal levels which provides "large" vacancy reservoirs. If the large copper volume is above a via, voiding occurs inside the DD-via; in case that the large copper volume is below, the void develops next to the via or the W-plug. Two important vacancy generation mechanisms were found to provoke stress voiding in copper metallizations: vacancy generation by recovery and recrystallization. Their occurrence depends on the initial microstructure and can be suppressed by introducing optimized pre-clean and anneal procedures, respectively. The SM failure times obtained in this study can be well described by lognormal distributions. Two different modes were observed which could be associated with grain boundary and interface diffusion. Failure times obtained on the Cu-Cu(DD) build are considerable larger in comparison to Al-W-Cu and show no bimodality. The MTFs for all modes can be well described by an Arrhenius equation over a wide temperature range. The extrapolated lifetimes can meet a typical 10yrs target for 100 C. Enhanced stressvoiding was observed on test structures with increasing vacancy reservoirs or decreasing via diameter. References [1] A.H. Fischer et al., "Experimental Data and Statistical Models for Bimodal EM Failures", IRPS 2000 Proceedings 38th Annual, 2000, pp [2] A. von Glasow et al. A Comparison of Reliability Aspects of a 0.35µm and 0.18µm Process Copper Metallization ; Proc. AMC 2000; San Diego 2000, MRS, pp [3] C.K.Hu et al., Electromigration path in Cu thin-film lines, Applied Physics Letters 1999 [4] T.Oshima et al., Improvement of Thermal Stability of Via Resistance in DD Cu-Interconnects, IEDM 2000 [5] J.W.McPherson et al., A model for stress-induced metal notching and voiding in VLSI AlSi metallizations, J.Vac.Sci.&Tech [6] A.H.Fischer et al., The quant. assessment of stressinduced voiding in process qualification, IRPS 2001 [7] E. Ogawa et al., "Stress-Induced Voiding Under Vias connected to Wide Cu Metal Leads, IRPS2002 [8] J.R. Lloyd, "Electromigration in integrated circuit conductors", J.Phys.D: Appl. Phys. 32, R , 1999 [9] A.v.Glasow et al., Geometrical Aspects of Stress- Induced Voiding in Copper-Interconnects, to be published in Proc. AMC 2002