12.2 Silicon Solar Cells

Transcription

1 12.2 Silicon Solar Cells High Efficiency Crystalline Solar Cells Development of (5 inch X 5 inch) crystalline silicon solar cells (S. Saravanan, Ashok Kumar Sharma, Anzar Gani, Sandeep S. S., Balraj Arunachalam, Vaithinathan Karthikeyan, Sandeep Kumbhar): In the previous quarter we had reported on the optimization of the texturization process with texture additive. The texture additive gives the following advantges over the process without texture additive. 1. IPA free process 2. Smaller amount of chemicals are used 3. Process duration is almost half compared to the IPA based process We have integrated the texture additive process in our cell line and an improvement in performance is obtained. The best baseline efficiency prior to this was 16.4%. Table 12.1: Performance of cells with texture additive process. Jsc (ma/cm2 ) Isc (A) Voc (mv) FF (%) Efficiency (%) Fig. 12.1: IV characteristics of the best cell. After a couple of trials, the texture additive process is now part of the baseline process at NCPRE. Historical best cell efficiency data is plotted in Fig

2 Fig. 12.2: Efficiency trends of silicon solar cells of area 5 inch X 5 inch fabricated at NCPRE. Further improvements in the cell efficiency require a detailed understanding of the losses in the solar cells. We have carried out a detailed analysis of the losses in the solar cell from our previous baseline, i.e. without texture additive. The objective is to identify the specific unit processes for priority development. The scheme of loss analysis is based on a set of measurements, including light and dark current-voltage, reflectance and quantum efficiency. The analysis provides a detailed quantification (in W/cm 2) of the seven main power loss mechanisms in a silicon wafer solar cell: front metal shading, front surface reflectance in the active cell area, front surface escape of light, series resistance, shunt resistance, non-perfect active-area internal quantum efficiency, and the forward-bias current at the one-sun maximum power point. It is assumed that the cell can be described using a one-diode circuit model and that the characteristics follow superposition principle. Fig shows the illuminated I-V and P-V characteristics under AM 1.5G spectrum. The performance parameters of the cell can be found on the figure. Fig. 12.3: The IV characteristics of the cell for which a detailed loss analysis was carried out. 2

3 The series resistance at the one-sun maximum power point is obtained by shifting the measured one-sun I-V curve by Jsc from the fourth to the first quadrant. It is determined from the voltage gap between the dark and one-sun I-V curves and is tabulated in Table From Rs corrected light I-V curve, whereby it is assumed that, for voltages above the Rs corrected Vmpp, curve is a single exponential curve the ideality factor n eff and diode saturation current density J0.eff were measured as 1.2 and 4.8 x A/cm2, respectively. The shunt resistance Rshunt (5 KΩ-cm2) of the solar cell is determined from a linear fit to the dark I-V curve, within the voltage range -0.5 V to 0 V. Fig. 12.3: Measured dark J-V, Jsc -shifted light J-V and Rs -corrected light J-V curves. The Rs -corrected light J-V curve is determined by connecting the two points (Vmpp + Rs* Jmpp, Jsc - Jmpp) and (Voc, Jsc). The other important parameters measured and derived viz. weighted average reflectance of Si wafer after alkaline texture, SiNx ARC coating, front metal coverage, diffused emitter sheet resistance, series and shunt resistanc, diode ideality factor, saturation current density and effective carrier lifetime are listed in Table Table 12.2: Measured and derived solar cell parameters. Wt. avr. R Wt. avr. R after texture after SiN (%) (%) Fraction metal coverage (%) Sheet Resistance Series Resistance (mω- cm2) Shunt Resistance Ideality factor neff Sat. Current density J0eff (Acm-2) Effective carrier lifetime τ (μs) x 40 (KΩ-cm2) (Ω/ )

4 10-11 Fig shows the internal quantum efficiency (IQE) measured in the nm wavelength range under light bias and active area reflectance. Table 12.3 lists maximum current density under spectrum, integrated current density over IQE, over EQE (ignoring optical losses due to active area reflectance) and current density at maximum power point (mpp). Fig. 12.4: Measured internal quantum efficiency (IQE) with and without light bias and active area reflectance of cell. Table 12.3: Measured and calculated current density under spectrum, as IQE, as EQE and at maximum power point. Maximum current density under spectrum 46.5 ma/cm2 Calculated current density {Σ IQE(λ)} 38.7 ma/cm2 Calculated current density {Σ EQE(λ)} 37.3 ma/cm2 Measured current MPP 31.4 ma/cm2 Fig lists the current and power loss per unit area and pie chart of the losses. The dominant loss mechanisms are the non-perfect IQE (49%) in the active cell area, front metal shading (21%) and forward-bias current at one-sun MPP (14%). The total current loss at MPP (15.1 ma/cm2) combined with the measured Jmpp (31.4 ma/cm2) adds up to total possible current from the AM1.5G spectrum i.e ma/cm2. 4

5 Fig. 12.5: Losses in the 16.4% efficient solar cell. The major component of the loss is the nonperfect IQE. The blue response of the cells can be much improved from the present values. Presently the sheet resistance of the emitter is in the range of 45 /sq. This can be further increased by etch back of the deadlayer or by controlling the diffusion process parameters to obtain a shallower junction. The other area for improvement is metal shading. This can be achieved by using narrower fingers. These processes would be pursued for improvement of cell performance. Al2O3 for surface passivation (Kalaivani S.): Aluminum oxide is an emerging material for the passivation of p-type crystalline silicon surfaces. We have recently started investigating solution processed Al2O3 for this purpose. This technique promises a cheaper process compared to any other technique presently being explored for the deposition of Al 2O3 for solar cell passivation. During the previous quarter, we had reported the passivation of p-type silicon using spray coated Al2O3. Though a low surface recombination velocity (SRV) of 28 cm/s was obtained, the draw back was that to obtained such low SRV, the sample had to be annealed at 850oC for 2 hrs. During the quarter under review, we had tried to improve the situation by introducing the chemical oxide on the surface of the silicon prior to the deposition of the Al2O3. RCA cleaned, p-type, FZ <100> Si wafers with resistivity of 3 Ω-cm is used as the substrate for the experiments. The 4 inch wafers were cleaved into four quarter samples and named S1, S2, S3, and S4. S2, S3 and S4 samples were treated with 5% HF for 5 sec followed by HNO3 oxidation at 80 C for 20 min with HNO3 concentration of 68 wt %. S3 is annealed in preheated furnace at 800 C for 15 min in N 2 keeping load in and load out temperature at 600 C. All samples were then spray coated to form thin layer of Al2O3 using N2 as carrier gas and heated on hot plate at 220oC for 5 min. S1, S2 and S3 samples were annealed in furnace in O2 ambient keeping load in and load out temperature at 525 C. 5

6 Table 12.4: Impact of interfacial oxide grown by HNO 3 treatment on the passivation quality. S1 S2 S3 S4 RCA 5% HF Dip for 30 sec HNO3 oxidation Furnace Anneal at 800 C No No No No Al2O3 sol-gel spray-coating Furnace Anneal in O2 525 C, 2h 525 C, 2h 525 C, 2h 800 C, 2h µs µs µs µs 249 cm/s 239 cm/s 457 cm/s 76 cm/s 1x 1015 cm-3 SRV It is seen that the addition of the SiO 2 do not change the temperature required for good passivation. We would optimize the growth of the SiO 2 using HNO3 and post deposition anneal conditions for improving the passivation. Low Temperature Oxy-nitride for Surface Passivation of Silicon Solar Cells (Sandeep S. S.): In the previous report, it was shown that the minority carrier lifetime of PECVD deposited silicon nitride films, improved significantly following Ar/N2O plasma treatment. The enhancement in lifetime was seen to be the result of a decrease in interface state density and an increase in fixed charge density. The lifetime enhancement was seen both on n-type and ptype silicon surfaces. It was also seen that the improvement in passivation was thermally stable up to annealing temperatures of 450oC. In this report, the physical mechanism underlying the improvement in lifetime is discussed. Fig. 12.6: (a) FTIR characteristics for SiN film for different plasma treatment powers. (b) FTIR and XPS data for SiN film for treated at 10 W plasma power. 6

7 FTIR measurements were carried out to investigate the impact of plasma treatment on the chemical composition of the silicon nitride film. The films were treated in Ar/N 2O plasma ambient. An increase in Si - O bond density, centered at 1105 cm-1, was the only difference between the post treated sample and its reference. However, even for higher plasma power, no significant change was seen in the bulk composition of the silicon nitride film as shown in Fig. 12.6(a). The plasma power used in our experiment may have been low enough to result in a change in chemical composition of the silicon nitride bulk. From ARXPS measurements on plasma treated and untreated samples, it was found that the amount of silicon and nitrogen for both the samples were identical. However, the oxygen signal intensity was seen to go up following the Ar/N2O plasma treatment, indicating oxygen incorporation into the silicon nitride film as shown in Fig. 12.6(b). The oxygen present in the untreated sample may have been the result of exposing the sample surface to ambient. For 0 degree, O - content in the reference and the post treated sample are comparable. However, as we move closer and closer to the surface, O - content was found to be higher for the post treated sample. Thus from the FTIR and XPS measurements, it maybe concluded that the plasma treatment of silicon nitride modified only the near surface region and not its bulk chemical composition. From previous experiments, it was seen that the τeff was seen to improve after Ar/N 2O plasma post treatment. C-V measurements, confirmed that the plasma treatment led to a decrease in interface state density and an increase in fixed charge density. The quantum of improvement in τeff was seen to have a bearing on the hydrogen content within the silicon nitride film. However, the exact physical mechanism behind the improvement in τ eff is not clearly understood. In this section we investigate the mechanism behind the enhancement in τ eff after Ar/N2O plasma treatment. As reported by Vernhes et al. plasma treatment of silicon nitride films can result in annealing of the silicon nitride. The kinetic energy of the ionised species is dissipated as it bombards the silicon nitride, resulting in a rise in temperature. This would imply that if, we use a lighter species like He, amount of energy transferred onto the silicon nitride film would be less. In order to test this hypothesis, an experiment was designed to study the impact of various plasma ambient on τ eff enhancement. Silicon nitride film was deposited on both sides of n-type FZ wafers (3 Ω-cm). The samples were then treated in He, Ar and Ar/N2O ambient for 10 min respectively on both sides of the wafer. The result of the experiment is shown in Fig. 2(a). As compared to the reference sample, there was significant enhancement in τeff. However, τeff across the samples were comparable. Ar/N2O plasma treatment resulted in best τeff, followed by Ar and He plasma treatments. However, the difference in τeff for different plasma ambient was not significant. This indicated that though the plasma ambient plays a role in determining τ eff, the cause for the significant enhancement in τeff following plasma treatment lies elsewhere. Fig. 12.7: (a) Variation in τeff for plasma treatment in different ambient. No significant change 7

8 in lifetime was seen for different ambient. (b) τ eff measurement on p-type textured samples, before and after plasma (RF) treatment. No RF corresponds to the sample kept in the chamber without turning on the RF supply. Another potential reason behind the improvement in lifetime may have been the annealing of the sample as a result of the high substrate temperature. During plasma treatment, the sample resides on the substrate for an additional 10 min at 380oC. This in situ annealing during the plasma treatment may have an impact on the final effective lifetime. Additionally, from C-V measurements, it was seen that the net enhancement in lifetime was the combined effect of an increase in Qf, as well as decrease in Dit. An increase in Qf on p-type wafers is known to result in a degradation in τeff for lower minority carrier density owing to the formation of an inversion layer. To investigate the impact of substrate temperature and to study the influence of plasma treatment on Qf, the experiment, was carried out on textured p-type Cz wafers of 1 Ω-cm resistivity. Silicon nitride was deposited on both sides of the sample, and the samples were treated in Ar/N2O ambient, by turning OFF the RF supply. All other chamber conditions remained same, and the sample was placed in chamber for 10 min. As shown in Fig. 2(b), τ eff doubled when the sample was kept in chamber without any RF supply. Upon turning the RF supply ON, τeff was seen to decrease for lower injection levels, while it was seen to improve marginally for higher injection levels. The fall in τeff for lower injection levels, can be attributed to an increase in fixed charge density, following plasma treatment. This experiment thus clearly demonstrates and decouples the effect of the substrate temperature and plasma treatment on the effective minority carrier lifetime. Thus, by combining the results shown in Fig. 12.7, it may be concluded that the enhancement in τ eff is brought about by the combined effect of both substrate annealing and as well as plasma treatment. The impact of plasma treatment on the emitter surface passivation was investigated on 1 Ωcm p-type textured Cz wafers. Gas phase phosphorus diffusion was carried out on both sides to form symmetric test structures. The sheet resistance after diffusion was measured to be 45 Ω/. Silicon nitride was deposited on both sides of the wafer, and Ar/N 2O plasma treatment was carried out on both sides as well. The schematic of the device used for measurement is shown in inset of Fig. 5. Sample without any Ar/N 2O post treatment was used as reference sample. The implied Voc was measured using PCD measurements. As shown in Fig. 12.8, an improvement in τeff was seen, which resulted in an improvement in implied Voc from 668 mv to 672 mv. Fig. 12.8: Improvement in lifetime observed following plasma treatment of silicon nitride on an n-type emitter. Inset shows the schematic of the device used for the experiment. 8

9 Solar cells on n-type wafers (Bandana Singa): Screen printed Al at the back side was used to form a p- type emitter in n- type c- Si solar cell. The process flow diagram of the work is shown below. TMAH texturing for pyramid heights 4-5µm RCA cleaning n+ diffusion at the front SiNx deposition over n+ layer Al screen printed at the back side and Ag at the front cofiring. The lighted and dark IV of the cell are shown in Fig The parameters of the solar cell are given belowsize: 12.3 cm2, Isc: ma, Jsc: ma/cm2, Voc: mv, Impp: ma, Vmpp: mv Pmpp: mw, Fill factor: 55.0 %, Rseries= 6.15 Ω-cm2, R shunt= 4.78 Ω-cm2. Efficiency: 6.9 % Illuminated IV Dark IV Current density Voltage, V Fig. 12.9: AM1.5 G and dark IV characteristics of the solar cell fabricated on n-type wafer with backside Aluminum doping. The Voc value for the back junction Al diffused n- type c- Si solar cell was more than 530mV. The dark IV shows that the device is shunted and needs improvement Laser fired contact solar cell (Som Mondal, Swati, Aneesh, Aldrin Antony): The solar cell structure with rear side passivation and laser fired contact is presented schematically in Fig (a). In earlier study with solar cell fabricated on 4 cm 4 cm area, series resistance value of 0.5 Ω-cm 2 was obtained leading to fill factor of 76%. Solar cells were made on 5 ( cm2) pseudosquare substrate. Back side Aluminium was evaporated through a mask of cm 2 area. The laser firing was performed using 11 µs and 100 pulses. The passivation layers used are SiON and SiON/SiNx double layer. The effect of passivation layer was not very good and hence the Voc and Jsc are not very high. Because of the area uncovered by evaporated Al at the rear edges, the series resistance was very high (0.9 Ω-cm2). However, with an illumination area of 118 cm2, series resistance of 0.2 Ω-cm2 and fill factor of 78.9% has been achieved. This led to a maximum efficiency value of 15.95% on >100 cm2 area using SiON/SiNx stack as passivation layer. Fig (b) depicts the J-V curve of the cells with two different passivation schemes. 9

10 Fig : (a) Solar cell structure with rear surface passivation and laser fired contacts. (b) JV data of solar cells with screen printed front contact and laser fired rear contact. The J-V curve was measured with an illumination area of 118 cm Ni/Cu metallization for front contact (Mehul Raval): Complete solar cell with rear-side passivation and without conventional firing step based on Ni-Cu-Sn front side metallization stack is fabricated with Voc of 626 mv. Solar cells of size 4x4 cm 2 were obtained from 5 inch processed Cz wafers with only front side texturing and diffusion. The processed wafers had front and rear-side passivation layers of PECVD based SiN x. The front ARC was patterned using solar etch paste with line openings in range of µm. Al was then screen-printed on rear-side and dried which were then laser fired to form localized contacts on the back side. The high temperature RTP step typically used for full Al-BSF based cells is not required in the current cell processing. An optimized electroless nickel alkaline bath with temperature in the range of C was used for deposition of thin nickel seed layer. Samples were annealed at 375 C in a tubefurnace with N2 ambient for nickel silicide formation. Subsequently, Cu-Sn plating was done for thickening the grid lines. Suns-Voc and EQE measurements were performed to check the impact of rear-side passivation on the cell performance. Suns-Voc curve for a fabricated cell is shown in Fig The V oc value of 626 mv is more by around 15 mv than cells based on full Al-BSF architecture. Since the pff value is 77%, further dark I-V analysis will be done to understand the recombination mechanisms responsible for the loss as values in the range of 80-81% have been achieved for cell based on full Al-BSF architecture. EQE for cells with rear-side passivation is shown in Fig It can be observed that the response for wavelength greater than 1000 nm improves under lightbias which is attributed to the activation of the charges in the rear-side passivation. In comparison with a cell based on full Al-BSF, there is an improvement in the lower wavelength response due the N2O based oxidation before front side SiNx deposition, while the response in the range of nm is also better. Illuminated I-V analysis of fabricated cells will help to determine the impact of the laser-fired contacts on the series resistance of the solar cell. 10

11 Fig : Suns-Voc I-V curve for Ni-Cu-Sn Fig : plot for Ni-Cu-Sn based cell with based cell with rear-side SiNx based rear-side passivation. EQE of cell based on passivation. full Al-BSF is included for reference Adhesion of Ni-Cu contacts on silicon (Vishnu Kant Bajpai): The objective is to improve the adhesion of nickel-copper electroplated front contact of c-si solar cell without any performance sacrifice. Adhesion value of >23 MPa has been already obtained between Ni seed and Si emitter after silicidation by improvement in nickel seed layer and annealing optimization studies. The adhesion between complete Ni-Cu contact and Si came out to be ~12 MPa which is reduced because of intrinsic stress in the Cuelectroplated film. Although, this 12 MPa of adhesion strength is sufficient to withstand the mechanical and thermal stresses caused during module fabrication and its field operation but still we are trying to further improve it as it can be. Currently we are studying the stability issues of complete Ni-Cu contact with respect to adhesion and copper diffusion into junction shunting. Thin Ni-P seed layer is deposited by electroless chemical bath deposition and Cu is electroplated onto it. Ni-Cu deposited samples on textured Si cell were co-fired at different annealing temperatures to study contact adhesion, formation of silicide and stability of diffusion barrier against copper. Cross-sectional TEM sample were prepared following standard process and characterized using optical, HR-TEM and EDS characterization techniques. It is found that the nickel is presenting excellent barrier against copper up to 400 C as there is no deep Ni or Cu diffusion into silicon found causing junction shunting as shown in Fig of EDS elemental line scan of cross-sectional TEM sample.but above 400 C, there is local spot like shunting observed causing dissolution of nickel barrier layer as shown in Fig Although most of the substrate is unaffected by this local spot like shunting but this will lead to completely shunted cell as piller like structures caused by deep Cu diffusion are deeply rooted (~ 3-4 times the pyramid height) into the silicon substrate as shown in crosssectional image in Fig The local spot like shunting may be due to the local nonuniformities in the nickel seed layer. 11

12 Cu Ni Si Fig : Elemental line scan Fig : Optical image of Ni-Cu contact on textured in cross-sectional TEM of Ni-Cu silicon solar cell after annealing at 450 C. The left image contact on c-si cell. is a plan view and the right is a cross section Plasmonics for Photovoltaic Application (Hemant Kumar Singh): The dielectric - metal - dielectric (D-M-D) based plasmonic anti-reflector has been tested on PV cell having standard thickness 180 µm. Also, the reflectance reduction was demonstrated on 140 µm Si wafer as shown in earlier reports. These sandwiched structure based plasmonic anti-reflectors (SiNx-Ag-SiNx) was further tested on 100 µm Si wafer. We etched the as-cut c-si wafer from its main thickness 200 µm to 100 µm in 20 % KOH solution and then we deposited the plasmonic anti-reflectors (SiN x-ag-sinx) as optimized before. Also for comparison we fabricated standard 80 nm SiN x based samples on 100 µm Si substrate. The cross-sectional SEM image is shown in Fig which shows wafer with plasmonic antireflection layer having SiNx-Ag-SiNx structure. The wafer/substrate was non-textured surface having 100 micron thickness. Fig (b) shows the zoomed SEM image for SiN xag-sinx D-M-D structure. Fig shows 3D microscope image of sample surface for samples e.g. Si substrate (100 µm); Si(100 µm)/sinx(80nm) and Si(100 µm)/d-m-d plasmonic ARC respectively. The measured total reflectance with corresponding weighted total reflectance (TWR) of the samples is shown in Fig

13 Fig : (a) Device geometry for sample having 100 µm Si substrate with optimized dielectric-metal-dielectric (D-M-D) plasmonic AR structure; (b) the zoomed SEM image for SiNx-Ag-SiNx D-M-D structure on Si substrate. Fig : 3D microscope image of sample surface for different samples. (a) Si substrate (100 µm); (b) Si(100 µm)/sinx(80nm), (c) Si(100 µm)/d-m-d plasmonic ARC. Fig : Measured total reflectance with corresponding weighted total reflectance (TWR) for different sample. (a) Si substrate (100 µm); (b) Si(100 µm)/sinx(80nm); (c) Si(100 µm)/d-m-d plasmonic ARC. For such multilayer geometry, the weighted total reflectance (TWR) is 8.8 % for broad wavelength range 300 nm nm which is 32.3 % lesser than standard 80 nm SiN x based ARC geometry which results 13 % on thinner (100 µm) c-si substrate. It can be clearly seen that the same optimized plasmonic anti-reflectors (SiN x-ag-sinx) works for thinner wafer and it indicates its potential use for thinner c-si wafer based cell. Further we are trying to fabricate thin wafer based solar cell using the optimized plasmonic ARC. 13

14 Slicing of silicon wafers for PV applications using Wire Electric Discharge Machining (We-EDM) (Kamlesh Joshi, Pradeep P.): During the quarter under review we have investigated various complex phenomenon like formation of plasma channel, melting and erosion of Si material with the help of a mathematical model. A mathematical model has been developed using dielectric-ingot material properties, heat transfer equations and steady state heat source characteristics to predict temperature profile, melt radius and erosion rate for the ingot and its dependence on voltage, current, wire diameter and pulse on-time have been considered. Modeling of plasma for different phases like ignition phase, heating phase and removal phase has been done. Fig shows the different phases during the wire EDM process. Fig : Phases showing plasma formation, heating and material removal during Wire EDM. Fig : Growth of nucleated bubble to fully grown plasma channel. The following conclusions can be made based on the simulation results: In wire-edm, breakdown of liquid dielectric leads to the formation of a plasma channel between the electrodes. The plasma expands and interacts with electrodes to effect the material removal from the respective electrodes. 14

15 As the voltage, current and pulse on-time increase (keeping other parameters constant), plasma temperature and interface temperature increase. Because increased power input to the wire causes increase in plasma energy, which consequently increases plasma and interface temperature. Erosion rate will increase with increase in voltage, current and pulse on-time. With increase in wire diameter, crater radius will decrease so erosion rate will decrease. With increase in wire diameter, kerf-width increases due to increase in plasma width. We have also investigated the surface morphology of silicon sliced using wire EDM process and surface profilometry and SEM imaging were employed for analysis. Fig (top) shows the suface profile of standard PV wafers purchased fom the market. These wafers were sliced using diamond wire saw technique. The saw marks can be easily identified. The surface roughness is about 6 μm. The bottom images show the surface roughness of wafers sliced using the wire-edm process. Brass wires and molybdenum wires were used. It can be seen that the wire EDM process result in higher surface roughness than the diamond wire saw method. In the case of brass wire, the roughness is in the range of 8 μm, and it is about 12 μm in the case of molybdenum wire. The average surface roughness of Mo wire EDM seems to be more than that of brass. This was against expectation as the Mo wire EDM machines using lesser current than brass wire EDM. Fig : (top) Surface profile of commercial silicon wafer sliced using diamond wire saw. (bottom-left) Surface profile of wafer sliced using brass wire. (bottm-right) Surface profile of wafer sliced using molybdenum wire. The vertical scales in micrometers. 15

16 Fig : SEM images of surface of wafers sliced using brass wire. (left) after 2 minutes of sonication (right) after 5 minutes of sonication. Fig : SEM images of surface of wafers sliced using molybdenum wire. (left) after 2 minutes of sonication (right) after 5 minutes of sonication. SEM images taken after ultra sonic cleaning of the wafers. SEM images of surface of wafers sliced using brass wires is shown in Fig and those sliced using molybdenum wire are shown in Fig After ultrasonicating for 5 minutes no concrete difference was observed under SEM. On Ultrasonic cleaning for more than 5 minutes the wafers started to disintegrate. 16