Low D it High-k/In 0.53 Ga 0.47 As Gate Stack with CET down to 0.73 nm and Thermally Stable Silicide Contact by Suppression of Interfacial Reaction

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1 IEDM 2013 Dec 9 th, 2013 Low D it High-k/In 0.53 Ga 0.47 As Gate Stack with CET down to 0.73 nm and Thermally Stable Silicide Contact by Suppression of Interfacial Reaction D. Hassan Zadeh, H. Oomine, K. Kakushima, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, and H. Iwai Tokyo Institute of Technology 1

2 Metal high-k/ingaas and S/D Recently various device structures have been demonstrated on InGaAs platform with superior performance. J. Lin, IEDM 12 S.H. Kim, IEDM 11 M. Radosavljevic, IEDM 11 InAs QW MOSFET Gate: Mo/HfO 2 /InGaAs S/D: Ion Implant -High transconductance -Small SS III-V-OI MOSFET Gate:Ta/Al 2 O 3 /InGaAs S/D: Metal (Ni-InGaAs) -High peak mobility Tri-gate (high-k/ingaas) S/D: n ++ cap -Steep SS and Small DIBL Improvement in dielectric/ingaas interface quality has been a key factor for superior performance. 2

3 Selection of gate oxides for InGaAs High-k Al 2 O 3 (a) k-value (scalability) ~9 (CET~2nm) HfO 2 /Al 2 O 3 stack (b) ~16/9 (CET=1nm) D it (cm -2 /ev) Temperature tolerance ~8x10 11 ~400 o C >10 12 ~400 o C HfO 2 (c) ~16 (CET~1nm) >10 12 ~400 o C ZrO 2 (d) ~20 (CET=0.78nm) >10 13 ~400 o C La 2 O 3 ~26 (this work) this work this work (a) E. J. Kim, JAP 106, (b) R. Suzuki, APL, 100, (c) R. D. Long, JAP 106, (d) J. Huang, IEDM 09 Scalable dielectric with high interface quality and high thermal tolerance are still needed. 3

4 Band discontinuity (ev) 4 La 2 O 3 dielectric properties Al 2 O 3 (1) CB In 0.53 Ga 0.47 As VB HfO 2 (1) Gd 2 O 3 (2) La 2 O 3 (2) Ref (1) :N. Goel et al., IEDM 08 Ref (2) :S. Oktyabrsky ZrO 2 (1) Ga 2 O 3 (Gd 2 O 3 ) (1) Dielectric constant LaAlO (1) Fundamentals of III-V semiconductor MOSFETs La 2 O 3 Properties: k-value 26, Band gap: 5.5 ev (hexagonal crystalline) Suitable for scaling Absorbs Moisture In-situ process for gate dielectric and metal required.

5 Metal S/D approach for InGaAs S.H. Kim, IEDM 10 Metal S/D Advantages of metal Schottky S/D - atomically abrupt junction - robust against short-channel effect - low parasitic resistance - low temperature process capability 5

6 Purpose of this presentation 6 (A) High-k/In 0.53 Ga 0.47 As Interface Investigate La 2 O 3 /In 0.53 Ga 0.47 As interface properties and its scalability Demonstrate ALD compatibility and MOSFET performance (B) Metal S/D Contact Propose a thermally stable silicide contact on In 0.53 Ga 0.47 As for S/D regions

7 Outline (A) High-k/In 0.53 Ga 0.47 As Interface La 2 O 3 /In 0.53 Ga 0.47 As interface properties and its scalability Demonstrate ALD compatibility and MOSFET performance (B) Metal S/D Contact Thermally stable silicide contact on In 0.53 Ga 0.47 As for S/D regions 7

8 8 High-k stack fabrication n-in 0.53 Ga 0.47 As (S: cm -3 ) in-situ in-situ Oxide removal by HF 20% Sulfur passivation with (NH 4 ) 2 S (6%) at RT La 2 O 3, deposition by e-beam or ALD ( (La( i PrCp) 3 ) - H 2 O ) TiN /W gate electrode depo./pattern Post metallization annealing (PMA) in FG (H 2 :N 2 =3:97% ) for 5min Backside Al contact Measurement TiN *W (5 nm) La 2 O 3 n-ingaas S: (cm -3 ) InP Al *W layer, used as oxygen supply layer to prevent O 2 vacancy formation in La 2 O 3.

9 Intensity (a.u.) Interface Reaction : La 2 O 3 and HfO 2 (10 nm) W HfO 2 InGaAs (10 nm) W As 2p 3/2 As-oxide Substrate Ga 2p 3/2 Substrate In 3d 5/2 Ga-oxide Ga-O-La In-oxide Substrate In-O-La La 2 O 3 InGaAs PMA 500 o C Binding Energy (ev) Metal PMA Metal PMA HfO 2 HfO 2 + suboxides La La 2 O 2 O 3 3 IL La3.1 In 1.9 Ga 2.5 O 12 In 0.53 Ga 0.47 As In 0.53 Ga 0.47 As La 2 O 3 and channel react and form LaInGaO x IL. 9

10 Oxide to substrate HAXPS peak intensity ratio Capacitance (µf/cm 2 ) Metal gate effect on interface reaction La 2 O 3 (10 nm) In 3+ /In Ga 1+ /Ga As 3+ /As PMA 420 o C 1.0 PMA 420 o C IL w/o gate W TiN(10nm) (13nm) /W(3nm) khz 10 khz 100 khz 1 MHz Gate Voltage 5 khz 10 khz 100 khz 1 MHz Oxygen from the gate, triggers IL formation. By appropriate IL formation, D it in the mid (ev -1 cm -2 ) can be achieved. poor IL TiN W thin W La 2 O 3 10 nm La 2 O 3 In 0.53 Ga 0.47 As D it : 3x10 13 (ev -1 cm -2 ) appropriate IL D it : 7x10 11 (ev -1 cm -2 ) 10

11 Capacitance (µf/cm 2 ) D it (ev -1 cm -2 ) La 2 O 3 scalability and interface stability PDA 400 o C+PMA 320 o C CET = 0.73 nm La 2 O 3 Thickness: 4.0 nm 4.5 nm 5.0 nm 5.5 nm 100 khz Gate Voltage k eff ~ La 2 O 3 = 4.0 nm La 2 O 3 = 5.5 nm E-E i = 0.1 ev By optimizing process, obtaining CET= 0.73 nm ( C max, 100kHz =2.82 mf/cm 2 ) is possible PDA 400 o C PMA ( o C) D it mid ev -1 cm -2 is possible at scaled dielectric thickness and high annealing tolerance. 11

12 Outline (A) High-k/In 0.53 Ga 0.47 As Interface Investigate La 2 O 3 /In 0.53 Ga 0.47 As interface properties and its scalability La 2 O 3 ALD compatibility and MOSFET performance (B) Metal S/D Contact Thermally stable silicide contact on In 0.53 Ga 0.47 As for S/D regions 12

13 Thickness (nm) Growth rate (nm/cycle) La La( i PrCp) 3 La 2 O 3 synthesis by ALD ALD method is widely used for high-k fabrication. Oxidant: H 2 O Purge: Ar Metal Precursor: C 2 H Growth Temperature ( o C) 3.0 Can oxidize at low 1.0 temperature 150 o C Low carbon contamination (C ~ 0.44%) compared to Number of Cycles other La- precursors Ref: T. Suzuki JVST(A) 30, on n-in 0.53 Ga 0.47 As ALD 0.12 nm/cycle

14 ALD-La 2 O 3 layer TOA=90 o TiN Thin 150 o C 75 cyles InGaAs TiN W La 2 O 3 In 0.53 Ga 0.47 As PMA 320 o C Poly-crystalline La 2 O 3 with minimum interfacial layer (<0.5nm) 10 nm IL 1 3 d1=0.32nm Φ12=34.8 o 2 d2=0.20nm Φ23=36.1 o d3=0.32nm Diffraction analysis shows hexagonal crystalline structure. 14

15 Capacitance (µf/cm 2 ) D it (ev -1 cm -2 ) ALD-La 2 O 3 electrical characteristics PMA 320 o C ALD 150 o C D it : 6.8x10 11 (ev -1 cm -2 ) khz khz 100 khz 0 1 MHz Gate Voltage D it in the mid (ev -1 cm -2 ) is sustained for EB and ALD-La 2 O 3 and at sub-nm CET for EB case. (1) N-passivated HfO 2 (2) ZrO 2 ALD-La 2 O 3 EB-La 2 O 3 (3) HfO 2 /Al 2 O 3 (2) ZrO 2 /Al 2 O CET (nm) E-E i = 0.1 ev (1) V. Chobpattana, APL 102, (2) J. Huang, IEDM 09 (3) S. Takagi, IEDM 12 15

16 Drain Current (A) Mobility (cm 2 /Vs) InGaAs MOSFET with ALD-La 2 O 3 Al ALD-La 2 O 3 TiN/W Al SiO Ni- Ni- InGaAs p-ingaas InGaAs (Zn: cm -2 ) p-inp V d = 1 V V d = 0.05 V SS~130 mv/dec L/W: 50/50 mm Gate Voltage (V) 900 CET= 1.1nm Si- universal 400 N 300 a = cm N s (cm -2 ) Good MOSFET operation with mobility higher than Si-universal is confirmed. 16

17 Intensity (a.u.) Capacitance (mf/cm 2 ) 168 S 2p 164 Sulfur passivation effect La 2 O 3 Ga 3s 160 ALD- La 2 O 3 InGaAs with S w/o S TOA=90 o Binding Energy (ev) D it : 7.0x10 11 (ev -1 cm -2 ) with S PMA 320 o C D it : 8.2x10 11 (ev -1 cm -2 ) w/o S khz 10 khz khz 1 MHz Gate voltage (V) TiN Thin W ALD- La 2 O 3 InGaAs Unlike (1) Al 2 O 3 and (2) HfO 2, S passivation is not mandatory for achieving low D it. advantage for industrial application (1) H.D. Trinh, APL 97, (2) E. O Connor, APL 92,

18 Outline (A) High-k/In 0.53 Ga 0.47 As Interface Investigate La 2 O 3 /In 0.53 Ga 0.47 As interface properties and its scalability Demonstrate ALD compatibility and MOSFET performance (B) Metal S/D Contact Thermally stable silicide contact on In 0.53 Ga 0.47 As for S/D regions 18

19 Intensity (a.u.) Ni reaction with substrate As 2p 3/2 Ga 2p 3/2 In 3d 5/2 w/o PMA 400 o C Alloy Substrate no PMA Ni (10 nm) InGaAs 400 o C Ni-InGaAs InGaAs 500 o C Ga 2 O Binding energy (ev) 500 o C Ga 2 O 3 Ni-InGaAs InGaAs Ni-InGaAs composition strongly depends on PMA temperature. 19

20 Ni-InGaAs for scaled device structures gate bulk (b) FinFET gate candidate S/D approach for scaled device structures (c) SiNW FET Nanowire gate interface roughness S.H. Kim, IEDM 10 III-V-OI SOI Ni encroachment S.H. Kim, VLSI 13 silicide Si fin Silicide silicide Nanowire Si nanowire Abrupt, controllable interface required for 3D transistor application. 20

21 Intensity (a.u.) Intensity (a.u.) 8 sets NiSi 2 formation on InGaAs PMA 400 o C As 2p 3/2 substrate 400 o C 500 o C 600 o C Si (1.9nm) Ni (0.5nm) p-ingaas Ref: A. Ishizaka Surface Science 174, nm p-ingaas 859 Ni 2p 3/2 NiSi NiSi ev Ni 851 Binding energy (ev) 849 NiSi 2 /InGaAs interface is more stable at a wider thermal treatment window Ga 2p 3/2 substrate In 3d 5/2 substrate o C 500 o C 600 o C o C 500 o C 600 o C Binding energy (ev) 21

22 J diode (A/cm 2 ) NiSi 2 /InGaAs electrical properties Hole barrier height (ev) Metal (10nm)/In 0.53 Ga 0.47 As Ni 600 o C o C o 1.1 C 10-1 NiSi Gate voltage (V) NiSi 2 (10nm)/In 0.53 Ga 0.47 As PMA ( o C) Ideality Factor JV characteristics, Schottky barrier height and ideality factor for NiSi 2, does not change for PMA temperature up to 600 o C. 22

23 Conclusions La 2 O 3 /In 0.53 Ga 0.47 As gate stack: LaInGaO interface layer (IL) is formed at La 2 O 3 /InGaAs - Thermally stable, La 2 O 3 /In 0.53 Ga 0.47 As gate stack with CET=0.73nm, D it of mid (ev -1 cm -2 ) can be achieved. ALD processed La 2 O 3 gate dielectric - High quality interface (D it of mid (ev -1 cm -2 ) ) comparable to e-beam La 2 O 3. NiSi 2 /In 0.53 Ga 0.47 As for metal S/D: Inhibit interface reaction with NiSi 2 up to 600 o C with nearly ideal diode characteristics - Applicable S/D scheme with highly scaled channel for future III-V-OI and nanowire designs. 23

24 24 Acknowledgments This work was granted by JSPS through FIRST Program initiated by the Council for Science and Technology Policy (CSTP).