Disruptive technological routes to monitor temperature and improve thermal management in GaN HEMTs

Transcription

1 1 Disruptive technological routes to monitor temperature and improve thermal management in GaN HEMTs M. LESECQ (1), F. COZETTE (1), M. ABOU DAHER (1), M-R. IREKTI (1), M. BOUCHERTA (1), N. DEFRANCE (1), Y. CORDIER (2) & J-C. DE JAEGER (1) (1) IEMN : Institut d Electronique de Microélectronique et de Nanotechnologies (2) CRHEA : Centre de Recherche sur l'hétéro-epitaxie et ses Applications

2 INTRODUCTION GaN HEMTs for high power / high frequency applications (Satellite communications and radar systems) Power density can exceed 4W/mm at 4GHz [1] GaN HEMTs for power converter (Automotive industry commercial devices) Breakdown voltage can reach 6V [2-3] (switching frequency of 1MHz) HIGH OPERATING TEMPERATURE Decrease of electron mobility strong consequence on DC and RF performances Damages induced by thermal stress reducing of Mean Time To Failure Importance to monitor temperature of GaN HEMTs in operating conditions Need to improve thermal management to overcome limitations encountered on SiC substrate [1] Y-F. Wu et al, in Device Research Conference, 26 64th (June 26), pp [2] Y. Wanget et al, in Energy Conversion Congress and Exposition, 21 IEEE, pp , 21. [3] S. Ji et al, in Power Electronics, IEEE Transactions on, vol. 28, no.9, pp ,

3 OUTLINE 1. Temperature monitoring in operating GaN HEMTs : Thermal sensor integration Objectives and sensor design Technological process Characterization (choice of sensor metallisation, influence of sensor bias, temperature measurement) Conclusion 2. Thermal management improvement GaN HEMTs on free-standing GaN substrates Objectives Samples description Technological process (optical and e-beam lithography) and measurement Conclusion and perspectives GaN HEMTs on diamond substrates obtained through layer transfer technology Objectives Technological process overview Technological process details and results Conclusion and perspectives 3

4 OUTLINE 1. Temperature monitoring in operating GaN HEMTs : Thermal sensor integration Objectives and sensor design Technological process Characterization (choice of sensor metallisation, influence of sensor bias, temperature measurement) Conclusion 2. Thermal management improvement GaN HEMTs on free-standing GaN substrates Objectives Samples description Technological process (optical and e-beam lithography) and measurement Conclusion and perspectives GaN HEMTs on diamond substrates obtained through layer transfer technology Objectives Technological process overview Technological process details and results Conclusion and perspectives 3

5 Temperature monitoring in GaN HEMTs PhD F. Cozette Objective : Temperature measurement of GaN HEMTs under DC and RF operating conditions Challenges : Sensor integration in short source-to drain spacing No modification of the reliable transistor fabrication process Sensor Design: Sensor based on four probes method V I Source Gate Drain Barrier AlN GaN buffer Hot spot HR-Si (111) Cross section of GaN HEMTs on silicon substrate with integrated sensor View of two-fingers gate HEMTs with integrated sensor 4

6 Technological process 1. Technological steps to fabricate transistor Alignment marks : Mo/Ni/Mo Ohmic contacts : Ti/Al/Ni/Au + Annealing Devices isolation : N + implantation Gate fabrication : Ni/Au Passivation N 2 pretreatment 1nm thick SiN layer deposited by PECVD Thickening pads Ti/Au Thin layer of SiN to enable heat propagation Temperature measurement near hot spot Necessary to avoid a parasitic electrode in gate-to-drain spacing No modification of the standard technological fabrication process View of two-fingers gate HEMTs 5

7 Technological process 2. Technological steps to integrate thermal sensor Microresistance fabrication by e-beam lithography Nickel, Width : 2nm, Thickness : 1nm Thickening pads fabrication by optical lithography (Ni/Au) Sensor S G S Sensor Pads S S D G Pads D Remark : Metallic access lines to microresistance go over the gate metallisation Needing to check the electric continuity The cross between gate metallisation and sensor brings a low additional parasitic capacitance View of access line going over gate metallisation 6

8 Rc (Ω) Sesnor self-heating ( C) 7 Study on sensor metallisation T ( C) Sensor resistance versus temperature for different metallisation : Gold, Nickel, Platinum (sensor length : 5µm) Choice of Nickel for sensor metallisation Better sensitivity : 1.2 Ω / C Low self-heating :.7 C at P inj =6µW Sensor self-heating calculation : ΔT c = R thc P c R thc = ΔR c SΔP c R thc : thermal resistance of sensor P c : power dissipated by sensor due to applied current ΔR c : variation of sensor resistance due to selfheating P(µW) Sensor self-heating (length 5µm) versus sensor power dissipated

9 I DS (A/mm) Gain (db) 8 DC and RF characteristics on HEMTs influence of sensor bias Measurement on a 2 x 25 x.2 µm 2 AlGaN/GaN HEMT with sensor (with and without bias) I DS (ma/mm) DC characteristics (V GS : -6V step -1V) Bias sensor No bias sensor V DS (V) V DS (V) I DS,max V DS =1V & V GS =V Gain (db) Current gain modulus H 21, Mason s unilateral gain (U) versus frequency at V GS = -3V and V DS = 4 V h 21 no bias sensor U no bias sensor h 21 bias sensor U bias sensor 1G 2G 3G 4G 5G 1G 2G 3G 4G 5G f (Hz) F (Hz) F T = 28 GHz, F MAX = 42 GHz No influence of sensor biased on DC and RF characteristics

10 T ( C) ΔT ( C) Temperature measurement - Comparison with thermal simulation I D (ma/mm) Measurement with sensor between source and drain L SD = 2.6 µm I D (V DS ) and T (V DS ) V DS (V) T( C) T( C) Temperature versus dissipated power Inset : sensor resistance versus temperature R S (Ohm) T( C) Measurement Simulation P(W/mm) P (W/mm) Remark : Simulation with a physical thermal model developed at IEMN [4] P(W/mm) R thmeas (K.mm/W) R thsim (K.mm/W) A temperature of 11 C for a dissipated power of 5.4W/mm is obtained. [4] M.Rousseau et al, in Applied physics letters, vol.11, pp. 1-3, 212 9

11 1 Conclusion No modification of reliable transistor fabrication process but adding only two steps to integrate temperature sensor Temperature sensor integrated in short source-to-drain distance (RF applications) Sensor S D No modification of DC and RF characteristics of GaN HEMTs with sensor under bias Temperature measurement of 11 C for a dissipated power of 5.4W/mm (in agreement with thermal simulations) Potential applications Reliability tests : Use this type of sensor to measure accuratly temperature (near hot spot) and identify mechanisms to failure Monitor operating temperature in real time and adjust bias conditions

12 OUTLINE 1. Temperature monitoring in operating GaN HEMTs : Thermal sensor integration Objectives and sensor design Technological process Characterization (choice of sensor metallisation, influence of sensor bias, temperature measurement) Conclusion 2. Thermal management improvement GaN HEMTs on free-standing GaN substrates Objectives Samples description Technological process (optical and e-beam lithography) and measurement Conclusion and perspectives GaN HEMTs on diamond substrates obtained through layer transfer technology Objectives Technological process overview Technological process details and results Conclusion and perspectives 11

13 12 Thermal management improvements (1) GaN HEMTs on free-standing GaN substrates PhD R. Irekti Objective : Barrier AlGaN Spacer AlN (1nm) Canal GaN ( 1 nm) Buffer GaN (> 1.5 µm) ~2 nm SiN Cap ~2 nm AlGaN25% ~1 nm AlN spacer ~17 µm GaN nid Thick buffer layer for electrical isolation ~2 nm SiN Cap ~2 nm AlGaN25% ~1 nm AlN spacer ~4 µm GaN nid Nucleation layer AlN/GaN Substrat Si HR GaN FS Substrate GaN FS Substrate Standard Heterostructure on silicon substrate Heterostructres on free-standing GaN substrate Substrate Lattice mismatch with GaN (%) Thermal conductivity (W/cm.K) substrate cost GaN $ (2 inches) Si(111) $ (4 inches) + - Low dislocations density thanks to homoepitaxy No thermal barrier at GaN/Si interface Cost Needing of thick buffer layer for electrical isolation

14 13 Samples description MOCVD growth C-V CC293E RMS=.2nm Vp -5,5 V Ns 1, cm -2 e AlGaN 2 nm Nd min cm -3 Low TDD cm -2 CCOO293E Surface roughness Cathodoluminescence RMS=.1nm C-V Vp CC294E -5,5 V Ns 1, cm -2 e AlGaN 2 nm Nd min cm -3 CCOO294E Low TDD cm -2

15 Technological process based on optical lithogaphy Ohmic contacts : Ti/Al/Ni/Au + Annealing Devices isolation : N + implantation Gate fabrication : Ni/Au Passivation N 2 pretreatment 5nm / 15nm thick SiN /Si 2 layer deposited by PECVD Thickening pads Ti/Au Optical views of HEMTs on GaN substrate No modification of the standard technological fabrication process CCOO293E Hall effect measurement : R = 319 Ω µ = 241 V/m.s N S = cm -2 TLM measurement : R C = 1.12 Ω.mm R = 4 Ω I 1V = 31 µa I MAX =1.5 1V (d=5µm) CCOO294E Hall effect measurement : R = 37.9 Ω µ = 23 V/m.s N S = cm -2 TLM measurement : R C = 1.2 Ω.mm R = 496 Ω I 1V = 2 µa I MAX =1.1 1V (d=5µm) Coplanar waveguides fabricated on both samples RF loss lower than.7db/mm at 1GHz and 2dB/mm à 4GHz on both samples 14

16 I DS (A/mm) I GS (A) I GS (A) I DS (A/mm) I GS (A) I GS (A) Gated- TLM measurement (L SD =1µm L G =2µm) CCOO293E I DS -V DS characteristics V GS = -5v step -1V V DS (V) 1.2 x x x x x x V GS (V) I GS -V GS characteristics Direct - Inverse V GS (V) CCOO294E I GS -V GS characteristics Direct - Inverse I DS -V DS characteristics V GS = -5v step -1V V DS (V) 8 x x x x V GS (V) V GS (V) 15

17 16 Technological process based on e-beam lithogaphy Short gate lengths (75nm 2nm) to achieve high RF performances Technological challenge : Adapt the standard process for GaN substrate (Not so easy! ) Stable process on silicon substrate Metallic alignment marks Ohmic contacts Device isolation Gate fabrication Adjustements required Development of deep etching process Optimisation of lithography parameters and annealing conditions No optimisation needing in a first time Optimisation of lithography parameters New process on GaN substrate Etched alignment marks Ohmic contacts Device isolation Gate fabrication Passivation No optimisation needing in a first time Passivation

18 17 Process details Etched alignment marks Inductively Coupled Plasma Etching : Etching depth : 55 6 nm 55nm SEM views of etched sidewalls Vertical etched sidewalls, high etching depth for e-beam screening

19 I (A/mm) Ohmic contacts Source to drain distance smaller than expected L SD =1,9µm L SD =2,9µm L SD =4µm L SD =4,8µm Optical views of ohmic contacts after annealing Measurement on CC294E Hall effect measurement : R = 322 Ω µ = 1784 V/m.s N S = cm -2 TLM measurement : R C = 1.5 Ω.mm R = 384 Ω I 1V = few µa I MAX =1 1V (d=1.5µm) 1,2 1,8,6,4, , ,4 -,6 V (V) -,8-1 -1,2 d = 1.5µm d = 2.5µm d = 9.7µm d = 19.6µm d Optimisation of annealing conditions under progress (Recent results : R C <.35 Ω.mm ) 18

20 I DS (A/mm) 19 Gate fabrication Optimisation of e-beam parameters Tri-layers resist stack : PMMA / PMMA MMA / PMMA Access pads : Gate : With optimal dose L G =193nm L G =148nm L G =92nm DC Characteristics (V GS : 1V -6V step -1V) I D (V DS ) sweep L G = 3 nm, L DS = 2 µm, V GS (from -5 to 1 V by step of 1V) 8 8 I D (ma/mm) V DS (V) V DS (V) L G =3nm L DS =2µm I DS,max V DS =1V & V GS =1V

21 2 Conclusion AlGaN/GaN growth on FS-GaN substrate by MOCVD low TDD ~ cm -2 Thick GaN buffer layer for electrical insulation (17µm and 4µm) RF loss lower than.7db/mm at 1GHz and 2dB/mm at 4GHz Fabrication process based on optical lithography R ~ 32 Ω; µ = 2 V/m.s; N S = cm -2 R C ~ 1.5 Ω.mm (optimization needed on annealing conditions) DC characterization of HEMTs (L G =2µm) : I DS =.55A/mm at V DS =5V and V GS =V Fabrication process based on e-beam lithography Etched alignment marks Tri-layers resist process to obtain short-gate length Optimisation of ohmic contacts annealing condition Perspectives RF and load-pull measurement Crucial point : Thermal characterizations (Infra-Red camera) comparison with results on SiC substrate

22 OUTLINE 1. Temperature monitoring in operating GaN HEMTs : Thermal sensor integration Objectives and sensor design Technological process Characterization (choice of sensor metallisation, influence of sensor bias, temperature measurement) Conclusion 2. Thermal management improvement GaN HEMTs on free-standing GaN substrates Objectives Samples description Technological process (optical and e-beam lithography) and measurement Conclusion and perspectives GaN HEMTs on diamond substrates obtained through layer transfer technology Objectives Technological process overview Technological process details and results Conclusion and perspectives 21

23 OUTLINE 1. Temperature monitoring in operating GaN HEMTs : Thermal sensor integration Objectives and sensor design Technological process Characterization (choice of sensor metallisation, influence of sensor bias, temperature measurement) Conclusion 2. Thermal management improvement GaN HEMTs on free-standing GaN substrates Objectives Samples description Technological process (optical and e-beam lithography) and measurement Conclusion and perspectives GaN HEMTs on diamond substrates obtained through layer transfer technology Objectives Technological process overview Technological process details and results Conclusion and perspectives 21

24 Thermal management improvements (2) GaN HEMTs on diamond substrates obtained through layer transfer technology PhD M. Abou Daher Objective : Remove silicon growth substrate and replace it by a high thermal conductive substrate in order to improve the thermal management expected to strongly influence the performance and the reliability of GaN HEMTs Advantage Possibility to use conductive silicon substrates for AlGaN/GaN growth Low cost regarding high resistive silicon substrate Low surface roughness better cristalline quality of AlGaN/GaN growth (low TDD) Technological challenge Etch nucleation and adaptation layers (constituting a thermal barrier) Bonding on host substrate (without adding thermal barrier) 22

25 Layer Transfer Technology Process overview 23

26 24 Layer Transfer Technology Process overview - Low cost - GaN growth on large area - Devices fabrication know-how AlGaN/GaN HEMTs on Si(111) 2.7W/mm at 4GHz 2. Temporary bonding on sapphire substrate Altuntas P. et al, IEEE Electron Device Lett. 36, 4 (215) doi: 1.119/LED GaN-based devices on silicon substrate 3. Silicon growth substrate removal 6. GaN based devices on host substrate 4. Bonding onto host substrate 5. Debonding from sapphire substrate

27 24 Layer Transfer Technology Process overview - Low cost - GaN growth on large area - Devices fabrication know-how AlGaN/GaN HEMTs on Si(111) 2.7W/mm at 4GHz Technological development needed Adhesive layer compatible with the followed process and easily removable 2. Temporary bonding on sapphire substrate Altuntas P. et al, IEEE Electron Device Lett. 36, 4 (215) doi: 1.119/LED GaN-based devices on silicon substrate 3. Silicon growth substrate removal 6. GaN based devices on host substrate 4. Bonding onto host substrate 5. Debonding from sapphire substrate

28 24 Layer Transfer Technology Process overview - Low cost - GaN growth on large area - Devices fabrication know-how AlGaN/GaN HEMTs on Si(111) 2.7W/mm at 4GHz Technological development needed Adhesive layer compatible with the followed process and easily removable Existing method to etch silicon Optimization needed Altuntas P. et al, IEEE Electron Device Lett. 36, 4 (215) doi: 1.119/LED GaN-based devices on silicon substrate 2. Temporary bonding on sapphire substrate 3. Silicon growth substrate removal Avoid cracks at the interface GaN/Silicon due to lattice mismatch parameter 6. GaN based devices on host substrate 4. Bonding onto host substrate 5. Debonding from sapphire substrate

29 24 Layer Transfer Technology Process overview - Low cost - GaN growth on large area - Devices fabrication know-how AlGaN/GaN HEMTs on Si(111) 2.7W/mm at 4GHz Technological development needed Adhesive layer compatible with the followed process and easily removable Existing method to etch silicon Optimization needed Altuntas P. et al, IEEE Electron Device Lett. 36, 4 (215) doi: 1.119/LED GaN-based devices on silicon substrate 2. Temporary bonding on sapphire substrate 3. Silicon growth substrate removal Avoid cracks at the interface GaN/Silicon due to lattice mismatch parameter 6. GaN based devices on host substrate 4. Bonding onto host substrate 5. Debonding from sapphire substrate Technological development needed Interlayer used for bonding must not constitute a thermal barrier and must be electrically resistive

30 24 Layer Transfer Technology Process overview - Low cost - GaN growth on large area - Devices fabrication know-how AlGaN/GaN HEMTs on Si(111) 2.7W/mm at 4GHz Technological development needed Adhesive layer compatible with the followed process and easily removable Existing method to etch silicon Optimization needed Altuntas P. et al, IEEE Electron Device Lett. 36, 4 (215) doi: 1.119/LED GaN-based devices on silicon substrate 2. Temporary bonding on sapphire substrate 3. Silicon growth substrate removal Avoid cracks at the interface GaN/Silicon due to lattice mismatch parameter 6. GaN based devices on host substrate 4. Bonding onto host substrate 5. Debonding from sapphire substrate Technological development needed Interlayer used for bonding must not constitute a thermal barrier and must be electrically resistive No major difficulty Temporary bonding layer removal

31 24 Layer Transfer Technology Process overview - Low cost - GaN growth on large area - Devices fabrication know-how AlGaN/GaN HEMTs on Si(111) 2.7W/mm at 4GHz Technological development needed Adhesive layer compatible with the followed process and easily removable Existing method to etch silicon Optimization needed Altuntas P. et al, IEEE Electron Device Lett. 36, 4 (215) doi: 1.119/LED GaN-based devices on silicon substrate 2. Temporary bonding on sapphire substrate 3. Silicon growth substrate removal Avoid cracks at the interface GaN/Silicon due to lattice mismatch parameter 6. GaN based devices on host substrate 4. Bonding onto host substrate 5. Debonding from sapphire substrate Technological development needed GaN HEMTs with improved thermal management Interlayer used for bonding must not constitute a thermal barrier and must be electrically resistive No major difficulty Temporary bonding layer removal

32 Layer Transfer Technology - details Step 2 : Temporary bonding on sapphire substrate Objective : Resist layer must be compatible with the process and must be easily removable at the end. Test with different resist layers focus on resist SPR 22 for its excellent adhesion (dry and wet) and plating characteristics and possibility to coat a 1µm-thick film with good uniformity. Device at the end of process with the use of SPR resist Step 3 : Silicon growth substrate removal Objective : Avoid cracks at the interface GaN/Silicon due to lattice mismatch parameter. Test with different etching procedure focus on lapping and dry etching Mechanical lapping to thin silicon substrate down to 1µm Xe F 2 based etching (etchning rate ~ 4µm/mn) x5 x2 Backside view of devices (through GaN layer) 25

33 26 Layer Transfer Technology details Step 4 : Bonding onto host substrate 1 st test : bonding with 3M Thermally Conductive Epoxy Adhesive TC-281 3M Thermally Conductive Epoxy Adhesive TC-281 is a thermally conductive 2-part epoxy using boron nitride (BN) filler for good thermal conductivity with high adhesion. Thermal conductivity : W/m.K ; Volume resistivity : Ω.cm TC281 Host substrate (AlN) Bonding at room temperature Optical views of transferred devices CPW characterization.8 db/mm at 4GHz HEMTs characterization under progress 2 nd test : bonding with AlN interlayer deposited by sputtering EDS (energy dispersive X-ray spectrometry) AlN 25nm Host substrate 3 rd test : bonding without interlayer collaboration with CEA-LETI (ANR GaNYMEDE)

34 27 Conclusion Layer transfer technology developped to enhance thermal dissipation replace Si substrate by a high thermal conductive substrate (such as diamond) Technological challenges Silicon substrate removal Development of process to remove silicon without cracks in GaN layer Bonding onto host substrate Use of a thermally conductive epoxy as interlayer Measurement to be done Studies in progress about AlN interlayer Collaboration with CEA-LETI for bonding without interlayer Perspectives DC, RF and load-pull measurement Crucial point : Thermal characterizations (Infra-Red camera) Heat dissipation improvement?

35 28 THANKS FOR YOUR ATTENTION Thanks to RENATECH network for the support Thanks to GaNEX cluster and DGA for phd funding