Half-pitch 15-nm metal wire circuit fabricated using directed self-assembly of PS-b-PMMA

Transcription

1 Half-pitch 15-nm metal wire circuit fabricated using directed self-assembly of PS-b-PMMA Y. Seino, Y. Kasahara, H. Kanai, K. Kobayashi, H. Kubota, H. Sato, S. Minegishi, K. Miyagi, K. Kodera, N. Kihara, Y. Kawamonzen, T. Tobana, M. Shiraishi, S. Nomura and T. Azuma EUVL Infrastructure Development Center A part of this work was funded by the New Energy and Industrial Technology Development Organization (NEDO) in Japan under the EIDEC project. 1

2 Outline Background of this work: EIDEC original sub-15-nm Line and Space (L/S) process using PS-b-PMMA lamellar block copolymer (BCP) Process performance of DSA lithography and pattern transfer: Defects and L/S pattern Critical Dimensions (CD) Electrical yield verification of HP (Half pitch) 15-nm metal wire circuits applying DSA process: open yield test and physical failure analysis Summary 2

3 Outline Background of this work: EIDEC original sub-15-nm Line and Space (L/S) process using PS-b-PMMA lamellar block copolymer (BCP) Process performance of DSA lithography and pattern transfer: Defects and L/S pattern Critical Dimensions (CD) Electrical yield verification of HP (Half pitch) 15-nm metal wire circuits applying DSA process: open yield test and physical failure analysis Summary 3

4 E DSA Technology Challenges From sub-15-nm to sub-10-nm DSA Process DSA Metrology DSA Material Electrical Yield Verification Guide Pattern Design DSA Simulation T. Kato, Hitachi High- Technologies 10/26 17:20 K. Kodera, EIDEC, 10/27 14:10 States Our target at EIDEC is to evaluate DSA performance for semiconductor device manufacturing through electrical yield verification. 4

5 Comparison of Sub-15-nm L/S Process Flows X-PS (cross linked-ps) coating PTD resist patterning LiNe flow SMART TM flow EIDEC original flow pinning guide front forming process Neutral layer coating NTD resist patterning No special pinning guide material required PTD resist patterning X-PS etching Resist stripping Neutral layer grafting / rinse Neutral layer etching Resist stripping 1/2 L0 3/2 L0 PS PMMA Pinning layer grafting / rinse PS PMMA Pinning guide back forming process Resist trim / SOG shallow etching No resist strip step required Neutral layer grafting / rinse 1/2 L0 PMMA PS BCP coating / annealing BCP coating / annealing BCP coating / annealing Dry development Dry development Dry development EIDEC s simple process using the resist and spin-on glass (SOG) as pinning guides requires neither guide materials nor any resist strip process. 5

6 EIDEC COOL Process ArF Immersion Exposure Resist Spin-on-Glass (SOG) Spin-on-Carbon (SOC) Hard Mask Resist Trimming & SOG Partial Etch Pinning Guide DSA lithography Neutral Layer Grafting Neutral Layer BCP Apply & Anneal BCP: PMMA PS Dry Development DSA pattern transfer SOG Etch SOC Etch 200nm 200nm Y. Seino et al., SPIE (2015) Y. Kasahara et al., SPIE (2015) EIDEC chemo- and grapho-coordinated line epitaxy (COOL) process development using the resist trim etch and SOG shallow etch including DSA pattern transfer. 6

7 Outline Background of this work: EIDEC original sub-15-nm Line and Space (L/S) process using PS-b-PMMA lamellar block copolymer (BCP) Process performance of DSA lithography and pattern transfer: Defects and L/S pattern Critical Dimensions (CD) Electrical yield verification of HP (Half pitch) 15-nm metal wire circuits applying DSA process: open yield test and physical failure analysis Summary 7

8 DSA Defect Classification after SOG Etch DSA lithography DSA pattern transfer NGR3520 Dislocation defects Which DSA process factor is the cause of etching short and open defects? inspection area mm 2 Grid defects CAD edge detected image CAD image DSA lithography and DSA pattern transfer defects were classified. 8

9 DSA L/S Pattern CDs & Roughness after SOG Etch Line CD SOG LWR Placement error Isolated PS line was placed in the center Space CD SOG LER L1 L2 L3 S3 S1 S2 S3 SOG SOC dry development Isolated PS Paired PS Paired PS Guide Mask design: 15-nm L/S E1 E2 E3 E4 E5 E6 L1 L2 L3 SOG etch S3 S1 S2 S3 Measured values Guide space CD is narrow. Sufficient roughness control? CG5000 Placement error T. Kato, 10/26 17:20 9

10 Analysis of Dislocation Defect: Experimental Results Defect dependence on guide CD Defect examples of electrical yield test wafer after SiO 2 RIE (Reactive Ion Etching) Typical defect: 4 metal short lines Dislocations are almost entirely short NG and point symmetrical short: 4 short: 5 short: 6 short: 7 short:5 open:1 Narrow guide resist CD Increase of defect density 2 mixed defects 10

11 Analysis of Dislocation Defect: Simulation and model SCFT Simulation using BCP chain conformation Single dislocation Double dislocation Typical defect: 4 metal short lines Counter segments of BCP are concentrated Model of defect generating Narrow guide PS blocks are concentrated PS PMMA Guide Concentrated PS blocks at the point of narrow guide result in the dislocation defects. 11

12 Analysis of Grid Defect: Experimental Results phase separation PMMA PS SOG SOC Process step trace dry development PS Shallow SOG etching SOG full etch Y. Seino et al., Microelectronic Engineering 134 (2015) Grid defect BCP phase separation With guide Hole pitch: 37.0-nm Finger print Hole pitch: 35.5-nm SOG SOC PS PMMA Taper angle L=Hole pitch * N Reduction of grid defects by process conditions Grid defects,i.e., PS connection under PMMA after phase separation, in SOG after shallow etching having periodic pitch, can be decreased with process conditions. 12

13 Analysis of Grid Defect: SCFT Simulation Kodera et al., J. Photopolym. Sci. Technol. 28, 683 (2015) Grid defect (GD) Vertical lamellar (VL) Mixed lamellar (ML) The suitable BCP 3D structure results in the decrease of the grid defects. 13

14 Outline Background of this work: EIDEC original sub-15-nm Line and Space (L/S) process using PS-b-PMMA lamellar block copolymer (BCP) Process performance of DSA lithography and pattern transfer: Defects and L/S pattern Critical Dimensions (CD) Electrical yield verification of HP (Half pitch) 15-nm metal wire circuits applying DSA process: open yield test and physical failure analysis Summary 14

15 Full Integration of HP 15-nm Metal Wire Circuits using DSA Process flow of the electrical yield test applying the DSA process is integrated. 15

16 HP 15-nm Metal Wire Circuits Fabricated from DSA Process HP 15-nm metal wires were fabricated from the DSA process. 16

17 Frequency 700 um Electrical Yield Verification of HP 15-nm Metal Wire Circuits 87 shots / wafer 10 units /1 shot Open yield verification n = 87shot 10 units Failure SiO 2 RIE OK chip electrical test SiO 2 RIE NG chip no test Passed T. Azuma et al., J. Vac. Sci. Technol. B 33(6), Metal wire resistance (Ω) Open yield verification of a 700-μm metal wire length on a 300-mm wafer substrate 17

18 Electrical Yield Dependence on the Thickness of Hard mask Thin SiO 2 layer Thick SiO 2 layer #1 #2 #3 #4 Failure 30% Passed 10% 30% yield was successfully achieved at 700 μm length at thinner SiO 2 thickness. 18

19 Physical Failure Analysis of HP 15 nm Metal Wire Circuit EBAC (Electron Beam Absorbed Current) image Electron Beam Amplifier Probe Probe GND Breaking Point EBAC Absorbed Current The contrast has clearly changed. Analysis of the thinner SiO 2 layer wafer by EBAC and TEM revealed metal open defects. 19

20 Metal Open Defects Originated from SiO 2 Etching Short Defects Passed:Mode 1 Numbers of passed units Passed SiO 2 Line CDs Failure: Mode 2 Failure:Mode 2 Failure:Mode 1 narrow SiO 2 lines high yield Mode 1: SiO 2 wiggling short Precise SiO 2 etching is required. Mode 2: perfect short relating to DSA process? DSA defects such as dislocation and grid defects are not observed. The SiO 2 etching short defects affect the metal open defects. 20

21 Etching Short Defects: DSA L/S Pattern CDs Control Cause of the metal open defects Y. Kasahara et al., MNE A6-C4 (2015) Effect of film thickness Narrow spaces after SOG RIE result in the SiO 2 etching short defects. Precise L/S CDs control of the DSA process is required for defect reduction. 21

22 Etching Short Defects: Roughness of DSA L/S Patterns RIE methods of roughness improvement after SOG etch RF (Radio Frequency) power in pulsed mode Depo-Etch Process Continuous Wave LWR: 3.7 nm LER: 2.9 nm RF pulse 1 K Hz, duty=50 % LWR: 2.5 nm LER: 2.6 nm Depo-Etch process aims at increasing PS residue after SOG RIE. No deposition LWR: 3.4 nm LER: 5.4 nm Depo-Etch LWR: 2.8 nm LER: 4.4 nm 100 nm 100 nm 200 nm 200 nm Roughness improvement of DSA process is important for defect reduction. 22

23 Summary DSA process performance relating to defects (dislocation and grid defect) and L/S pattern CD was evaluated using EIDEC original sub-15-nm L/S DSA process and simulation techniques. Electrical yield verification of HP 15-nm metal wire circuits fabricated from the DSA process was performed. 30% open yield was successfully achieved at 700 μm metal wire line length. The SiO 2 thickness affects the open yield and metal open defects were observed by physical failure analysis. It is revealed that L/S pattern CDs control and roughness improvement of the DSA process are required for reduction of etching short and open defects. 23

24 Thank you for your attention! A part of this work was funded by the New Energy and Industrial Technology Development Organization (NEDO) in Japan under the EIDEC project. We would like to thank NGR Inc., Hitachi High-Technologies Corporation and members of Super Clean Room (SCR) in National Institute of Advanced Industrial Science and Technology (AIST) for technical support. 24