ASIC Physical Design CMOS Processes Smith Text: Chapters 2 & 3 Weste CMOS VLSI Design Global Foundries: BiCMOS_8HP8XP_Training.pdf BiCMOS_8HP_Design_Manual.pdf
Physical design process overview CMOS transistor structure and fabrication steps Standard cell layouts Creation, verification & characterization of a standard-cell based logic circuit block Creation of a chip from circuit blocks 2
ASIC layout 3
ASIC Design Flow Behavioral Design Verify Function DFT/BIST & ATPG Gate-Level Netlist Verify Function Transistor-Level Netlist Verify Function & Timing DRC & LVS Verification Physical Layout Verify Timing 4 Mask Data
ASIC Design Flow 5
IC Floorplan 6
CMOS standard cell layout (generic) 7 Source: Weste CMOS VLSI Design
BiCMOS8HP NAND2_A Cell Yellow Pins Orange = Poly Blue = Metal1 (LEF file) 8 Cadence Encounter Cell Viewer Tool
BiCMOS8HP DFFS_B Cell (LEF file) Yellow Pins Orange = Poly Blue = Metal1 9 Cadence Encounter Cell Viewer Tool
Standard Cell-Based Block 10
Global Foundries BiCMOS8HP process cross-section Passivation 11
BiCMOS8HP process cross-section External Connections Via Via Aluminum Via Via Copper PC = Polysilicon 12 CA = Contact to diffusion/poly
BiCMOS8HP metallization options: AM Analog Metal (RF wiring) 13
Basic N-channel MOS transistor drain V GS + W L + V DS V GS + gate so urce bulk + V DS gate T ox p-type n-type so urce electrons E x mobile channel charge n-type drain depletion region fixed depletion charge bulk GND or VSS 14
CMOS Inverter Cross-Section 15 Source: Weste CMOS VLSI Design
Inverter cross-section with well and substrate contacts 16 Source: Weste CMOS VLSI Design
IC fabrication process 2 3 1 hour 4 5 1 wafer furnace spin resist grow crystal sa w grow oxide mask resist oxide etch As + 6 7 8 9 10 11 12 17 4. Grow oxide SiO2 5. Apply photoresist 6. UV light exposes resist 7. Remove exposed resist 8. Etch exposed oxide 9-10. Implant ions in exposed substrate 11. Strip resist 12. Etch oxide
CMOS Process steps P-substrate SiO2 layer Photoresist Expose and etch Etch SiO2 Remove photoresist Implant n-well Remove SiO2 18 Source: Weste CMOS VLSI Design
CMOS Process steps Deposit poly Etch Deposit SiO2 Etch Diffusion Remove SiO2 19 Source: Weste CMOS VLSI Design
Inverter mask set Generated by IC layout tools Layout is a set of patterns for each layer. N-well Poly N+ diffusion P+ diffusion Contacts Metal 20 Source: Weste CMOS VLSI Design
Inverter mask set 21
Standard Cell Mask Set (Submitted to foundry) Source: Smith, Figure 2.7 22
MOSIS fabrication processes (www.mosis.org) TSMC Fabrication Processes 28, 40, 65, 90, 130, 180 and 350 nanometer processes. Tiny2 program is also available on 65 and 180nm processes. GlobalFoundries Fabrication Processes 14 nm, 28 nm, 40 nm, 55 nm, 0.13 µm,0.18 µm, 9HP (90 nm), 8HP (0. 13 µm), 8XP (0.13 µm), 7WL (0.18 µm), 7RF SOI (0.18 µm) 7SW (0. 18 µm) 9WG (90 nm), 9WG (90 nm), and TinyChip processes. ON Semiconductor Fabrication Processes 0.7 µm high voltage CMOS, 0.5 µm CMOS, and 0.35 µm high voltage CMOS. ams AG Fabrication Processes 180 and 350 nanometer processes - CMOS and high voltage CMOS and SiGe-BiCMOS. AIM Fabrication Processes AIM Photonics Fabrication 23
(Older) MOSIS fab processes (http://www.mosis.org) AMI bought by ON Semiconductor: http://www.onsemi.com/ TSMC (Taiwan Semiconductor): http://www.tsmc.com =ON =ON Mentor Graphics ASIC Design Kit 24 Scalable CMOS Source: Weste CMOS VLSI Design
Scalable CMOS process design rules 25 1. 1 w ell 2. 2 active 3. 3 poly 10 (1.1) 3 (2.1) 5 (2.3) 3 (2.4) nwell nwell 3 0 or 4 (2.2) (2.5) nwell pdiff pdiff ndiff 0 (1.4) 9 (1.2) nwell pwell 4. 4 select pwell poly 2 (4.2) hot ndiff n-se lect p-se lect pdiff pwell ndiff p-se lect ndiff pdiff 3 (2.1) 5 (2.3) 3 (2.4) pwell pdiff nwell n-se lect ndiff 7. metal1 8. 8 via1 1 (7.3) pdiff poly 3 (7.1) 2 (8.4) poly 2 (8.5) via1 3 1 (8.3) metal2 co ntact (7.2a) m1 m2 active m1 co ntact poly 2 (8.5) 2 2 2 (8.1) (7.2b) 3 (8.2) ndiff 1 (7.4) 9. metal2 15. metal3 10. 9 overglass (microns) 14. via2 m2 via1 3 (9.2b) 4 (9.2a) m1 0 or 6 (1.3) 3 (9.1) 1 (9.3) 1 (4.3) 2 2 (14.1) m2 via2 3 (14.2) 2 (14.4) m2 3 (2.2) m3 via1 1 (14.3) 3 (4.1) 0 or 4 (2.5) m3 4 (15.2) 5. 5 poly contact via2 6. 6 active contact 2 (15.3) 1.5 (6.2a) 6 (15.1) 2 (3.2) 1.5 (5.2a) poly 2 2 (6.1a) glass 1 (3.5) 2 (6.3a) 6 (10.3) 1.5 (6.2a) m3 100 100 (10.1) pdiff 3 (3.4) 2 (3.3) 2 (3.1) poly 2 (5.3a) poly 2 2 (5.1a) nwell 2 (6.4a) 30 (10.4) m3 m2 15 (10.5) m1 Source: Smith, Figure 2.11
MOSIS Design Rules Smith text: Tables 2.7-2.9 26
MOSIS Design Rules Smith text: Tables 2.7-2.9 27
MOSIS Design Rules Smith text: Tables 2.7-2.9 28
MOSIS Design Rules Smith text: Tables 2.7-2.9 29
MOSIS Design Rules Smith text: Tables 2.7-2.9 30