AGOOD scheduling system enhances the benefits of

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009 381 A WIP Balancing Procedure for Throughput Maximization in Semiconductor Fabrication Jaewoo Chung and Jaejin Jang Abstract In a semiconductor fabrication line (fab), high throughput often guarantees high revenue and profit since relatively constant operating cost is required throughout the year; however, maintaining high throughput has been a challenging task due to complicated operational variables in a modern high-end wafer fabrication line. To deal these variables, the industry has developed a fab scheduling system consisting of several functional modules that focus on different areas of decision making. WIP balancing, which aims to prevent starvation of bottleneck toolsets, has been an important component for fab scheduling. This research proposes a new WIP balancing concept, which directly considers load levels of bottleneck toolsets for higher throughput. Also, an MIP (mixed integer programming) model is developed for the new WIP balancing. A performance test shows that the new approach increases throughput, especially when WIP level and product routing flexibility are low. Index Terms Fabrication, load balancing, mixed integer programming, scheduling, semiconductor, WIP balancing. I. INTRODUCTION AGOOD scheduling system enhances the benefits of modern automated semiconductor fabrication lines (fabs). It increases throughput while reducing work-in-process (WIP) and enables earlier detection of process failures. With less operator intervention in a standardized fab control, operations become more predictable and transparent. Since a modern high-end wafer fab involves very complicated operational variables, the fab scheduling system consists of several functional modules that focus on different areas of decision making. Fig. 1 shows a fab scheduling system (left box) and related fab operating systems (right boxes). This and other similar structures [1] are being used in industry. While a planning system makes long-term production plans at an aggregated level, a scheduling system makes a shorter production schedule with more frequent updates [1], [2]. In Fig. 1, the WIP balancing module in the scheduling system determines target production quantity for each layer, defined as a set of several sequential processing stages such as deposition, etching, metrology, and litho stage at its end. Based on this quantity, detailed schedules of each lot, toolset, and toolset group are Manuscript received May 23, 2008; revised February 24, 2009. First published July 07, 2009; current version published August 05, 2009. J. Jang is with the Department of Industrial and Manufacturing Engineering, University of Wisconsin-Milwaukee, Milwaukee, WI 53211 USA (e-mail: jang@uwm.edu). J. Chung was with the School of Industrial Engineering, Purdue University, West Lafayette, IN 47906 USA. He is now with the School of Business Administration, Kyungpook National University, Daegu 702-701, Korea (e-mail: chung@knu.ac.kr). Digital Object Identifier 10.1109/TSM.2009.2017666 made by other modules in the scheduling system. The lot-based scheduling module in the figure makes very detailed schedules for both individual lots and toolsets, based on the target production quantity. The area scheduling module, which focuses on specific processing areas such as photolithography (litho), diffusion, etching, and deposition areas, also makes detailed schedules by assigning the target production quantities to toolsets based on detailed process constraints. While the WIP balancing module focuses on longer term performance criteria, these detailed scheduling modules focus on short term ones. Sometimes rescheduling is required when unpredictable disturbances occur [3] [5]. Also, simulation helps fab scheduling by estimating gaps between scheduling and its implementation. The scheduling system guides the lot dispatching system [6] [10] and the automated material handling system (AMHS) at its lower hierarchy. WIP balancing has been widely used to achieve high utilization of toolsets in a fab [12], [31]. Performance measures in a fab are very complicated because of such characteristics as long ramp-up period, frequent product change, high productmix, reentrant flow, batch process, setup time and mask allocation. Consequently, fab managers often use indirect performance measures to increase operational efficiency. The conventional view regards the uniformity of WIP levels of processing stages based on flow times as an important criterion because it potentially increases toolset utilization and decreases waiting time of wafers in storage. This research proposes a new WIP balancing concept and a procedure called the toolset available WIP balancing (TAWB) to foster efficient fab scheduling, specifically for the litho stage, the bottleneck in most fabs. The new WIP balancing concept considers two main factors: load levels of litho toolsets and the target production volumes from the planning system. In previous studies, the load levels of toolsets were not considered for WIP balancing; hence, an already overloaded bottleneck toolset often gets even more wafers. The detailed method and benefits of TAWB are explained in Section III-B. TAWB is different from existing WIP balancing methods in two aspects. 1) New WIP balancing measure: The new measure uses the routing flexibility of each litho layer (measured by the number of toolsets that can process the litho layer). It also uses the current WIP level of an individual litho toolset while conventional methods use the WIP level of each litho layer. 2) Relaxing planning requirements: Lee et al. [11] pointed out that module lines often use a pull system while fab lines use a push system; as a consequence, a large amount of WIP often piles up between them. Also, there are binning, substitution, and product branch-off at the end of the 0894-6507/$26.00 2009 IEEE

382 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009 Fig. 1. Fab operating systems. fab lines (see the last part of this section). Fab lines and module lines are often located far from each other, sometimes belonging to different companies. All these factors make the synchronization of fab and module lines difficult; therefore, following the production guide from planning too closely can give unnecessarily tight constraints to scheduling. The method proposed in this paper relaxes requirements from production planning, i.e., the target production volume (Fig. 1), to maximize throughput. In a semiconductor manufacturing system, the front-end (fab) has more than 400 processing stages and uses more than 85% of the system s time and resources. In a fab, about of the lots waiting time and WIP are observed in front of the bottleneck stage, i.e., litho stage [12]. Each layer on a wafer requires its own mask (reticle) at this litho stage, and a mask change requires a non-negligible amount of setup time. The litho process is so sensitive that one layer can only be processed by a few dedicated toolsets approved after a series of tests using send-ahead lots or test wafers. This dedication limits the wafer s routing flexibility. The average up time of a litho toolset, including its idle time, is more than 90%. A litho toolset has about of unscheduled down time [13] with 10 20 days of MTBF (mean time between failure). Although this uptime rate is relatively high compared with other industries, its random disturbance has been regarded as an important characteristic [14], apparently because of the high standard of reliability for the expensive toolsets and the low routing flexibility. The back-end (module line) makes final products. One type of wafer from the front-end (fab) possibly becomes tens of different semiconductor products, or branches-off, depending on the attached materials, the required specifications of products and others. Chips are graded, or binned, by their quality, such as clock speed. Sometimes higher binned chips are downgraded, or substituted, to meet the due date of lower binned chips. Branch-off, binning, and substitution make tight synchronization of front-end and back-end production difficult and less relevant. Section II reviews previous studies on fab scheduling. In Section III, we develop the TAWB procedure and illustrate the use of the TAWB in an area scheduling module. Section IV compares the new method with two existing methods. II. PREVIOUS RESEARCH From the 1980s to the early 1990s a large number of studies focused on a single operational aspect of fab scheduling (e.g., lot releasing, due-date scheduling, batch scheduling, WIP balancing or load balancing). Since the mid 1990s, integrated solution procedures were proposed, often based on hierarchical approaches. Lot releasing methods attempted to avoid starvation of bottleneck toolsets by using the flow rate of a layer [16], [17]. For load balancing, mathematical programming and heuristic methods were frequently used, considering detailed operational aspects such as the toolset setup time and the number of available masks [19] [22]. Batch processing, which is common at such stages as diffusion, oxidation, litho and wet bench, was also studied [14], [23] [26]. Look-behind and look-ahead approaches were frequently used to form a batch [16], [25]. Some studies focused on due-date scheduling for ASIC (application-specific integrated circuit) manufacturers and foundry companies [27] [29]. The integrated approaches focused on multiple performance measures. Bai et al. [30] recognized the complexity of fab scheduling and proposed a hierarchical framework. Vargas-Vilamil et al. [31] proposed a three-layer hierarchical approach based on integrated product, optimization and dispatching steps. Based on the flow rate control procedure, the TB (two boundary) algorithm was introduced by Lou and Kager [17], and its robustness was confirmed by Yan et al. [32]. The TB algorithm tried to make surplus, the difference between planned and actual production, zero to determine TPQ (target production quantity) at the end of a shift. Many hierarchical approaches were developed based on the TB algorithm for WIP balancing [12], [18], [33] [37]. Lee et al. [12] proposed scheduling methods for lot release, WIP balancing, and load balancing based on a modified TB method. In industry, gaps between planning and scheduling were frequently observed, and some studies proposed daily planning procedure as an intermediate decision step of long-term planning and scheduling [32]. Dabbis et al. [35] proposed a dispatching-based scheduling that integrated WIP balancing (global criteria) and several dispatching criteria (local criteria) using a linear combination of these criteria. III. THE NEW WIP BALANCING METHOD: TAWB(TOOLSET AVAILABLE WIP BALANCING) In this section, we develop a new WIP balancing method called TAWB (toolset available WIP balancing) and illustrate use of the TAWB in an area scheduling module that centers on the bottleneck stage, photolithography (litho). (See [4], [5], [12], [27], [36], [37] for other bottleneck scheduling methods.) The new method in this section also shows by an MIP model

CHUNG AND JANG: A WIP BALANCING PROCEDURE FOR THROUGHPUT MAXIMIZATION IN SEMICONDUCTOR FABRICATION 383 TABLE I CALCULATING LAYER DEMAND (FOR PRODUCT i) how the WIP balancing module cooperates with the area scheduling module to maximize throughput of the current shift and the following shifts as well. The higher throughput in the bottleneck stage eventually creates higher actual production quantity (fab-out volume) over the long term. The detailed MIP modeling may need to adjust to reflect specifics of each fabrication site. TABLE II SCHEDULING INPUT DATA FROM MES A. Input for the New WIP Balancing Procedure The new procedure receives input from the planning system and the manufacturing execution system (MES) (Fig. 1). The production planning system determines target production volume for each of the front and back end, product type and time bucket. The time horizon and time bucket of planning vary from two months to a year and from a day to a week, respectively. Based on the target production volume, the WIP balancing module in the scheduling system determines target production quantity (TPQ) for each product type and process stage. Generally, its time horizon is a few months and its time bucket is a shift. Tables I and II show an example of input data for WIP balancing. The weekly target production volume is given for each week in Tables I and II shows the flow times, current WIP levels, and toolset dedications for each layer of a product, or a layer in short, which are available from the manufacturing execution system (MES). B. Overview of the TAWB Procedure This section overviews the detailed WIP balancing processes presented in Part C and Part D in Section III. Fig. 2 shows a flow chart of the new WIP balancing procedure, consisting of four sub-modules (M1 to M4). M1 calculates layer demands, i.e., standard production quantities, for layers based on the layers flow times (times from lot release to fab-out) and target production volumes given by product types from the planning system (Table I). M2 calculates the lateness indices for layers, which indicate urgency for processing, and M3 calculates the upper-limit production quantity (UPQ), the maximum allowed production quantity, based on the layer demands from M1 and the current WIP levels. Finally, M4 determines the target production quantity (TPQ) of each layer using a new MIP model and assigns available WIP of each layer to litho toolsets based on the lateness and UPQ. The new MIP model internally uses the concepts of LAW (layer available WIP) and TAW (toolset available WIP) to be explained below, for better WIP balancing. M1 and M2 have been used by many other researchers, while M3 and M4 are new in this research. In M2, the lateness index for each layer is the difference between its remaining flow time until fab-out and the remaining Fig. 2. Flow chart for the proposed WIP balancing procedure. calendar time until the designated fab-out time internally specified by the planning system. If the lateness of a layer is larger than a certain limit, it is assigned to at least one toolset for production in the MIP model (constraint (14) in Part D in Section III). In M3, the UPQ is obtained from a modified method of the two boundary heuristic [17]. The resultant UPQ in a shift can be larger than the production capacity of the litho toolsets;

384 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009 Fig. 3. Layer WIP balancing versus toolset WIP balancing. TABLE III CALCULATION OF UPPER-LIMIT PRODUCTION QUANTITY (UPQ) AND TOOLSET AVAILABLE WIP (TAW) (FOR PROJECT i) this loosened upper limit of the production quantity gives some flexibility for determining TPQ and is used to increase actual production quantity by the MIP model. Sometimes, starvation can not be avoided even with good WIP balancing from the two boundary method because of the low routing flexibility of wafers, as is illustrated in Fig. 3 and Table III. UPQ in Table III [and Fig. 3(a)] represents a conventional WIP balancing status based on layers, which we call layer WIP balancing. There are six layers, L1 to L6, in the table. In the last row of Table III [and Fig. 3(b)], we have another possible WIP balancing status based on toolsets, which we call toolset available WIP balancing. There are also six toolsets, T1 to T6 in the table. Although this layer WIP balancing looks good, since all layers have similar WIP levels, the toolset available WIP balancing in Fig. 3(b) is poor, since T1, T2, and T6 have much higher WIP levels than T3 and T4, and the toolsets 3 and 4 can be idle soon. The new MIP model calculates TPQ to maximize throughput for the current shift and maintain good toolset available WIP balancing to ensure the maximized throughput during the following shifts. The following notations are used in this model. 1) Data Sets: : Set of products. : Set of layers of product,. : Set of litho toolsets. : Set of weeks for demands. 2) Input Data: : Setup time of the litho toolset. : Flow time of product, layer (including average waiting time in days). : Sum of flow time of product from layer to final layer including the flow time of layer. : Number of available masks for product, layer. : Wafer processing time of product, layer on litho toolset. : Average wafer processing time of litho toolsets for product, layer. : Average wafer processing time on litho toolset. : Initial processing layer index. If toolset is processing product, layer at the beginning of the current shift, ; otherwise,. : WIP level of product, layer at the beginning of the current shift. : Target production volume for week given by the planning system. : Layer demand for product, layer. : Weight value of layers, if is the last layer of product i; otherwise,. : Toolset dedication. If product, layer can be processed at toolset, ; otherwise,. : Upper-limit production quantity (UPQ) for product, layer. : Current lateness (days) of WIP of product, layer. 3) Decision Variables: : Production quantity for product, layer from toolset during the current shift. : WIP of product, layer at the end of a shift. : Production assignment. If, ; otherwise,. C. Determination of Layer Demand, Layer Lateness, and UPQ 1) Layer Demand Calculation (M1 Module): Layer demand is the weekly target production volume times the flow time of the layer divided by 7 if the flow time of the layer is covered by one weekly target production volume: In Table I,. If the flow time of a layer is covered by two weekly target production volumes, a layer demand is determined based on the proportion of the weeks over the layer s flow time, i.e., if (1) or and (2) where and are the parts of in the 1st and 2nd weeks, respectively. If the flow time of layer 9 has 0.5 days in week 1 and 1.5 days in week 2 in Table I,. The subscript that

CHUNG AND JANG: A WIP BALANCING PROCEDURE FOR THROUGHPUT MAXIMIZATION IN SEMICONDUCTOR FABRICATION 385 TABLE IV CALCULATION OF LATENESS AND UPQ (FOR PROJECT i) In Table III, (here, it is assumed that 800 is the WIP level at the end of the previous shift). The TAW (toolset available WIP) in formula (5) of a tool set is a sum of the above average WIP levels ( s) for the tool set. : Toolset Available WIP for Toolset (5) appears on the right side of (1) and (2) does not appear on the left side because is a function of and in the if part of the equation. 2) Lateness Calculation (M2 Module): This index shows how much the layer production is behind schedule. If cumulative demand for a layer is larger than its cumulative WIP, lateness is increased by its flow time,. In Table IV, ( is less than,so is increased by ). 3) UPQ Calculation (M3 Module): This procedure uses two types of demand: rolling and pulling demand for the calculation of UPQ. The rolling demand for a layer is the sum of the layer demand from the current layer to the last layer. The pulling demand is the layer demand during the pulling period, which is assumed to be the preceding two days in this research. The pulling period (two days) is a parameter that can be changed by users. As discussed in Part B in Section III, by using the pulling demand, the production demand might be loosened; however, the scheduling flexibility increases in the MIP model. Consequently, throughput might be also increased by reducing setup times of toolsets. In Table IV, the rolling demand for layer 4 is, and the pulling demand is (layer 3 s demand for 1.5 days) (layer 2 s demand for 0.5 days). The UPQ for each layer is rolling demand plus pulling demand minus the sum of WIP from its next layer to the last layers: where is the pulling demand of product i, layer j. In Table IV,. D. Determination of TPQ: MIP Model Here, we first introduce a few indices for the TAWB (tool available WIP balancing) procedure. 1) TAWB Measure: For the WIP balancing, we first define WPT (WIP per toolset) for a layer as its average WIP per toolset that can process the layer. In formula (4),, WIP of product i, layer j at the end of a shift, is a decision variable of the MIP model. : WIP Level of Product, Layer Per Toolset: (3) (4) In Table III,. Now, the Toolset Available WIP Balancing is measured by the deviation of TAW of each toolset from the average TAW of all toolsets, i.e.,, where AAW is defined by (6). : Average Available WIP for all Litho Toolsets: The above indices are used in the MIP model in the next section. 2) MIP Objective Function: The objective function has two parts: one for the difference between the UPQ and scheduled quantity (for the throughput maximization of the current shift), and the other,, for WIP balancing at the end of the current shift (to ensure the high throughput of the following shifts). For higher fab-out volume (actual production quantity), more weight is given to the last layer of a product (i.e.,, and if ). In (7), is the relative weight of WIP balancing, which will be determined empirically reflecting the detailed conditions of each problem (see Part C in Section IV). The objective function of the MIP model is (7) 3) MIP Constraints: Production quantity constraint. Production quantity cannot exceed the available WIP: Toolset setup index. If there is production during a scheduled shift (i.e., ), then ; otherwise, : where is a large number. Toolset time constraint. The sum of production time and setup time cannot exceed the production capacity of a toolset. Here is the time bucket (e.g., 8 h): (6) (8) (9) (10) Balance equation for WIP. The WIP at the end of the shift is the WIP at the beginning of the shift plus assigned quantity of the previous layer minus the assigned quantity at the

386 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009 current shift. Also, the WIP of the 1st layer at the beginning of a shift is the same as the release quantity of the layer: of a toolset divided by the batch size. is the capacity of toolset for the shift. (18) (11) where is the newly released quantity of product [12], [16]. UPQ constraint. Production quantity of a layer cannot exceed its UPQ: (12) Mask constraint. The number of assigned toolsets to a layer cannot exceed the number of masks for the layer: (13) 2) Small WIP assignment. A layer whose WIP is less than one lot is not assigned to any toolset: if (19) 3) Large WIP assignment. A layer that has two times higher WIP than a toolset capacity is assigned to at least one toolset. This assignment happens in most cases even without bounding; however, this constraint reduces the computation time: if (20) Lateness constraint. If lateness of a layer is larger than two days (can vary depending on a site), at least one toolset is assigned to the layer: if and (14) where is batch size (e.g., number of wafers in a carrier) determined externally. Toolset dedication constraint. If a toolset cannot process a layer of a product, the binary variable of the assignment is set at zero: when (15) Current processing layer constraint. If a toolset is already processing a lot at the end of the last shift, it continues to process the lot at the beginning of the next shift; the corresponding assignment variable is set to unity: Restrictions on variables: E. Adding Bounds and (16) (17) To reduce its computation time, this MIP model bounds the range of variables. 1) The number of scheduled layers. The number of layers for a toolset to process during a shift cannot exceed the capacity Assumptions and Discussions of the Proposed MIP Model 1) One simplification assumption of the model is that the entire WIP is available at the beginning of each shift, which can give slightly higher TPQ than the true optimum. This discrepancy can be adjusted by the detailed scheduling modules explained in Section I. 2) If a toolset is already broken down or scheduled to be down, this can be reflected in constraint (10). Unscheduled toolset downtime can also be reflected in the constraint based on historical data if needed. 3) The model assumes that the same types of layers are processed together without setups between them. However, the number of actual setups cannot be known in advance because the lot processing sequence is determined by the lot dispatching system after WIP balancing. Based on estimation, the adjustment of the setup time can be made in the model by changing the term in constraint (10) to, where reflects the estimated number of additional setups. 4) Constraint (13) says that the number of assigned toolsets to a layer cannot exceed the number of masks for the layer during a shift. Although a mask can be used for multiple litho toolsets during one shift, when a toolset uses a new mask, it usually needs a test, which takes much time. If a layer is relatively easy to process or when a mask was used by the new toolset recently (e.g., within two to three hours), the test can be skipped. If it is desired for a layer not to have this constraint, the (13) for this layer can be removed from the model. 5) is used in constraint (18) to reduce the computation time. Equation (18) does not affect the model solution. If it is not convenient to calculate this average value, the minimum of over all and can be used for conservatively.

CHUNG AND JANG: A WIP BALANCING PROCEDURE FOR THROUGHPUT MAXIMIZATION IN SEMICONDUCTOR FABRICATION 387 TABLE V TOOLSET FLEXIBILITY AND PART MIX (NUMBER OF AVAILABLE LITHO TOOL SETS/LAYER) 6) While the performance test in the next section assumes four product types, some fabs in practice produce more than four product types at a specific scheduling period; however, the problem size is not increased much by this because, as the number of product types increases, the production quantity per product type decreases due to the capacity of the fab. A product type with less production quantity has fewer available toolsets; therefore, based on constraint (15), the number of non-constrained integer variables in this MIP model remains at a similar level. IV. PERFORMANCE TEST A. Test Case In this section, we compare the TAWB method and other two ones, the TBH (two boundary and heuristic) method [17] and the TBMIP (two boundary and MIP) method [29] for fab scheduling. These two methods use hierarchical approaches for WIP balancing and toolset assignment. These two methods also use the same WIP balancing algorithm, the TB algorithm. For the toolset assignment, the TBH method uses a heuristic algorithm while TBMIP uses an MIP model. The test case is a fab having 35 K WSPM (wafer starts per month), four product types, and 25 layers for each product type. There are 50 litho toolsets with two types of wafer processing time (25 toolsets with 140 s, and another 25 toolsets with 150 s). One test case runs for 21 shifts (7 days), and the scheduling result of a shift is used as input for the next shift. A production quantity in a shift is regarded as an actual production quantity in the next shift after a disturbance rate is multiplied. The disturbance rate, which is from a uniform distribution between 0.73 and 1.21, reflecting real production, makes actual production quantity be smaller or larger than a scheduled quantity. (Note that this value can be larger than one.) The test results are the same as a 3% less production quantities than scheduled quantities. (The test using other distributions such as a triangular distribution give similar test results.) The test also considers the different toolset flexibility and WIP levels, which are shown in Table V. Each layer can be processed by a specific set of tools (dedication). In the table, product type A has higher flexibility on average than the others because of its larger target production volume given by the fab planning system shown in Fig. 1. The test uses three WIP levels, low, medium, and high, which have 1200, 1800, 2400 wafers/per layer, respectively. Fig. 4 shows a simplified WIP modeling. A layer consists of three consecutive WIP stages: W1, W2, and W3. All WIP in the first and second stages (W1 and W2) move to the next stages during a shift. The amount of WIP in W3, which wait for litho machines, is multiplied by the disturbance rate and becomes the first WIP of the next layer at the next shift. The same number of wafers as the fab-out volume at the previous shift is newly released to the fab at the current shift as the WIP of the first layer for each product. This test realistically assumes 10 min of setup time for litho toolsets. The weight value of the objective function of the TAWB model, in (7), is set to 0.01 (more explanation on value is given in Part C in Section IV).

388 IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 22, NO. 3, AUGUST 2009 Fig. 4. WIP flows in test model. Fig. 6. Average throughput rate of different scheduling methods under different WIP levels. Fig. 5. Average throughput rates of different scheduling methods under different flexibility levels. CPLEX is used to solve the TAWB and TBMIP models. The parameters in the solver such as EpGap and ObjDif for relative optimality tolerance [38], and TiLim are carefully tuned for the computation time. The maximum solution time of TAWB and the other MIP models is limited to 15 min, which was determined after referencing a few semiconductor companies. If an optimal solution is not found within 15 min, the best solution until that time is used. B. Performance Comparison The performance criteria are throughput rate and the lateness of wafers. 1) Throughput: Fig. 5 compares throughput (number of wafers produced by litho toolsets in a shift) of three methods at three different flexibility levels given in Table V and at the medium WIP level. The largest throughput is observed from the TAWB method, and the throughput difference between methods is larger as the flexibility decreases. At a high flexibility level, the throughput difference between the TAWB and TBMIP methods is 28 wafers per shift, which increases to 218 and 403 wafers under medium and low flexibility level, respectively. The change of throughput of each method is larger between medium and low flexibility levels than between high and medium flexibility levels, even though the difference of the number of available toolsets per layer between high and medium flexibility cases is larger than that between medium and low flexibility cases. (In Table V, the average numbers of available toolsets per layer are,, and for low, medium and high flexibility cases.) It is worth noting that the flexibility of litho toolsets will get lower with the recent nano-process technology because of the tighter process control. Fig. 6 shows throughput at different WIP levels under the medium flexibility level. Again, the throughput of the TAWB method is the highest; in particular, when the WIP level is low, the difference is larger. At the high WIP level, the average throughput difference between the TAWB and TBMIP methods is 334 and increases to 1,531 wafers per shift under the low WIP level. The sum of the average assigned quantities of the TAWB method for 21 shifts is 9876 wafers at the medium WIP and flexibility levels, while it is 9448 for the TBH, and 9659 for the TBMIP. Since the capacity of litho toolsets is 9950 wafers per shift, the TAWB case corresponds to about 0.7% of throughput loss from setup and starvation time. Among the 0.7%, about 0.3% is used for setup, and 0.4% for idle time. The utilization in case of the TAWB method is about 4% higher than the TBH method and 2% higher than the TBMIP method, which is very significant in practice. 2) Late Quantity: We define the average late quantity as the quantity for 21 test shifts being delayed for more than two days. Fig. 7 shows the average late quantity for different methods at different flexibility levels and at the medium WIP level. The late quantity of the TBH method is much higher than that of the other two methods, implying that the TBH method cannot meet the required target production volume. The late quantity of the TBMIP method is slightly lower than that of the TAWB method. The average late quantity of the TAWB method is 1211 wafers, which is about 3.4% of total WIP (about 36 000 wafers) and higher than that of the TBMIP method by about 1.7%; however, it is still low enough when we consider uncertainty in the target production volume from planning and the characteristics of the semiconductor production explained in Section I. Note that the due date is set internally by the back-end, and the increase of the late quantity from medium flexibility to low flexibility of TAWB is much smaller than that of TBMIP. C. Determination of Weights We tested different G values in (7) to determine the best weight under various flexibility and WIP levels. Fig. 8 shows changes of average throughput for 21 shifts with different G values. High throughput is observed when G is between 0.005 and 0.05 in most cases, the best at 0.01. When the G value

CHUNG AND JANG: A WIP BALANCING PROCEDURE FOR THROUGHPUT MAXIMIZATION IN SEMICONDUCTOR FABRICATION 389 Fig. 7. Average late quantity of different scheduling methods under different flexibility levels. (TAWB) and relaxes the requirement from planning by using the UPQ (upper-limit production quantity). Although the TAWB method considers only the bottleneck stage, scheduling of other stages such as diffusion, implantation, deposition, and etching can be determined by targeting meeting the litho stage schedules. The target production quantity calculated in this research can guide detailed scheduling in the scheduling system shown in Fig. 1. In the future research, authors are interested in developing a more detailed MIP model with precedence constraints of wafer batches. This model will require longer computation time. However, practical bounding constraints from semiconductor production can substantially reduce the computational time as observed in the current research. Combining these bounding constraints with MIP-based heuristics [39] would be explored in future study. ACKNOWLEDGMENT The authors would like to express sincere appreciation to Dr. J. M. A. Tanchoco at the Department of Industrial Engineering, Purdue University, West Lafayette, IN, for his advice on this work. He helped the authors present this work better. Fig. 8. Weight value test. gets larger than 0.05, the throughput decreases because toolsets sometimes do not produce wafers to maintain good WIP balancing. G was set to 0.01 in the performance test. This value is expected to be good for most full size fabs, for example the fabs with 35 WSPM and 50 litho toolsets; however, a simulation study is recommended reflecting actual fab conditions for the determination of the best G value. D. Computational Issues The MIP model of the TAWB method has 5000 binary integer variables, and the sparseness is about 0.0001206 under medium flexibility and WIP levels. The effect of the bounding constraints in the TAWB model on computation time and optimality gap is examined. Here, gap is defined as (best integer best LP node)/best integer [38]. Without bounding constraints, the average gap for 21 shifts is 0.23%, and the average computation time is 6.97 min. The average gap decreases to 0.18% and average computation time to 4.52 min with constraints. Optimal solutions are often found (about a 20% was solved optimally and 50% was solved within a 2% gap) before the 15-min limit with bounding. Stronger bounding would be possible considering specifics of each fab. V. CONCLUSION Semiconductor fab scheduling has been regarded as one of the most difficult problems in production systems control. Fab scheduling begins with information from the planning system. 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Jaewoo Chung received the B.S. degree from Sungkyunkwan University, Korea, in 1995, the M.S. degree from the University of Wisconsin-Milwaukee in 2004, and the Ph.D. degree from Purdue University, West Lafayette, IN, in 2008, all in industrial engineering. He worked for LCD/Semiconductor division at Samsung Electronics for eight years on production scheduling and dispatching, automated material handling, and design and simulation of fab layouts. He is currently an Assistant Professor of Operational Management in the School of Business Administration at Kyungpook National University, Daegu, Korea. His areas of interests are the semiconductor/lcd/solar cell manufacturing systems, logistics planning, material handling automation and facilities layout, and combinatorial optimization. Jaejin Jang received the B.S. degree in industrial engineering from Seoul National University, Seoul, Korea, in 1984, the M.S. degrees in industrial engineering and operations research from Seoul National University, in 1986 and the University of California, Berkeley, in 1989, and the Ph.D. degree in industrial engineering from Purdue University, West Lafayette, IN, in 1993. He worked for Samsung Electronics and Hankuk University of Foreign Studies from 1994 to 2001. From 2001 to 2002, he was a visiting professor and researcher at Purdue University. Since 2003, he has been an Associate Professor in Industrial Engineering Department at the University of Wisconsin, Milwaukee. His areas of interest include scheduling and real-time resource management.