Manufacturer Part Number description Module 2: CMOS FEOL Analysis
Manufacturer Device # 2 Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. 2010 Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any yportion of the reproduced information. Report Code: IPR-XXXX-XXX.1 LOA# Revision XX Published: XX
Manufacturer Device # 3 Table of Contents (all CMOS Modules) Module 1: CMOS Overview Analysis Package photographs Package X-rays Determination of technology node based on SEM cross section Module 2: CMOS FEOL Analysis SEM and TEM analysis of isolation, MOS transistors and PMD Selected Materials analysis results Selected Materials analysis results Critical dimensions Module 3:CMOS BEOL Analysis SEM and TEM cross-sectional analysis of dielectrics, metals and vias. Materials analysis results for metals and dielectrics Critical dimensions Module 4:CMOS SRAM Analysis Plan-view analysis of minimum SRAM cell Cross-sectional SEM and TEM analysis of SRAM cell
Manufacturer Device # 4 Summary Slide Introduction Device Identification Process Summary Observed Critical Dimensions FEOL Analysis PMD TEM Contact Bottom and Silicide TEM NMOS and PMOS SEM Silicon Etch MOS Transistor TEM Contacted MOS Gates MOS Gate Detail MOS Gate Wrap MOS Gate Wrap Detail Gate Dielectric STI Depth Minimum Width STI Statement of Measurement Uncertainty and Scope Variation
Manufacturer Device # 5 Introduction The 45 nm XXXXXXXX was extracted from a XXXXXXX. [1] reference
Manufacturer Device # 6 Device Identification Manufacturer XXXXXXXXXX Foundry XXXXXXXXXX Part number XXXXXXXXXX Type XXXXXXXXXX Date code XXXXXXXXXX Package markings Package type XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX BGA Package dimensions XX.X mm x XX.X mm x X.X mm thick Die markings XXXXXXXXXX Die size (die edge seal) 8.42 mm x 8.14 mm (65.5 mm2)
Manufacturer Device # 7 Process Summary Process type CMOS Number of metal layers 9 Minimum MOS transistor gate length 32 nm Process generation 45 nm Feature measured to determine process generation Contacted gate pitch and MOS gate length
Manufacturer Device # 8 Observed Critical Dimensions Width (µm) Space (µm) Pitch (µm) Thickness (µm) Metal 1 0.09 0.05 0.14 0.13 Contacted Gates 0.18 Minimum MOS Gate Length 32 nm 0.11 Minimum STI 0.10 0.32
Manufacturer Device # 9 FEOL Analysis TEM and SEM cross-sectional analysis of metal 1, PMD, transistors and STI is included.
Manufacturer Device # 10 PMD TEM PMD 5 SiOC PMD 4 oxide M1 Cu PMD 3 oxide PMD 2 oxide 0.44 µm W contact PMD 1 - SiON poly gate NiSi NiSi
Manufacturer Device # 11 Contact Bottom and Silicide TEM W contact TiN liner ~5 nm ~12 nm NiSi ~8 nm Si substrate Contact bottom
Manufacturer Device # 12 NMOS and PMOS SEM Silicon Etch NMOS PMOS
Manufacturer Device # 13 MOS Transistor TEM NiSi buffer oxide silicon nitride SWS polysilicon 32 nm NMOS and PMOS have the same physical structure
Manufacturer Device # 14 Contacted MOS Gates NiSi 30 nm 50 nm 190 nm 24 nm 40 nm 32 nm notch NiSi 29 nm 36 nm 33 nm
Manufacturer Device # 15 MOS Gate Detail NiSi buffer oxide 13 nm SiON CESL W contact 27 nm polysilicon ONO gate dielectric silicon nitride SWS 7 nm 22 nm 38 nm NiSi Si substrate
Manufacturer Device # 16 MOS Gate Wrap 16 nm NiSi 108 nm polysilicon 11 nm Si substrate STI
Manufacturer Device # 17 MOS Gate Wrap Detail polysilicon gate dielectric 13 nm Si substrate STI
Manufacturer Device # 18 Gate Dielectric polysilicon O N O 2.0 nm Si 2.0 nm ONO gate dielectric
Manufacturer Device # 19 STI Depth
Manufacturer Device # 20 Minimum Width STI W contact poly 0.11 µm 0.32 µm
Manufacturer Device # 21 Statement of Measurement Uncertainty and Scope Variation Measurement Uncertainty Chipworks calibrates length measurements on its scanning electron microscopes (SEM), transmission electron microscope (TEM), and optical microscopes, using measurement standards that are traceable to the International System of Units (SI). Our SEM/TEM cross-calibration calibration standard was calibrated at the National Physical Laboratory (NPL) in the UK (Report Reference LR0304/E06050342/SEM4/190). This standard has a 146 ± 2 nm (± 1.4%) pitch, as certified by NPL. Chipworks regularly verifies that its SEM and TEM are calibrated to within ± 2% of this standard, over the full magnification ranges used. Fluctuations in the tool performance, coupled with variability in sample preparation, and random errors introduced during analyses of the micrographs, yield an expanded uncertainty of about ± 5%. A stage micrometer, calibrated at the National Research Council of Canada (CNRC) (Report Reference LS-2005-0010), 0010) is used to calibrate Chipworks optical microscopes. This standard has an expanded uncertainty of 0.3 µm for the stage micrometer s 100 µm pitch lines. Random errors, during analyses of optical micrographs, yield an expanded uncertainty of approximately ± 5% to the measurements. The materials analysis reported in Chipworks reports is normally limited to approximate elemental composition, rather than stoichiometry, since calibration of our SEM and TEM based methods is not feasible. Chipworks will typically abbreviate, using only the elemental symbols, rather than full chemical formulae, usually starting with silicon or the metallic element, then in approximate order of decreasing atomic % (when known). Elemental labels on energy dispersive X-ray spectra (EDS) will be colored red for spurious peaks (elements not originally in sample). Elemental labels in blue correspond to interference from adjacent layers. Secondary ion mass spectrometry (SIMS) data may be calibrated for certain dopant elements, provided suitable standards were available. Scope Variation Due to the nature of reverse engineering, there is a possibility of minor content variation in Chipworks standard reports. Chipworks has a defined table of contents for each standard report type. At a minimum, the defined content will be included in the report. However, depending on the nature of the analysis, additional information may be provided in a report as value-added material for our customers.
Manufacturer Device # 22 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at 1-613-829-0414 Chipworks 3685 Richmond Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T 1-613-829-0414 F 1-613-829-0515 Web site: www.chipworks.com com Email: info@chipworks.com Please send any feedback to feedback@chipworks.com