ENG/PHYS3320 Microsystems Technology Chapter 2 Fabrication of Microsystems

ENG/PHYS3320 Microsystems Technology Chapter 2 Fabrication of Microsystems ENG/PHYS3320: R.I. Hornsey Fab: 1

Fabrication Many of the new transducers are based on a technology known as micromachining a significant number of structures are miniaturized versions of well established devices you cannae change the laws of physics, Cap n but the importance of some of the mechanisms can be significantly different at small scales The generic term for these types of devices is MEMS micro-electro-mechanical systems although they may be thermal, optical or magnetic, and not really mechanical, the term is still used Micromachining is a misleading term used to describe a specialised form of chemical etching, that results in mechanical isolation ENG/PHYS3320: R.I. Hornsey Fab: 2

As we discussed in the introduction, the options for our design are limited by compatibility with the CMOS fabrication process what we get as part of the CMOS and what we can do afterwards without damaging the CMOS A review of the basic CMOS process can be found in books such as Microelectronic Circuits, by Sedra and Smith we will do a really quick overview here ENG/PHYS3320: R.I. Hornsey Fab: 3

CMOS technology Complementary Metal-Oxide-Semiconductor complementary = two opposite types; one conducts with electrons and one with holes one controlled by making gate = logical 1, other by making gate = logical 0 major advantages is that when both devices are used, current does not flow continuously, so they are low power By far the majority of chips are made in CMOS technology process characterised my minimum gate length, e.g. 0.18µm ENG/PHYS3320: R.I. Hornsey Fab: 4

http://courses.nus.edu.sg/course/p hyweets/projects99/01tech1a.gif (opriginally from Semiconductor International, I think) ENG/PHYS3320: R.I. Hornsey Fab: 5

Cross section through a simple CMOS inverter http://www.ami.ac.uk/course ware/comms/ch2/image6.gif IBM s damascene process ENG/PHYS3320: R.I. Hornsey Fab: 6

In a standard CMOS process, we get several materials that can be used for micromachining silicon substrate (with a variety of doping levels) silicon dioxide either thin (~5nm) or thick (~1µm) layers polycrystalline silicon (~1µm) aluminum several layers of various thicknesses possibly other materials, such as silicon nitride and, more recently, copper ENG/PHYS3320: R.I. Hornsey Fab: 7

If, for example, we want to make a free-standing cantilever beam, we have two basic choices, bulk and surface micromachining thin film removed sacrificial layer etched pit substrate substrate surface micromachining does not involve the substrate whereas bulk micromaching usually removes large portions of the substrate each technique is useful in different circumstances ENG/PHYS3320: R.I. Hornsey Fab: 8

When making these structures, a key parameter is the aspect ratio the ratio of the depth/height to the width of a structure generally a high aspect ratio structure is much harder to fabricate high aspect ratios low aspect ratios Clearly, the etching of a high aspect ratio hole requires specialised etchant http://hbksun17.fzk.de:8080/fzk/blick/englisch/micro.html ENG/PHYS3320: R.I. Hornsey Fab: 9

Etchants can be categorized as, isotropic etchants progress with almost equal rates in all directions and tend to give rounded corners anisotropic etchants favour a particular direction and hence give well-defined structures They can also be divided in to wet and dry etchants wet etching is performed using liquid chemicals dry etching uses physical processes, sometimes with the assistance of gaseous chemical processes There are a myriad of individual techniques, the choice of which depends on numerous factors and we will look at just the most common ones ENG/PHYS3320: R.I. Hornsey Fab: 10

Isotropic wet etch A simple and commonly used wet isotropic etch is known as HNA : a mixture of hydrofluoric acid (HF), nitric acid (HNO3), and Acetic acid As with many etchants, the idea is to oxidise the substrate and then to etch away the oxide the HNO 3 does the oxidation, the HF etches the oxide and the acetic acid is used to prevent dissociation of the HNO 3. The main problem with this is that the HF also attacks regular SiO 2, which must therefore be protected ENG/PHYS3320: R.I. Hornsey Fab: 11

Etching is essentially an electro-chemical process involving the exchange of charge between the etchant and the substrate so the rate of etching depends on the doping of the semiconductor, which can be useful to control the depth of the etch and the etch rate can be modified by a voltage In practical structures, the etching rate is governed by the diffusion of fresh chemicals and agitation of the sample during etching evens out the etch rate No agitation With agitation ENG/PHYS3320: R.I. Hornsey Fab: 12

Anisotropic wet etching Anisotropic chemical etchants rely on the differences in bonding and atomic densities between the various crystal planes most chemicals tend to stop on the (111) planes the selectivity to direction should be >100:1 an example is shown for two wafer orientations 54.7 (111) (100) surface direction (111) (110) surface direction ENG/PHYS3320: R.I. Hornsey Fab: 13

CMOS electronics is usually made on the (100) material, so micromachining of integrated systems behaves like the left picture above Another feature of these etchants is that they undercut convex and concave corners differently concave top view section convex corners are undercut more rapidly ENG/PHYS3320: R.I. Hornsey Fab: 14

This is useful since it allows a free-standing cantilever to be fabricated the following diagram shows a cross section through the dotted line above as a function of time 1. 2. Etching is still something of an art while the general behaviours are known, the rates, concentrations etc. usually need to be determined experimentally 3. ENG/PHYS3320: R.I. Hornsey Fab: 15

http://www-mat.ee.tu-berlin.de/research/koh_etch/koh_etch.htm Three main anisotropic wet etches are commonly used: potassium hydroxide (KOH) trymethyl ammonium hydroxide (TMAH) ethylene diamine pyrochatechol (EDP) ENG/PHYS3320: R.I. Hornsey Fab: 16

KOH (100) plane etched at typically 1µm per minute (100) plane is etched 400 times faster than the (111) plane this allows very long etches, enough to do back thinning of silicon wafers Etching slows down in boron (p-) doped regions ~10 19 cm -3 level Etching of SiO 2 is typically 1nm/min. A potential disadvantage to KOH is the K, which can contaminate the CMOS process so sometimes ammonium hydroxide is used instead but the etch rate is lower and ammonia is given off ENG/PHYS3320: R.I. Hornsey Fab: 17

TMAH TMAH is currently the most popular etchant for use on CMOS substrates it is cheap, controllable, does not etch aluminum or SiO2, and is less toxic than the alternatives A disadvantage is that the directional selectivity is only about 20 hence, TMAH is only suitable for relatively shallow structures Again, the etch slows for p + regions with a doping of ~10 20 cm -3 ENG/PHYS3320: R.I. Hornsey Fab: 18

EDP Formerly popular anisotropic etch with a selectivity to direction of about 40:1 It is less used for integrated systems because it is very carcinogenic it can attack aluminum conductors is corrosive to equipment ENG/PHYS3320: R.I. Hornsey Fab: 19

Etch-stop layers The depth of an etched hole can be controlled by timing an etch with a calibrated etch rate this raises a trade-off between speed and controllability An etch-stop is used to artificially stop the etch at a known depth this is usually accomplished with a p + layer e.g. to create a silicon membrane for a pressure sensor However, this approach will not necessarily be useful for standard CMOS processes A more suitable method uses a biased p-n junction to achieve the same ends Si membrane SiO 2 mask p + layer bulk silicon ENG/PHYS3320: R.I. Hornsey Fab: 20

Diode junction etch stop As mentioned above, the etch rate can be controlled by an applied voltage a positive surface promotes the formation of an SiO 2 layer on contact with the etch, and therefore turns off the etching So if we have a p-n diode with a reverse bias electrode solution p n - + the p-region etches away until the positively biased n-type is exposed, at which point the oxide forms and the etch self-terminates electrode solution - + SiO 2 n ENG/PHYS3320: R.I. Hornsey Fab: 21

Dry etching While wet etching has many advantages chemical cost, equipment cost, speed it can be hard to control and relatively inflexible There is also a limit on the achievable aspect ratio especially for (100) CMOS because the anisotropy results from the crystal planes vertical walls are not possible. Dry etching is a class of etching that does not rely on wet chemicals but on ion bombardment to sputter away a surface ENG/PHYS3320: R.I. Hornsey Fab: 22

The ions are generated in a plasma: which is an ionised gas (a mixture of electrons and ions), generated by a radiofrequency electric field similar to a fluorescent light plasma AC wafer http://info.web.cern.ch/info/scitech/toptech/03/chip/chip2.shtml http://www.physics.dcu.ie/~jpm/seminars/seminars00_01/etchprofile.jpg ENG/PHYS3320: R.I. Hornsey Fab: 23

Between the plasma and the wafer is a region where the electric field is perpendicular to the wafer and which accelerates the positive ions from the plasma towards the wafer The impact of the ions removes the wafer material at a rate which depends on: plasma power plasma ion species target material A purely physical etching tends to give more vertical edges but the etch rate will likely be low this is sometimes used just to clean surfaces ENG/PHYS3320: R.I. Hornsey Fab: 24

While such plasma etching can be a purely physical process, with the appropriate compositions it can also involve chemistry chemical reactions which would otherwise require very high temperatures (>1000 C) can take place at <300 C because energy is provided by the plasma [a similar plasma process, called plasma enhanced chemical vapour deposition, can be used to deposit materials such as amorphous silicon at low temperatures] The resulting degree of anisotropy depends on the ratio of the physical and chemical processes This techniques is known as reactive ion etching RIE ENG/PHYS3320: R.I. Hornsey Fab: 25

If the radicals freed in the plasma chemically etch the substrate without the need for ion bomdardment the etching will be isotropic e.g. SF 6 Adding in FREON115 (CClF 5 ) to the SF6 allows control of the lateral etching on the side walls, a protective polymer of fluorine-rich fluorocarbon is deposited which inhibits lateral etching on the bottom, the polymer is both thin and carbon-rich and etches rapidly (>250nm/min) hence a high degree of anisotropy is achieved As with the wet etching, the local availability of the reactants will affect the profile of the hole ENG/PHYS3320: R.I. Hornsey Fab: 26

The RIE machine is similar to the plasma etcher, with some modifications to increase ion energy (lower pressure operation) and uniformity (making the relative area of the wafer smaller): plasma wafer AC Because of the primarily chemical nature of RIE, good material selectivity can achieved to avoid etching dielectrics or metallization ENG/PHYS3320: R.I. Hornsey Fab: 27

While basic RIE can achieve a reasonable anisotropy, it is not good enough for aspect ratios much bigger than 10:1 Enter Deep Reactive Ion Etching DRIE ENG/PHYS3320: R.I. Hornsey Fab: 28

DRIE In order to enhance the anisotropy (and hence the maximum depth of hole), the polymerisation process described above can be enhanced deliberately, by alternating an etching step (e.g. SF 6 /Ar) with a polymerisation step (e.g. SF 6 /C 4 F 4 ) the polymer is effectively teflon (~50nm), and naturally coats both vertical and horizontal surfaces however, adding ion bombardment during polymerisation almost prevents the teflon formation at the bottom of the hole Holes up to 1mm deep, with a 30:1 aspect ratio and an etch rate of 2µm/minute can be achieved with >100:1 selectivity over SiO 2 ENG/PHYS3320: R.I. Hornsey Fab: 29

Numerous other etching recipes are available ß such recipes are frequently the source of competitive advantage for equipment vendors in this field http://www.ccmicro.rl.ac.uk/bulk.html ENG/PHYS3320: R.I. Hornsey Fab: 30

Lithography Both wet and dry etching techniques are immersive (as opposed to direct write ) and hence rely on a patterned masking layer to protect some areas of the substrate from undesired etching Patterning is transferred to the mask layer by a process called photolithography photo = light, litho = stone, graphy = writing In practice, this is achieved by exposing a lightsensitive chemical (the photoresist) to ultra-violet light, through an optical mask the optical mask is typically formed by a set of photographic reductions from a 100x master pattern and is usually chromium on quartz ENG/PHYS3320: R.I. Hornsey Fab: 31

UV light quartz chromium photoresist removed after developing photoresist photoresist substrate substrate http://britneyspears.ac/physics/fabrication/image46.jpg ENG/PHYS3320: R.I. Hornsey Fab: 32

The material for the masking layer on the chip must be selected so that it is not attacked by the etchant. Typically there are two choices the photoresist itself (an organic polymer) or another layer present (SiO2, Al) that is patterned from the photoresist by another etching stage. Straightforward lithography requires that the wavelength of the illumination must be smaller than the feature size of the pattern which is 0.13µm 0.09µm in 2003 so deep UV light is used, causing challenges in optics, resist technology etc. ENG/PHYS3320: R.I. Hornsey Fab: 33

http://www.agc.co.jp/english/rd_e/e_semicon2.html ENG/PHYS3320: R.I. Hornsey Fab: 34

The other key ingredient for lithography is alignment of a new layer pattern to previous layers this is achieved with registration marks on the periphery of the devices, much like commercial colour printing a CMOS chip consists of 15 20 layers, each of which must be aligned to typically 1/10 of the minimum feature size this is usually performed automatically in commercial fabrication plants ENG/PHYS3320: R.I. Hornsey Fab: 35

Stepper The patterns are then moved across the silicon wafer by the stepper one of the most expensive items in the clean room http://www.ptb.de/en/org/5/52/522/maske_e.htm http://www.cms.kyutech.ac.jp/photos/stepper.jpg ENG/PHYS3320: R.I. Hornsey Fab: 36

Deposition Surface micromachining requires prior deposition of layers, which can then be selectively etched i.e. additive processes Layer structures needed for MEMS are not usually available in the standard CMOS process and must therefore be deposited subsequently, in a compatible post-processing stage materials used in MEMS are still counted as thin films, even though they may be 10 100 times thicker than those in CMOS ENG/PHYS3320: R.I. Hornsey Fab: 37

Compatible means that: deposition temperature is low (<350 C because of Al metallization) low stress/strain in films (to avoid distortion) good coverage of steps good uniformity and integrity good properties for micromachining Two broad categories: Non-metallic thin film deposition such as SiO 2, poly-si, silicon nitrides (Si x N y ) Metallic thin film deposition Al, Au, Cu ENG/PHYS3320: R.I. Hornsey Fab: 38

Silicon dioxide SiO 2 can be obtained (grown or deposited) in several ways: thermal growth from Si deposited (see below) phosphorus-doped = phosphosilicate glass (PSG), used as final coating on chips boron-doped = borosilicate glass (BSG) both P- and B-doped = BPSG, or low-temperature oxide (LTO) LTO is useful because it flows well at low temperatures, and smooths out the underlying surface (called planarization) ENG/PHYS3320: R.I. Hornsey Fab: 39

Thermal SiO 2 growth: Si + O 2 Æ SiO 2 (dry oxidation) Si + 2H 2 O Æ SiO 2 + 2H 2 (wet oxidation) good quality, but requires Si substrate to start with Chemical vapour deposition (CVD): silane + oxygen: SiH 4 + O 2 Æ SiO 2 + 2H 2 dichlorosilane + nitrous oxide: SiCl 2 H 2 + 2N 2 O Æ SiO 2 + 2N 2 + 2HCl ENG/PHYS3320: R.I. Hornsey Fab: 40

Kovacs, p.79 ENG/PHYS3320: R.I. Hornsey Fab: 41

induction heater gas mixture wafers in carrier Chemical Vapour Deposition quartz tube http://www.pha.jhu.edu/~efelton/manufacturing.html ENG/PHYS3320: R.I. Hornsey Fab: 42

Both the thermal growth and the CVD above require high temperatures (~1000 C) to achieve decomposition of the appropriate materials these are therefore not CMOS-compatible Plasma-enhanced CVD (PECVD) is more commonly used, because: low temperature control of stress is possible by adjusting plasma conditions similar to the plasma etcher, but conditions are chosen to promote deposition over etching ENG/PHYS3320: R.I. Hornsey Fab: 43

Silicon Nitride SiN has many useful properties for MEMS: structural material passivation (protective) layer mask for etching/oxidation of Si dielectric material It also has a different dielectric constant from SiO 2 which gives it useful optical properties anti-reflective coating, waveguide The normal (stoichiometric) composition of silicon nitride is Si 3 N 4 but other stoichiometries can be used (i.e. silicon-rich or nitrogen-rich) which have different properties, especially with regard to stress. ENG/PHYS3320: R.I. Hornsey Fab: 44

A common CVD reaction for SiN is 3SiH 4 + 4NH 3 Æ Si 3 N 4 + 12H 2 Or, for PECVD: SiH 4 + NH 3 Æ SiNH + 3H 2 In the PECVD case, the presence of the hydrogen affects the stoichiometry. This in turn is affected by the plasma power and frequency which in turn affects the stress e.g. 13.56MHz Æ 400MPa tensile stress while 50kHz Æ 200MPa compressive stress [atmospheric pressure is 0.1MPa] ENG/PHYS3320: R.I. Hornsey Fab: 45

Polysilicon The main use of poly in MEMS is as a structural material In CMOS it forms the gates of MOSFETs and short interconnects and is deposited at high (600 C) using CVD Poly can also be deposited using PECVD (doped or undoped), where the temperature determines the morphology of the film: T>~350 C Æ poly T 250 C Æ amorphous ENG/PHYS3320: R.I. Hornsey Fab: 46

Deposition of metallic thin films Metallic films for ICs and micromachining are deposited primarily in four ways evaporation either resistive heating or electron beam sputtering electrodeposition The choice of technique depends on the metal, the deposition rate and the morphology required ENG/PHYS3320: R.I. Hornsey Fab: 47

Thermal evaporation hermal evaporation is the workhorse of deposition processes because it is simple, cheap, and reasonable quality Deposition by evaporation is simply an evaporation/condensation process the metal is heated until it evaporates the neutral atomic flux is then condensed onto the cooler substrate sometimes the metal to be deposited is wound around a heater filament (if a higher temperature is needed) ENG/PHYS3320: R.I. Hornsey Fab: 48

wafer low vacuum evaporated atoms heating current (~50A) tungsten boat molten metal http://www.astro.cf.ac.uk/groups/optoelec/pictures/edwards2.jpg ENG/PHYS3320: R.I. Hornsey Fab: 49

Resistive heating is limited by the temperature to which the boat/filament can be heated (~1400 C for W) so it is good for Al, Au, Mg, Cr Evaporation may not be good for depositing alloys because the various constituents may not evaporate at the same rate, and the deposited film may have a different composition than the original metal Film uniformity depends on the ratio of the wafer size to the boat-wafer separation increasing the separation to cope with larger wafers also requires higher vacuum to give the metal atoms a higher mean free path ENG/PHYS3320: R.I. Hornsey Fab: 50

The nature of the deposited film depends on the temperature of the substrate the temperature determines the mobility of the adsorbed atoms on the surface the more rearrangement they are allowed, the more like epitaxy the process becomes, and the less stress there is in the film in general, the nearer the substrate temperature to the melting point of the deposited metal, the lower the stress so lower melting point metals (Al, Au) have lower stress Deposition rates are typically ~nm/s ENG/PHYS3320: R.I. Hornsey Fab: 51

Electron beam evaporation In order to escape from the heating limitations of resistive heating, the metal can be evaporated by electron beam bombardment 10keV @ 100mA, leading to 1kW/mm 3 density This method both allows other materials (e.g. Ti, Pt, W) to be deposited with a higher rate the source temperature may get to 3000 C if the target wafer can be cooled sufficiently rate ~100nm/s One of the disadvantages of electron beam evaporation is the generation of x-rays indeed, this is how x-rays are normally generated! so appropriate shielding, both of the operator and of the wafer, is required ENG/PHYS3320: R.I. Hornsey Fab: 52

Sputter deposition Sputter deposition is the other very common metal deposition technique and is a cross between plasma etching and evaporation Now, instead of removing atoms from the source metal by evaporation, they are removed by ion bombardment (= sputtering) from a plasma typically the plasma is argon (Ar+) because it causes little contamination Because the metal atoms are actively knocked off, they are more energetic and hence have a higher surface mobility stress control is therefore better, as well as better step coverage ENG/PHYS3320: R.I. Hornsey Fab: 53

Moreover, the sputtering yield of different metals does not vary widely, so alloys are sputtered with the same stoichiometry as the source metal The type of plasma source has an influence, particularly because higher power sources are needed to sputter harder metals DC plasmas are able to sputter soft metals but if we want higher powers or to sputter dielectrics, we need an AC plasma this is to avoid charging of the insulating target typically, RF plasmas at 13.56MHz are used Sputtered metal films tend to be under tensile stress ENG/PHYS3320: R.I. Hornsey Fab: 54

Care must be taken to cool the wafer (it heats due to secondary electrons emitted from the target) and there will be a small amount of residual incorporation of the plasma material in the deposited film ENG/PHYS3320: R.I. Hornsey Fab: 55

Step coverage and shadowing A major difference between evaporation and sputtering is in the directionality of the deposition evaporated atoms move in straight lines to the wafer from the source in sputtering, the source is essentially distributed, especially in RF sputtering hence sputtered films cover side walls of structures almost as well as the surfaces, and step coverage is better (usually good) substrate evaporation substrate RF sputtering ENG/PHYS3320: R.I. Hornsey Fab: 56

The directional nature of evaporation can provide two useful techniques ß lift-off and shadowing metal photoresist as deposited with removal of resist, unwanted metal is lifted off Lift-off is the general name given to a type of patterning http://www.nnf.cornell.edu/spiebook/figures/30.jpg ENG/PHYS3320: R.I. Hornsey Fab: 57

Now, if the film is evaporated at an angle... structure can be smaller than lithographic limit shadow as deposited after lift-off... this is called shadowing because the resist is used to shadow some of the bottom of the hole and can be used as a way of cheating the minimum lithographic limit of your process ENG/PHYS3320: R.I. Hornsey Fab: 58

Electrodeposition Electrodeposition electroplating is appearing in micro-systems for forming very thick (~100µm) metallic layers In some ways, this can be seen as the opposite of etching where charge transfer now causes deposition rather than etching e.g. Cu 2+ + 2e - Æ Cu(solid) Electrodeposition of InSb to form a photonic crystal + e.g. mixture of copper sulphate (CuSO 4 ) and sulphuric acid (H 2 SO 4 ) http://www.phys.cwru.edu/research/index.php?section=optics&what=photonic ENG/PHYS3320: R.I. Hornsey Fab: 59

a conducting template layer is formed first by e.g. evaporation to form the base for the electrodeposition but this template is not usually sufficient to define the whole structure because the electrodeposition does not form vertical edges (see next section) Common materials to be electrodeposited are Au, Ag, Cu, Ni, Pt such processes have been in use for ~100 years and many recipes are well known Gold is deposited from gold cyanide, e.g. Au(CN) 2- AuCN + CN - and AuCN + e - Æ Au(s) + CN- As with anisotropic etching, the deposition rate is dependent on the crystal plane ENG/PHYS3320: R.I. Hornsey Fab: 60

final shape slow-growing surface initial shape fast-growing surface One important factor with all metal deposition techniques is how well the metal sticks to the surface Some metals e.g. nichrome, NiCr, and Ti are well known for being sticky, and thin layers are frequently used to promote adhesion ENG/PHYS3320: R.I. Hornsey Fab: 61

LIGA LIGA a German acronym for lithography, electroplating, and moulding is one of the primary techniques for making high aspect ratio (100:1) MEMS Example of LIGA process from Sandia Labs ENG/PHYS3320: R.I. Hornsey Fab: 62

The aspect ratio is achieved by electroplating through a template the template is a thick layer of patterned resist through which the electrodeposition occurs the thick layer of resist is then removed, leaving verticalsided metallic structures metal resist adhesion layer substrate The problem has now moved from how to do the metallization to how to pattern the resist! ENG/PHYS3320: R.I. Hornsey Fab: 63

In LIGA process, x-rays are used to expose the resist which is typically poly-methyl-methacrylate (PMMA) PMMA is also commonly used as the resist for electron beam lithography it is essentially plexiglass These x-rays are generated from a synchotron, and are well collimated so they impinge on the PMMA almost vertically the confinement of the electroplating to the PMMA pattern is the moulding part of the LIGA acronym ENG/PHYS3320: R.I. Hornsey Fab: 64

from Cronos Integrated Microsystems ENG/PHYS3320: R.I. Hornsey Fab: 65

Sacrificial processes We have mentioned sacrificial processes earlier in the context of the airbag sensor, micromirrors and microbolometers the sacrificial layer is specifically deposited to serve as a scaffold and is later removed to leave the structure freestanding structural layer (e.g. Au, poly, SiO 2 ) sacrificial layer SiO 2 insulator substrate as deposited substrate after separation ENG/PHYS3320: R.I. Hornsey Fab: 66

Sacrificial layers can be resists, phosphosilicate glass (PSG), oxide, nitride the sacrificial layer should etch much faster than the structural layer If the structure to be released has a large area, care must be taken to ensure that the sacrificial layer is exposed adequately to the etchant otherwise the etch time will be so long that the structure may also be damaged this is frequently achieved simply by forming holes in the structure to allow the etchant underneath ENG/PHYS3320: R.I. Hornsey Fab: 67

e.g. Sandia hinged mirror ENG/PHYS3320: R.I. Hornsey Fab: 68

SEM of pneumatic micro gripper prior to release from sacrificial layer http://www.imt.tu-bs.de/mitarbeiter/seidemann/projekte/su8compliant_struc.htm ENG/PHYS3320: R.I. Hornsey Fab: 69

One of the major issues regarding commercial manufacture of devices using sacrificial processes is that of sticking If a wet chemical is used to etch or wash the device, the fluid, when it dries, attracts the surfaces together and once the surfaces are stuck, it is very hard to release them again For hydrophobic (water repelling) materials, it appears that van der Waals forces (attraction of electric dipoles) causes the surfaces to stick mechanical forces surface tension forces ENG/PHYS3320: R.I. Hornsey Fab: 70

For hydrophilic (water attracting) materials, hydrogen bonding (bonding of surface OH groups) is responsible silicon falls into this group The typical technique for avoiding this problem is to avoid the liquid drying phase by first freezing the liquid (e.g. butyl alcohol) then the solid is sublimed (solid goes straight to gas) in a vacuum this is the same process used for freeze drying foods ENG/PHYS3320: R.I. Hornsey Fab: 71

Conclusion This chapter has provided an overview of the basic micromachining, and other, fabrication techniques relevant to a range of microsystems We will come across other fabrication issues as we discuss specific transducers We have discussed subtractive and additive processes, lithography we have not yet talked much about materials properties, but these too are important With these ideas of fabrication in our minds, we can now progress to individual transduction mechanisms, and examples of practical implementations ENG/PHYS3320: R.I. Hornsey Fab: 72