3D FRACTURE MECHANICS ANALYSIS OF UNDERFILL DELAMINATION FOR FLIP CHIP PACKAGES

Similar documents
Journal of Science and Technology The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA)

Packaging Effect on Reliability for Cu/Low k Damascene Structures*

Interfacial Delamination Near Solder Bumps and UBM in Flip-Chip Packages

Accurate Predictions of Flip Chip BGA Warpage

Mechanical Behavior of Flip Chip Packages under Thermal Loading

White Paper. Discussion on Cracking/Separation in Filled Vias. By: Nathan Blattau, PhD

Thermo-Mechanical Reliability of Through-Silicon Vias (TSVs)

Hannah Erika R. Ducusin, Jennifer.J. Fabular, Richard Raymond N. Dimagiba, Manolo G. Mena. A. Model Description

Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications

On the failure path in shear-tested solder joints

Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages

Processor Performance, Packaging and Reliability Utilizing a Phase Change Metallic Alloy Thermal Interface System

Lifetime Prediction and Design Tool Development for Power Electronics Modules

BGA Package Underfilm for Autoplacement. Jan Danvir Tom Klosowiak

CHARACTERISATION OF INTERFACIAL CRACKING IN MICROELECTRONIC PACKAGING

Fundamentals of Sealing and Encapsulation

Effect of Bond Layer Properties to Thermo-Mechanical Stresses in Flip Chip Packaging

IN ELECTRONIC packaging, materials with different coefficients

A Characterization Method for Interfacial Delamination of Copper/Epoxy Mold Compound Specimens Under Mixed Mode I/III Loading

Field Condition Reliability Assessment for SnPb and SnAgCu Solder Joints in Power Cycling Including Mini Cycles

23 rd ASEMEP National Technical Symposium

International Conference on Mechanics and Civil Engineering (ICMCE 2014)

Carbon-fiber Reinforced Concrete with Short Aramid-fiber Interfacial Toughening

Sherlock 4.0 and Printed Circuit Boards

Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design

Reliability Evaluation of CIF (chip-in-flex) and COF (chip-on-flex) packages

THERMAL MECHANICAL FATIGUE OF A 56 I/O PLASTIC QUAD-FLAT NOLEAD (PQFN) PACKAGE

Chip-Packaging Interaction and Reliability Impact on Cu/Low-k Interconnects. Mechanics, University of Texas, Austin, TX 78712

Finite element prediction of curing micro-residual stress distribution in polymeric composites considering hybrid interphase region

curamik CERAMIC SUBSTRATES AMB technology Design Rules Version #04 (09/2015)

Fracture analysis of Thermal Barrier Coating Delamination under Thermal Shock

Low Cycle Fatigue Testing of Ball Grid Array Solder Joints under Mixed-Mode Loading Conditions

The Failure Behavior of Composite Honeycomb Sandwich Structure with. Stringer Reinforcement and Interfacial Debonding

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging

Technical Report Documentation Page 2. Government 3. Recipient s Catalog No.

S/C Packaging Assembly Challenges Using Organic Substrate Technology

Solder joint reliability of plastic ball grid array with solder bumped flip chip

NUMERICAL MODELING OF CYCLIC STRESS-STRAIN BEHAVIOR OF Sn-Pb SOLDER JOINT DURING THERMAL FATIGUE

Study and mechanical characterization of high temperature power electronic packaging

TEMPERATURE CYCLING AND FATIGUE IN ELECTRONICS

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C

Selection and Application of Board Level Underfill Materials

Thermal stress analysis of leads in Quad Flat Package: a parametric study

Flip Chip - Integrated In A Standard SMT Process

AlSiC for Optoelectronic Thermal Management and Packaging Designs

DEVELOPMENT AND EVALUATION OF FRACTURE MECHANICS TEST METHODS FOR SANDWICH COMPOSITES

Reliability in Large Area Solder Joint Assemblies and Effects of Thermal Expansion Mismatch and Die Sizen

CHAPTER 2 Chip-Package Interaction and Reliability Impact on Cu/Low-k Interconnects. Xuefeng Zhang, Se Hyuk Im, Rui Huang, and Paul S.

LEAD-BASED solders have been used to provide electrical

Numerical analysis of TSV/micro-bump deformation due to chip misalignment and thermal processing in 3D IC packages

Recent Advances in Die Attach Film

27th Risø International Symposium on Materials Science, Polymer Composite Materials for Wind Power Turbines, 2006

Study on Effect of Coupling Agents on Underfill Material in Flip Chip Packaging

Qualification and Performance Specification for High Frequency (Microwave) Printed Boards

Micro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation

ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY

Reliability Challenges for 3D Interconnects:

Reliability Assessment of a High Performance Flip-Chip BGA Package (organic substrate based) using Finite Element Analysis

Finite Element Modeling of Heat Transfer and Thermal Stresses for Three-dimensional Packaging of Power Electronics Modules

Molding materials performances experimental study for the 3D interposer scheme

SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

Solder joint reliability of cavity-down plastic ball grid array assemblies

FRACTURE LENGTH SCALES IN DELAMINATION OF COMPOSITE MATERIALS. and M. D. Thouless

DIRECT MEASUREMENT ON FRACTURE TOUGHNESS OF CARBON FIBER ABSTRACT

Plasma for Underfill Process in Flip Chip Packaging

Available online at ScienceDirect. Procedia Engineering 79 (2014 )

ANALYSIS OF STRESS INTENSITY FACTOR OF AL7075 T651 PLATE WITH CRACKED HOLE -A CONSTANT CRACK LENGTH METHOD

NOVEL CRACK STOPPER CONCEPT FOR LIGHTWEIGHT FOAM CORED SANDWICH STRUCTURES EXPERIMENTAL VALIDATION, FE-MODELLING AND POTENTIAL FOR USE IN STRUCTURES

MSE 3143 Ceramic Materials

BUCKLING ANALYSIS OF PULTRUDED GFRP HOLLOW BOX BEAM

Characterization of acoustic emission signals from particulate filled thermoset and thermoplastic. polymeric coatings in four point bend tests

High Reliable Non-Conductive Adhesives for Flip Chip CSP Applications

Subject Index. STP1156-EB/Jun. 1993

Package Design Optimization and Materials Selection for Stack Die BGA Package

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking

Key words: microprocessor integrated heat sink Electronic Packaging Material, Thermal Management, Thermal Conductivity, CTE, Lightweight

Reliability of Interconnects in LED Lighting Assemblies Utilizing Metal Clad Printed Circuit Boards Stefano Sciolè BDM I.M.S.

Fracture. Brittle vs. Ductile Fracture Ductile materials more plastic deformation and energy absorption (toughness) before fracture.

Manufacturing and Reliability Modelling

NUMERICAL ANALYSIS OF BUCKLING AND POST BUCKLING BEHAVIOR OF SINGLE HAT STIFFENED CFRP PANEL

Chip Warpage Damage Model for ACA Film Type Electronic Packages

II. A. Basic Concept of Package.

Passive TCF Compensation in High Q Silicon Micromechanical Resonators

Study on Damage Tolerance Behavior of Integrally Stiffened Panel and Conventional Stiffened Panel

A NOVEL HIGH THERMAL CONDUCTIVE UNDERFILL FOR FLIP CHIP APPLICATION

A New Continuous Wave 2500W Semiconductor Laser Vertical Stack

DEVELOPMENT AND EVALUATION OF FRACTURE MECHANICS TEST METHODS FOR SANDWICH COMPOSITES

Design for Plastic Ball Grid Array Solder Joint Reliability. S.-W. R. Lee, J. H. Lau*

ENHANCING WLCSP RELIABILITY THROUGH BUILD-UP STRUCTURE IMPROVEMENTS AND NEW SOLDER ALLOYS

Micro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation

World Academy of Science, Engineering and Technology International Journal of Electronics and Communication Engineering Vol:3, No:11, 2009

Ultralow Residue Semiconductor Grade Fluxes for Copper Pillar Flip-Chip

Predicting the Reliability of Zero-Level TSVs

The influence of loading direction on micro-crack behaviour in polymer composite

PROGRESSIVE FAILURE OF PULTRUDED FRP COLUMNS

Two dimensional (2D) RVE-Based Modeling of Interphase Separation and Particle Fracture in Graphite/5050 Particle Reinforced Composites

THROUGH-SILICON interposer (TSI) is a

Trapping mechanism of interface crack at concrete/engineered cementitious composite bimaterial interface

The influence of loading direction on micro-crack behaviour in polymer composite

Transcription:

3D FRACTURE MECHANICS ANALYSIS OF UNDERFILL DELAMINATION FOR FLIP CHIP PACKAGES Zhen Zhang, Charlie J Zhai, and Raj N Master Advanced Micro Devices, Inc. 1050 E. Arques Ave., Sunnyvale, CA 94085, USA Phone: 408-749-3106 Fax: 408-749-2907 Email: zhen.zhang@amd.com ABSTRACT: In flip-chip package, the mismatch of thermal expansion coefficients between the silicon die, copper heat spreader and packaging substrate induces concentrated stress field around the edges and corners of silicon die during assembly, testing and services. The concentrated stresses result in delamination on various interfaces involving a range of length scales from hundreds of nanometers to millimeters. Among these failures underfill delamination is a dominant failure mode. In this paper, a full parametric 3D model of flip chip package with heat spreader is developed with the capability of explicit modeling of 3D cracks. The crack driving force is computed as the functions of underfill properties including coefficient of thermal expansion and Young s modulus, as well as underfill fillet dimensions. The impact of different shapes of crack front is also investigated. The results show that underfill properties need to be optimized to minimize the occurrence of underfill delamination at the die corner. The results also show that there exists an optimal range of underfill fillet height to balance the manufacturability and reliability. KEY WORDS: underfill, delamination, 3D, FEA E G a NOMENCLATURE Young s modulus, GPa Energy release rate crack size Greek symbols α Coefficient of thermal expansion (CTE) Poisson s ratio ν INTRODUCTION It is well known that underfill has significant impact on flip chip package reliability. Organic substrate flip chip technology with underfill provides a cost effective solution to the demands of electronic packaging industry for increased reliability. Underfill protects solder bumps by considerably reducing the stress to the solder bumps. However, underfill itself is subject to shear or peeling stress and consequently, may induce additional failure modes. For instance, imperfect underfill with voids or microcracks will produce cracks or delamination under temperature cycling conditions. Delamination at bimaterial interfaces such as underfill and die passivation or underfill and substrate solder mask, driven by coefficient of thermal expansion (CTE) mismatch between organic substrate and silicon die, is one of the dominant failure modes in presence of imperfect underfill. Once underfill delamination, occurs, the failure usually results in solder bump fatigue crack because of the loss of underfill protection and stress concentration arising from the underfill delamination. In conventional stress analysis, a material is assumed to be free of defects. However, the junction of the three dimensional die corner and underfill is the potential failure site due to the presence of split singularity [1, 2]. The strength of singularity depends on the associated material properties and geometries. The delamination initiated from die edge takes a form of interfacial microcrack. In addition, initial delamination may also be the consequence of formation of microcracks or voids during dispensing process or surface contamination. Initial flaws are unavoidable in underfill. Hence preventing the flaw propagation as an unstable crack becomes important. The purpose of this paper is to study the effects of various design variables including underfill modulus, CTE, fillet dimensions on the energy release rate (ERR) of underfill delamination by using 3D fracture mechanics analysis in ABAQUS. MODEL Since temperature cycling is the cause of the failures studied in this paper, thermal excursion from 125C to room temperature 25C is used as the temperature loading. The flipchip is assumed to be in stress-free state at 125C, which is the typical glass transition temperature of epoxy underfill. Most material properties are assumed to be isotropic linear elastic. Although high-pb or eutectic solder is essentially rate and temperature dependent, material nonlinearity is not the focus of this work and will not be considered. Underfill material is assumed to behave linear elastically. As shown in Fig. 1, a quarter model of a three dimensional flip-chip is built up in ABAQUS for finite element analysis (FEA). ABAQUS is a powerful modeling tool that provides great flexibility of parametric modeling. In this study, a

parametric flip chip model with capability of automatic crack generation was created. Geometrical model includes silicon die (20 mm wide, 0.8 mm thick), organic package substrate (40 mm wide, 1.4 mm thick), epoxy underfill (0.09 mm thick), copper lid, gel-like TIM between die and lid, and adhesive for lid bonding with package substrate. It is also noteworthy that in this study the fillet shape is sketched with curvature close to reality and also with the flexibility to model different fillet width and fillet height. Only a quarter of the flip chip package is modeled because of symmetric geometry and loading conditions. All materials properties are tabulated in Table 1. A pre-existing crack is inserted along the interface from die corner between silicon die and underfill with the crack front convex inwards, as illustrated in Fig. 2. The upper part is silicon die (die passivation is neglected in the model), and the lower part is underfill. In order to illustrate the crack profile, fillet and all other materials are intentionally not shown here. The crack replicates the situation where a micro-crack is initiated from the die edge or an existing flaw due to non-clean surface. Fig. 2 also explains the definition of crack size a in this 3D model. Table 1. Material properties for flip chip package Materials E (GPa) ν α (ppm/c) Silicon die 130 0.28 3.3 Underfill 6 0.32 36 Copper lid 115 0.3 17.7 Lid adhesive 3.3e-3 0.3 300 TIM 6e-3 0.3 50 Package buildup 27.3 0.3 20 Package core 38 0.2 15.5 The design factors studied in this paper are: (1) Shape of crack front; (2) Underfill material properties (Young s modulus and CTE); (3) Underfill fillet height; (4) Crack size; (5) Comparison of results for lidded and lidless packages. (6) Comparison of results from 3D and 2D modeling. In order to study the effect of underfill material properties, we vary the modulus from 3 to 9 GPa, CTE from 20 to 50 ppm/c. These variations allow full characterization of the individual as well as coupled effects of underfill mechanical properties on fracture parameters. Baseline case assumes elastic modulus = 6 GPa and CTE = 36 ppm/ C for the underfill, as listed in Table 1. The influence of fillet height around die corner on underfill delamination is investigated by varying the baseline case, which assumes fillet of half coverage, i.e. the fillet height is half of die thickness, to the extreme configurations: no coverage and full coverage. These fillet configurations are intended to mimic properly encapsulated, under encapsulated and over encapsulated situations resulted from varied underfill dispense conditions. Figure 1. FEA model of a quarter symmetric package Note that in the following presentation, the loading is temperature drop T = 1 0 C. Therefore, from underfill glass transition temperature (125C) to room temperature, the energy release rate (ERR) should be multiplied by a factor of 10 4. RESULTS AND DISCUSSIONS a Fig. 2. Corner Crack Configuration Distribution of ERR along crack front Since in this study, a full 3D fracture mechanics-based FEA model is developed with explicit modeling capability of 3D crack. Along the whole crack front, the energy release rate (ERR) has a spatial distribution. The position with maximum ERR will propagate firstly. Therefore, the shape of the crack front will converge to a shape in favor of the fastest energy release. In this Fig. 3, we present the results for three different crack front profile, straight crack, arc crack and circular crack. The so called straight crack means the crack front is a straight line from point 1 to point 21; the arc crack means the crack front bows inwards to some extent; while the circular crack means that the crack front is a part of circle, just as penny crack; see Fig. 3(a). For all three cases, the ERR has the similar distribution with slight shift upwards if the

crack front moves inwards, as shown in Fig. 3. So the mid point 11 always has the maximum ERR, which means the crack prefers to propagate inwards from the center of the crack front. If the die is rectangular instead of square, the distribution profile skews to a little extent. ratio, fillet profile, etc, and the interactions among these factors. The choice of underfill modulus needs to take into consideration of the other factors to mitigate the risk of underfill delamination. crack size a=10um 21 11 1 8.0E-04 6.0E-04 4.0E-04 2.0E-04 0 5 10 CTE=20 (10^-6/C) 30 40 50 (a) Fig. 4. Energy release rate is plotted as a function of underfill modulus for different CTE with fixed crack size a=10um. The G either increases or decreases with the increase of modulus E, depending on CTE and crack size. 1.5E-03 1.0E-03 5.0E-04 0 5 10 15 20 points on crack front straight crack arc crack circular crack Fig. 3. (a) Stress field at the crack front energy release rate vs. crack front location Effect of underfill CTE Fig. 5 plots the energy release rate, G, as a function of underfill CTE, i.e.α, for different CTE with fixed crack size a =100um. In general the higher ERR will be produced by the higher CTE, despite the sensitivity is moderate. For instance, energy release rate increases by nearly 30% if underfill CTE varies from 20 ppm/c to 50 ppm/c. The effect of underfill CTE on ERR, as shown in Figure 5, clearly demonstrates that, in addition to global CTE mismatch between silicon die, copper lid and organic substrate, the local CTE mismatch among die and underfill also play a viable role in determining fracture behavior for underfill delamination. The results validate the general recommendation of lower- CTE underfill. crack size a=100um Effect of underfill modulus Fig. 4 plots the energy release rate, G, as a function of underfill modulus, E, for different CTE with fixed crack size a=10um. The G either increases or decreases with the increase of modulus E, depending on CTE and crack size. For high CTE (40ppm/C) and small cracks (<20um), G increases with E; otherwise G decreases with E. For CTE in the range of 30-40ppm/C, G is insensitive to E. The trends of either up or down in Fig. 4 are not captured by previous studies. The complex trends vs. underfill modulus underlines the facts that the ERR dependence on underfill modulus is not straightforward: it also depends on other factors including underfill CTE, crack size, die size, die aspect 5.0E-03 3.0E-03 1.0E-03 0 10 20 30 40 50 60 CTE, α (10^-6/K) 3 GPa 5 GPa 7 GPa 9 GPa Fig. 5. Energy release rate is plotted as a function of underfill CTE for different modulus with fixed crack size a=100um.

Effect of crack size Fig. 6 plots the energy release rate as a function of crack size for different modulus with fixed CTE=20ppm/C. The G increases rapidly with the propagation of crack in all the cases. Once the crack is initiated, it will continue to grow. produces approximately 2~3 times higher ERR than in the lidless package. 6.E-03 crack size a=100um, CTE=30(10^-6/C) 8.0E-03 6.0E-03 CTE=20ppm 0 50 100 150 200 250 Crack size, a (um) 3 GPa 5 GPa 7 GPa 9 GPa 5.E-03 4.E-03 3.E-03 2.E-03 1.E-03 lided unlided 0.E+00 0 2 4 6 8 10 Fig. 8. Comparison of lidded and lidless packages. Fig. 6. Energy release rate is plotted as a function of crack size for different modulus with fixed CTE=20ppm/C. Effect of underfill fillet height Fig. 7 plots the energy release rate as a function of normalized fillet height for baseline case. The energy release rate for different temperature excursions can be readily obtained from the fact that energy release rate is proportional to ( T ) 2. As shown in Fig. 7, the energy release rate G decreases with increasing fillet height. Therefore, the taller underfill fillet is critical to reducing to the risk of underfill delamination. Comparison of 3D model and 2D model Fig. 9 plots the G as a function of E for both 3D model and 2D plane strain models. Both 3D and 2D models show the same characteristics. However, 3D crack, in the same crack length, produces 3~5 times greater crack driving force than in the 2D crack. 2D model does predict correct trend, except significantly underestimating the magnitude of crack driving force. 6.0E-03 0 0.2 0.4 0.6 0.8 1 Fillet height normalized by die thickness Fig. 7. Effect of fillet height on energy release rate. 5.E-03 4.E-03 3.E-03 2.E-03 1.E-03 crack size a=100um 3D model 2D model (a) 0.E+00 0 2 4 6 8 10 Comparison of lidded and lidless packages Fig. 8 plots the energy release rate as a function of underfill modulus for two different packages: lidded and lidless. Same trends are exhibited for either lidded or lidless packages, despite in different magnitudes. The lidded package, however, Fig. 9. (a) A half model to 2D flip chip in FEA. Comparison of 3D model and 2D model.

CONCLUSIONS It has been demonstrated that it is possible to optimize design factors to reduce the risk of underfill delamination. The design factors studied in this paper involve material properties including elastic modulus and CTE, underfill fillet height, crack size, thermal solution, i.e. lidded and lidless through both 3D model and 2D model. From the results we find that underfill delamination for this particular flip chip configuration exhibits instability as the energy release rate increases with crack length. We found that the crack driving force is in general insensitive to the underfill modulus in the range between 3 and 9 GPa. Furthermore, the dependence on underfill modulus is affected by the interaction with other factors such as underfill CTE, etc. It is evident that lower-cte underfill is always favorable to reduce the energy release rate. Increasing fillet height is proved to be effective to prevent underfill delamination. Lower fillet (under encapsulation) has the highest probability of causing underfill delamination because it results in higher energy release rate. The lidded package has about 2~3 times larger G than lidless package. 2D model predicts correct trend, but results need to scale up 3~5 times to reflect 3D nature. flip-chip solder joints, J. Electronic Packaging 120 (4): 342-348, (1998). [11] Semmens, J.E. and Adams, T., Flip chip package failure mechanism, Solid State Technology 41(4): 59-64, (1998). [12] Suryanarayana D, Hsiao R, Gall TP, et al., Enhancement of flip-chip fatigue life by encapsulation, IEEE Trans. Components, Hybrids, & Manuf. Tech. 14(1): 218-223, (1991). References [1] Wang J. S. and, Suo Z., "Experimental determination of interfacial toughness curves using Brazil-nut-sandwiches", 1990, Acta Met., vol. 38, pp 1279-1290. [2] Liu, X.H., Suo, Z. and Ma, Q., Split singularities: stress field near the edge of a silicon die on a polymer substrate, Acta Mater. 47(1): 67-76, (1999). [3] Zhang Z., and Suo Z., Split singularities and the competition between crack penetration and debond at a bimaterial interface, Int. J. Solids Struct. 44(13), 4559-4573 (2007). [4] Zhai CJ, Sidharth, Blish RC, and Master R.N, Investigation and minimization of underfill delamination in flip chip packages, IEEE Trans. Device Mater. Reliability 4(1): 86-91, (2004). [5] Atluri, V.P., et al., Critical aspects of high-performance microprocessor packaging, MRS Bulletin 28(1): 21-34, (2003). [6] Chen, L, Zhang, Q, Wang, G.Z., et al. The effects of underfill and its material models on thermomechanical behaviors of a flip chip package, IEEE Transactions on Advanced Packaging 24(1): 17-24, (2001). [7] Fan X.J., Wang H.B., Lim T.B., Investigation of the underfill delamination and cracking in flip-chip modules under temperature cyclic loading, IEEE Trans. Components Packaging Tech. 24(1): 84-91, (2001). [8] Hirohata K., et al., Mechanical fatigue test method for chip/underfill delamination in flip-chip packages, IEEE Trans. Electronics Packaging Manuf. 25(3): 217-222, (2002). [9] Liu X.H., Lane, M.W., Shaw, T.M, and Simonyi, E., Delamination in patterned films, Int. J. Solids Struct. 44(6): 1706-1718, (2007 [10] Rzepka S, Korhonen MA, Meusel E, et al., The effect of underfill and underfill delamination on the thermal stress in