An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages Michael Hertl 1, Diane Weidmann 1, and Alex Ngai 2 1 Insidix, 24 rue du Drac, F-38180 Grenoble/Seyssins, France Phone: +33-(0)4-3812-4280 Fax: +33-(0)4-3812-0322 Email: michael.hertl@insidix.com 2 Teltec Semiconductor Pacific Ltd., 2802 Wing On House, 71 Des Voeux Rd. Central, Hong Kong Phone: (852) 2521 4213 Fax: (852) 2810 6090 Email: teltecalexngai@gmail.com Abstract - A new approach to reliability improvement and failure analysis on ICs is introduced, involving a specifically developed tool for Topography and Deformation Measurement (TDM) under thermal stress conditions. Applications are presented including delamination risk or bad solderability assessment on BGAs during JEDEC type reflow cycles. I. INTRODUCTION Today developers of ICs are facing reliability demands from customers asking for zero defect quality. Besides increasing costs and efforts to achieve this reliability level, even the classical technologies for reliability assessment are challenged. The current failure characterization technologies like X-ray imaging or scanning acoustic microscopy all follow a post-mortem approach, i.e. they only detect failure modes where the sample is already physically damaged. Thus with decreasing failure probability, a lot of time and effort is wasted in waiting for the manifestation of failures that are supposed not to happen. An increasing number of failures risks are due to the strongly increasing complexity of the assemblies rather than for example to one single weak interface. The number of layers in one single component is increasing, without the exact behaviors or layers and interfaces always well being known and understood. Therefore, damages like delaminations are increasing due to CTE mismatch of laminated materials. This phenomenon is particularly problematic in case of stacked dies, which are assembled by a number of successive solder processes, heating up the component to 260 C each time that a new layer is added. Therefore new experimental tools are required for the assessment of failure risks related to the thermo-mechanical stress of the components. II. EXPERIMENTAL more or less deformed by the sample s surface structure. The resulting image is captured by a CCD camera. Thermal stress generation is available by top and bottom heating and cooling elements. The current sample temperature is monitored. User defined temperature profiles with heating gradients up to +3 C/s and cooling gradients down to -6 C/s may be imposed to the component, within a temperature range from -60 C up to +300 C. The primary obtained information consists of high resolution 3D topography images of the entire assembly. The high depth of view (up to 32 mm) of the optical set-up allows to acquire all relevant levels of virtually every component or assembly simultaneously, as for example PCB, BGA substrate and BGA top surface. For each pixel, the (x,y,z) coordinates are absolutely known. After acquisition, software zoom on each level is possible and will reveal detailed surface information on a µm scale. Bottom thermocouple Light source Top thermocouple Camera Bottom heating Top heating Top Cooling Sample holder Bottom Cooling The experimental set-up is shown in Figure 1. The electronics package to be studied is illuminated by structured light (stripe pattern) on the sample surface. The stripe pattern is Fig. 1: Sketch of the Topography and Deformation Measurement (TDM) set-up.
Series 1 Series 2 Series 3 Series 4 III. APPLICATIONS A. Production Process Qualification Components are often produced by different sub-contractors, resulting in strong dispersion in terms of failure risk and reliability. Figure 2 presents SAM images obtained on 8 theoretically identical components produced by 2 different manufacturers (say A and B), after soldering. Components from manufacturer A (series 1 and 2) behaved well, while those from manufacturer B (series 3 and 4) show delamination. Details of component behavior during the reflow process have been obtained by the TDM system. Figure 3 shows the TDM analysis sequence for a BGA out of series 3. The BGA is initially slightly concave, and shows at the top temperature a strongly convex topography. After cooling down again to room temperature, residual deformation remains, indicating non Fig. 2: Differences in delaminations detected on theoretically identical components from 2 different manufacturers A(series 1 and 2) and B (series 3 and 4). z [µm] 25 C 25 C 150 C 143 C 165 C 173 C 183 C 200 C 157 C * 170 C * 200 C * 245 C Fig. 3: Topography following on a BGA during a JEDEC type reflow profile. This particular BGA is part of the series 3 in Fig. 2. 25 C = final Fig. 4: Topographies of one component out of each series shown in fig. 2. Topographies are shown at initial room temperature, maximum solder cycle temperature, and final room temperature after the solder cycle.
elastic deformation during the solder profile. Figure 4 shows the topographies of 4 different components, one out of each series as indicated in Fig. 2 (Comp. 1 is one component out of series 1, and so on). The first observation is that immediately after production, at room temperature, all 4 components show the same topography. The same finding is true for electrical tests or Scanning Acoustic Microscopy analysis: Directly after production, there is no detectable difference between all 4 components, no matter what kind of test is applied. However if we look at the topography measured by TDM at maximum temperature, a clear difference is seen between on the one side components out of series 1 and 2, and on the other side components out of series 3 and 4. Components out of the first two series show relatively low, and relatively homogeneous deformation. The components become convex, and the height increases gradually from the component borders to the center. The deformation amplitude in the center of the components is in the order of 60-80µm. On the other hand, components out of the series 3 and 4 show a different type of deformation at maximum solder temperature: They also become convex, but the deformation is mainly concentrated to the center of the components, whereas a large stripe along the borders stays more or less flat. Additionally, the deformation amplitude in the component center is much higher as for components out of series 1 and 2. Typical deformations at maximum temperature are in the order of 250µm for series 3 and 4 components. When coming back to room temperature, the series 1 and 2 components show very little hysteresis, i.e. their topography after the solder cycle is more or less the same as before the cycle. In contrast, series 3 and 4 components show residual deformation of about 70 µm in the component center. The surface topography variation with temperature is caused by elastic and plastic deformations due to internal stress accumulations. It is therefore related to the quality (in terms of ability to withstand typical solder conditions) and the expected reliability of the component. The measured deformations are related to the delamination risk during the solder cycle. Fig. 5: In-plane iso-displacement lines (x-direction) of a component (not soldered on the underlying PCB), when heating up the component from 25 C to 145 C. Fig. 6: In-plane iso-displacemnt lines (x-direction) of a PCB (without any component soldered), when heating up from 25 C to 145 C. B. CTE Mismatch Induced IC Failure Risk The evaluation of coefficients of thermal expansion (CTE) is necessary for minimizing the CTE mismatch of materials to be assembled. Otherwise, if the CTE of components and PCB is not matched, permanent shear stress will be loaded on the solder joints between components and PCB during cooling down of the assembly (hardening of the solder paste) after the solder process. The higher the permanent shear stress is, the higher will be the failure risk of the assembly during its life time in field. With TDM, in plane deformation (CTE) analysis is possible by digital image correlation for images taken at different temperatures. Fig. 7: In-plane iso-displacement lines (x-direction) of the component shown in Fig. 5 soldered on the PCB shown in Fig. 6, when heating up the assembly from 25 C to 145 C.
Fig. 5 shows the in-plane iso-displacement lines of a component in x-direction when the component is heated up from 25 C to 145 C. It can be deduced that, for this temperature increase, the component expands by about 16 µm in x-direction. Together with the known absolute size and the temperature increase, one can thus easily calculate the CTE value for the component in x-direction, which is found to be 14 10-6 1/K. Fig. 6 shows the same in-plane deformation analysis for the area of the PCB where the component will be soldered to, for the same temperature increase. The experimentally obtained x-direction expansion of the PCB on the solder area is about 12 µm, which allows to calculate the CTE value of the PCB to be about 10 10-6 1/K. Finally fig. 7 shows the same in-plane deformation field for the assembly, i.e. for the component shown in fig. 5 soldered on the PCB shown in fig. 6. The experimentally obtained CTE value of the assembly is 11 10-6 1/K. This analysis shows that the CTE values of the component and the PCB differ by about 40%, which is a quite important mismatch. The CTE of the assembly is very close to the CTE of the PCB alone, which means that the PCB governs the in-plane deformation characteristics of the assembly. The components have to follow the deformation imposed by the PCB. From that it is directly clear that the connectors of the component will face permanent shear stress during the entire assembly life time. C. Flip Chip on Chip Solderability Analysis The solderability and the reliability of the solder joints during product life time of components with bottom side solder ball arrays is among others determined by the amount of (out-of-plane) warpage of the component before, during, and after the solder process. Fig. 8 shows the bottom side of a Flip Chip on Chip component with 8 lines of solder balls. The warpage of the ball array has been analyzed by TDM. Fig. 9 shows the bottom side topography of the component at room temperature, with a height scale adapted to visualize the topography of the mould compound. The bottom side of the component has a concave topography, with an amplitude between component center and the borders of typically 60-120 µm. Fig. 8: Bottom side of the Flip Chip on Chip component. For optimum solderability, all solder balls should be coplanar at all temperatures during the reflow cycle. Fig. 9: Bottom side topography of the Flip Chip on Chip component. In this representation, a software thresholding of the height scale is done in such a way to show details of the mould compound topography. Other thresholdings allow to check the height of each single solder ball. Note that this topography has been obtained before any external heat load on the component. It therefore represents the component surface deformation due to internal stresses accumulated during manufacture of the component. For detailed analysis, 2D profiles along straight lines have been extracted from the topography in fig. 9. Fig. 10 shows the profiles along the red and blue arrows indicated in fig. 9, for room temperature conditions (thus for the same conditions as those prevailing in fig. 9). It can be seen that the TDM equipment if able to resolve single solder balls. The height of a solder ball can be deduced from fig. 10 to be about 350 µm. It can also be seen that the valleys of the profile extracted along the solder ball line overlap perfectly with the blue profile, extracted just besides the solder ball line. This observation might prove the reliability of the topography extracted on the solder ball line, along a quite complicated peak-valley structure. In terms of solderability, the annoying result is that along the (quite short) length of one single line of solder balls, the height difference between the central ball and the two balls on the outer side of the line is in the order of 100 µm. Therefore, when only inspecting this part at room temperature, the question of its solderability would be an issue. We then applied to the component a typical lead free JEDEC solder profile, with a top temperature of about 255 C, and acquired a similar topography as the one shown in fig. 9 at 215 C in the cooling cycle, i.e. at the temperature where the solder will solidify. The respective profiles on the mould compound and along the solder ball line as shown in fig. 9 is shown in fig. 11. Both profiles perfectly flattened out. The solder balls on the line are perfectly aligned at solder solidification temperature. From this topography we can deduce that the proper solidification of all solder balls will not be an issue at all for this component. However, for the assessment of the solder reliability during the life time of the
Fig. 10: 2D profiles extracted on the component topography as indicted by the arrows in fig. 9. The blue profile corresponds to the blue arrow, the red profile to the red arrow. The solder balls are clearly resolved. This profile is obtained on a component at room temperature. Fig. 11: 2D profiles extracted on the component topography as indicted by the arrows in fig. 9. The blue profile corresponds to the blue arrow, the red profile to the red arrow. The solder balls are clearly resolved. This profile is obtained on a component at 215 C, in the temperature decreasing part of a JEDEC type lead free solder profile. component on its PCB, we have to keep in mind the profiles obtained at room temperature (fig. 10). These profiles represent the topography that the component would show once back at room temperature, without being soldered to a PCB. Now a (more or less) stiff PCB will certainly hinder the component to come back to its usual room temperature shape, once the solder being solid. Therefore, permanent pull stress will be applied to the central solder balls of the component during the entire life time of the assembly. IV. SUMMARY A new failure analysis and reliability assessment approach has been developed for assessing failure modes of ICs due to thermal stress issues. The approach is based on surface topography analysis of ICs and assemblies under thermal stress conditions. An important application concerns the assessment of the ability of ICs to withstand typical JEDEC type solder cycles without too strong stress accumulation in the components. An important advantage of the new TDM technology is its predictive power, i.e. delamination or solder ball breakage risks may be visualized before physical failure occurs. Three examples have been discussed for application of TDM in analysis of failures risks on ICs and assemblies. In each example, analysis of the different components in an early stage of the development and production cycle allows an early failure or failure risk recognition, successive design optimizations, and thus shorter time to market as well as lower risk of customer returns. In the first application example the surface topography variation with temperature caused by elastic and plastic deformations due to internal stress accumulations is the only way to differentiate good and bad components. The topography variation with temperature is related to the quality (in terms of ability to withstand typical solder conditions) and the expected reliability of the component. The measured deformations are related to the delamination risk during the solder cycle. We can conclude that analysis of the topography variation constitutes an ideal complement to the widely used SAM analysis of the components. However while SAM acquisitions are only possible at room temperature, TDM adds a lot more information by giving detailed insight in the component variation for varying temperatures. In the second application example we demonstrated that even for a perfectly behaving IC package (without any out-of-plane warpage issue), an important reliability risk concerns
itspossible CTE mismatch with the PCB it is soldered on. Thus the knowledge of the CTE value of a specific component alone is not sufficient to describe accurately the behavior of this component once it is assembled on a PCB, neither for practical purposes of failure risk minimization nor for numerical modeling of the assembly. Once the component is soldered on the PCB, the stiffer one of the two parts (lower CTE) will retain the one with the higher CTE value when temperature is increasing, and an intermediate CTE value will govern the assembly. In the third application example we highlight once again the importance of warpage variation with temperature for assessment of the quality of a IC package. In fact, the package presented here might be rejected for too high warpage when analysed at room temperature. However it occurs that it becomes perfectly flat at the solder solidification temperature. The knowledge of this topography variation opens the way to answer the relevant question for this package: It does not concern the solderability, but the reliability of the solder joints once the solder process is done.