R Sensor resistance (Ω) ρ Specific resistivity of bulk Silicon (Ω cm) d Diameter of measuring point (cm)

Similar documents
CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

The Effect of Annealing on Resistivity Measurements of TiSi 2 and TiN Using the collinear Four Point Probe Technique

Fabrication Technology

Microelectronics Devices

Lecture 0: Introduction

Materials of Engineering ENGR 151 ELECTRCIAL PROPERTIES

Development of Silicon Pad and Strip Detector in High Energy Physics

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:

Slide 1. Slide 2. Slide 3. Chapter 19: Electronic Materials. Learning Objectives. Introduction

Crystalline Silicon Solar Cells With Two Different Metals. Toshiyuki Sameshima*, Kazuya Kogure, and Masahiko Hasumi

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

Semiconductor Very Basics

9/4/2008 GMU, ECE 680 Physical VLSI Design

Czochralski Crystal Growth

ET3034TUx High efficiency concepts of c- Si wafer based solar cells

IC Fabrication Technology Part III Devices in Semiconductor Processes

EE 330 Lecture 12. Devices in Semiconductor Processes

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY

TOWARD MEMS!Instructor: Riadh W. Y. Habash

This Appendix discusses the main IC fabrication processes.

CMOS VLSI Design. Introduction. All materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN. Introduction

Chapter 2 Manufacturing Process

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

MATERIALS. Silicon Wafers... J 04 J 01. MATERIALS / Inorganics & thin films guide

Lab IV: Electrical Properties

Change in stoichiometry

EECS130 Integrated Circuit Devices

Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance

HYPRES. Hypres MCM Process Design Rules 04/12/2016

SEMICONDUCTORS R. A. SMITH CAMBRIDGE AT THE UNIVERSITY PRESS. M.A., PH.D. Head of the Physics Department Royal Radar Establishment Malvern J 959

Supporting Information

VLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris

Manufacturing Process

Quarterly Report EPRI Agreement W

Chapter 3 CMOS processing technology

CX Thin Fil s. Resistors Attenuators Thin-Film Products Thin-Film Services. ISO 9001:2008 RoHS/REACH Compliant ITAR Compliant

Processing of Semiconducting Materials Prof. Pallab Banerjee Department of Material Science Indian Institute of Technology, Kharagpur

EE 330 Lecture 9. IC Fabrication Technology Part 2

6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term Solution to Problem Set 2 (16 pts)

Silicon Wafer Processing PAKAGING AND TEST

Department of Electrical Engineering. Jungli, Taiwan

Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon

Ion Implantation Most modern devices doped using ion implanters Ionize gas sources (single +, 2+ or 3+ ionization) Accelerate dopant ions to very

Process Flow in Cross Sections

Surface micromachining and Process flow part 1

CMOS Manufacturing process. Design rule set

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005

"Plasma CVD passivation; Key to high efficiency silicon solar cells",

Instructor: Dr. M. Razaghi. Silicon Oxidation

Fabrication of Nanoscale Silicon Membranes on SOI Wafers Using Photolithography and Selective Etching Techniques:

1. Introduction. What is implantation? Advantages

VLSI Design and Simulation

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

Thin Film Circuit Substrate(RUSUB TM )

Chapter 3 Silicon Device Fabrication Technology

VLSI Digital Systems Design

Materials, Electronics and Renewable Energy

CHAPTER 4: Oxidation. Chapter 4 1. Oxidation of silicon is an important process in VLSI. The typical roles of SiO 2 are:

EE 143 CMOS Process Flow

EE THERMAL OXIDATION - Chapter 6. Basic Concepts

Fairchild Semiconductor Application Note June 1983 Revised March 2003

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam

THERMAL OXIDATION - Chapter 6 Basic Concepts

ASIM-X MEMS-Specific Design Rules

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Chapter 2 Capacitive Sensing Electrodes

Gallium Nitride Based HEMT Devices

An advantage of thin-film silicon solar cells is that they can be deposited on glass substrates and flexible substrates.

EE 434 Lecture 9. IC Fabrication Technology

OPTICAL, ELECTRICAL AND STRUCTURAL PROPERTIES OF PECVD QUASI EPITAXIAL PHOSPHOROUS DOPED SILICON FILMS ON CRYSTALLINE SILICON SUBSTRATE

Ion Implantation Most modern devices doped using ion implanters Implant dopants by accelerating individual atoms (ions) Ionize gas sources (single +,

1 HRL Laboratories, LLC, Malibu, California, Baskin School of Engineering, University of California, Santa Cruz, CA *

FABRICATION of MOSFETs

Chapter 18: Electrical Properties

SiGeC Cantilever Micro Cooler

MEMS II: January 23. Lab 1: Pop-up mirror - PolyMUMPS - Thermal actuators - Mirror CoventorWare

IC/MEMS Fabrication - Outline. Fabrication

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

Lecture 22: Integrated circuit fabrication

L5: Micromachining processes 1/7 01/22/02

Exam 1 Friday Sept 22

Dr. Lynn Fuller Webpage:

MATTHEW A. WICKHAM 5th Year Microelectronic Engineering Student Rochester Institute of Technology ABSTRACT

Graduate Student Presentations

Lecture 1A: Manufacturing& Layout

VAR. Vishay Foil Resistors FEATURES INTRODUCTION

Semiconductor Technology

162 Solar Energy. front contact (metal grid) serial connections (to the back contact of the next cell) p-type wafer back contact

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

Passive TCF Compensation in High Q Silicon Micromechanical Resonators

EE 560 FABRICATION OF MOS CIRCUITS. Kenneth R. Laker, University of Pennsylvania

Transcription:

4 Silicon Temperature Sensors 4.1 Introduction The KTY temperature sensor developed by Infineon Technologies is based on the principle of the Spreading Resistance. The expression Spreading Resistance derives from a method, called the one-pointmethod (Figure 19) used to measure the specific resistivity of semiconductor wafers. The resistance R is given by: R = ρ ------------ π d where: R Sensor resistance (Ω) ρ Specific resistivity of bulk Silicon (Ω cm) d Diameter of measuring point (cm) This measurement is independent of the thickness, D and the diameter of the wafer, as long as the contact point diameter d is negligibly small in comparison. In addition, the contact resistance between semiconductor and metal is also measured. Figure 19 Measuring the Specific Resistance of Semiconductors Using the One-point Method In a conventional temperature sensor based on the principle of spreading resistance, a contact hole in the oxide mask serves as the measuring point (Figure 20). In order to comply with the measuring principle, the hole diameter must be negligibly small compared to the chip dimensions. An essential feature of the spreading resistance sensor is that it contains no p/n junction. Data Book 1 2000-07-01

Figure 20 Conventional Spreading Resistance Temperature Sensor The basic conduction mechanism can be explained by looking at a single Si-crystal. At normal temperatures all crystal locations are ionised, so an increase in temperature does not lead to an increase in the number of charge carriers. However, the increased lattice energy associated with a rise in temperature leads to an increase in the phonon scatter within the crystal and thereby increases the resistance. A Si-temperature sensor based on the spreading resistance principle therefore has a positive temperature coefficient (Figure 21). Figure 21 Change in the Specific Conductivity of Silicon with the Reciprical Temperature 1/T The temperature range of dislocation creation is limited by the intrinsic conductivity process at higher temperatures and by the dislocation reserves at low temperatures. This gives a natural boundary on the measurement range of a Spreading resistance sensor, it is dependent on the crystal doping. A specific resistance of about 7 Ωcm Data Book 2 2000-07-01

results in a TC factor (100 C/25 C) of 1.70. With a hole diameter of 22 µm this gives a resistance value of 1000 Ω. In a conventional spreading resistance temperature sensor the current flow spreads from the contact hole in the oxide mask on the chip surface through to to the rearside of the chip (Figure 19).This construction is assymmetric and, due to the non-ohmic contact between the metalisation and the silicon, produces to a resistor which is dependent on current direction. To overcome this, a symmetric construction was selected for the KTY temperature sensor (Figure 22). Here, two spreading-resistance sensors are put in series with one another, the current through the sensor then flows through two identical contact holes in the oxide mask. With this arrangement the sensor is low in capacitance; this means that the sensor has to be protected against high voltages. With the optimised values of 7 Ωcm and 22 µm hole diameter the sensor resistance is defined at (2 1000) Ω= 2000 Ω. Figure 22 Schematic Cross Section through the Temperature Sensor KTY Chip Figure 23 View on the KTY Sensor Chip Data Book 3 2000-07-01

4.2 Technology of the KTY Temperature Sensor Photolithography with image definitions in the sub micron range are used to produce the KTY temperature sensor. A double layer of Oxide and Nitride on the chip surface serves as an insulation film. After deposition of the contact areas, this is again covered with plasma nitride, only that over the contact point being etched away to allow bonding. The chip produced in this process is thereby fully passivated against environmental influences. In order to increase the yield of chips per wafer which fall into the tightest possible tolerance band, neutron activated material is used in the production of the KTY sensors. In this doping method the silicon wafer is implanted with neutrons in a nuclear reactor which change Si-atoms into P-atoms. This method allows not only a precise doping level (to 0,1%), but also gives exceptionally high homogeneity (1% Tolerance on doping level instead of 15% with normal material ). The quality of the contact of the back of the Silicon chip to the metal lead frame is a further factor influencing the resistance value of a conventional spreading resistor sensor. With the KTY sensor the chip rear side is coated with Gold and alloyed to the lead frame. In comparison to the conventionally used adhesive solution this leads to a higher stability of the bonding between the sensor chip and the lead frame. The restrictions placed on the contact holes are decisive for the reproducibility and the long term stability. In the KTY sensor a multi-layer metalisation is employed as opposed to the conventional Al-Metalisation. This multi-layer metalisation of Ti-Pt-Au, was developed for industrial microwave components which normally have very high current densities and which place strong demands on reliability. This together with Au-thermocompression bondwire contacting assures high reliability in the KTY sensor. Figure 24 shows results of long-term high temperature steady state operation. Data Book 4 2000-07-01

Figure 24 Drift of the Resistance R with Long-term High Temperature Steady State Operation Spread of Resistance Value and Corresponding Temperature Error (I op = 1 ma) Table 10 T Resistance Band Ω Temperature Deviation C R 25 = 2000 Ω± 1% R 25 = 1000 Ω± 1% C 50 1002.2 1070.5 501.1 535.2 ± 3.43 45 1053.0 1121.0 526.5 560.5 ± 3.29 40 1105.9 1173.3 553.0 586.7 ± 3.15 35 1160.9 1227.5 580.4 613.7 ± 3.00 30 1217.9 1283.5 608.9 641.7 ± 2.86 25 1276.9 1341.3 638.4 670.7 ± 2.71 20 1338.0 1401.0 669.0 700.5 ± 2.57 15 1401.1 1462.4 700.6 731.2 ± 2.43 10 1466.3 1525.7 733.1 762.9 ± 2.28 5 1533.5 1590.9 766.8 795.4 ± 2.14 0 1602.8 1657.8 801.4 828.9 ± 1.99 5 1674.2 1726.6 837.1 863.3 ± 1.85 10 1747.5 1797.2 873.8 898.6 ± 1.71 Data Book 5 2000-07-01

Table 10 (cont d) T C Resistance Band Ω R 25 = 2000 Ω± 1% R 25 = 1000 Ω± 1% 15 1823.0 1869.6 911.5 934.8 ± 1.56 20 1900.5 1943.9 950.2 972.0 ± 1.42 25 1980.0 2020.0 990.0 1010.0 ± 1.27 30 2057.0 2102.6 1028.5 1051.3 ± 1.41 35 2135.8 2187.3 1067.9 1093.6 ± 1.56 40 2216.4 2274.0 1108.2 1137.0 ± 1.71 45 2298.8 2362.7 1149.4 1181.4 ± 1.85 50 2383.1 2453.5 1191.5 1226.8 ± 1.99 55 2469.2 2546.4 1234.6 1273.2 ± 2.14 60 2557.1 2641.3 1278.6 1320.6 ± 2.28 65 2646.9 2738.2 1323.4 1369.1 ± 2.43 70 2738.5 2837.2 1369.2 1418.6 ± 2.57 75 2831.9 2938.3 1415.9 1469.1 ± 2.71 80 2927.1 3041.4 1463.6 1520.7 ± 2.86 85 3024.2 3146.5 1512.1 1573.3 ± 3.00 90 3123.1 3253.7 1561.5 1626.9 ± 3.15 95 3223.8 3363.0 1611.9 1681.5 ± 3.29 100 3326.3 3474.3 1663.2 1737.2 ± 3.43 105 3430.7 3587.7 1715.3 1793.8 ± 3.58 110 3536.9 3703.1 1768.4 1851.5 ± 3.72 115 3644.9 3820.5 1822.5 1910.3 ± 3.87 120 3754.8 3940.0 1877.4 1970.0 ± 4.01 125 3866.4 4061.6 1933.2 2030.8 ± 4.15 130 3979.9 4185.2 1990.0 2092.6 ± 4.30 135 4043.5 4256.3 2021.7 2128.2 ± 4.44 140 4145.0 4367.5 2072.5 2183.8 ± 4.59 145 4246.6 4478.9 2123.3 2239.4 ± 4.73 150 4348.1 4590.2 2174.0 2295.1 ± 4.87 Temperature Deviation C Data Book 6 2000-07-01