Measurement of thickness of native silicon dioxide with a scanning electron microscope

Similar documents
A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

SUPPLEMENTARY INFORMATIONS

Silver Diffusion Bonding and Layer Transfer of Lithium Niobate to Silicon

Semiconductor Technology

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width

RIE lag in diffractive optical element etching

Czochralski Crystal Growth

Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO 2 (glass) Major factor in making

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Chapter 3 Silicon Device Fabrication Technology

the surface of a wafer, usually silicone. In this process, an oxidizing agent diffuses into the wafer

X-Ray Reflectivity Study of Hafnium Silicate Thin Films Prepared by Thermal Chemical Vapor Deposition

UHF-ECR Plasma Etching System for Gate Electrode Processing

Formation of High-quality Aluminum Oxide under Ion Beam Irradiation

A Functional Micro-Solid Oxide Fuel Cell with. Nanometer Freestanding Electrolyte

MICROCHIP MANUFACTURING by S. Wolf

UV15: For Fabrication of Polymer Optical Waveguides

Nanoscale Imaging, Material Removal and Deposition for Fabrication of Cutting-edge Semiconductor Devices

MICROFABRICATION OF OPTICALLY ACTIVE InO X MICROSTRUCTURES BY ULTRASHORT LASER PULSES

Mater. Res. Soc. Symp. Proc. Vol Materials Research Society

EECS130 Integrated Circuit Devices

Self organization and properties of Black Silicon

PATTERNING OF OXIDE THIN FILMS BY UV-LASER ABLATION

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Growth and Doping of SiC-Thin Films on Low-Stress, Amorphous Si 3 N 4 /Si Substrates for Robust Microelectromechanical Systems Applications

The Effect of Interfacial Roughness on the Electrical Properties of Organic Thin Film Transistors with Anisotropic Dielectric Layer

MICROCHIP MANUFACTURING by S. Wolf

EUV Transmission Lens Design and Manufacturing Method

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Available online at ScienceDirect. Materials Today: Proceedings 2 (2015 )

Instructor: Dr. M. Razaghi. Silicon Oxidation

Supporting Information for Effects of Thickness on the Metal-Insulator Transition in Free-Standing Vanadium Dioxide Nanocrystals

Fabrication of Nanoscale Silicon Membranes on SOI Wafers Using Photolithography and Selective Etching Techniques:

IC Fabrication Technology Part III Devices in Semiconductor Processes

Chemical Vapor Deposition

Fully-integrated, Bezel-less Transistor Arrays Using Reversibly Foldable Interconnects and Stretchable Origami Substrates

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

Physical Vapor Deposition (PVD) Zheng Yang

Silicon nitride deposited by ECR CVD at room temperature for LOCOS isolation technology

O2 Plasma Damage and Dielectric Recoveries to Patterned CDO Low-k Dielectrics

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

EUV Transmission Lens Design and Manufacturing Method

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

THE INCREASE IN THICKNESS UNIFORMITY OF FILMS OBTAINED BY MAGNETRON SPUTTERING WITH ROTATING SUBSTRATE

Fundamentals of X-ray diffraction and scattering

Introduction to Lithography

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

In-Situ Low-Angle Cross Sectioning: Bevel Slope Flattening due to Self-Alignment Effects

ABSTRACT. which indicates the implanted region did not adequately inhibit the diffusion of oxygen.

ECE 541/ME 541 Microelectronic Fabrication Techniques

Method to obtain TEOS PECVD Silicon Oxide Thick Layers for Optoelectronics devices Application

High Pressure Chemical Vapor Deposition to make Multimaterial Optical Fibers

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook

ise J. A. Woollam Ellipsometry Solutions

Supplementary Figure 1 TEM of external salt byproducts. TEM image of some salt byproducts precipitated out separately from the Si network, with

UT Austin, ECE Department VLSI Design 2. CMOS Fabrication, Layout Rules

Integrated Silicon Heater for Tip-Based. Nanomanufacturing

Review of CMOS Processing Technology

Specimen configuration

SnO 2 Thin Films Prepared by Sol Gel Method for Honeycomb Textured Silicon Solar Cells

MARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices

Ellipsometry as a tool for identifying process issues in roll-to-roll sputter deposited metal-oxide coatings

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

Doping and Oxidation

Fabrication Technology, Part I

Properties of Inverse Opal Photonic Crystals Grown By Atomic Layer Deposition

Synchrotron X-Ray Topography Measurements on 4H-SiC Epitaxial Layer

ALD Film Characterization Rachel Brown 5/13/14

Transmission Kikuchi Diffraction in the Scanning Electron Microscope

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005

THIN METALLIC LAYERS STRUCTURED BY E-BEAM LITHOGRAPHY. Miroslav HORÁČEK, Vladimír KOLAŘÍK, Michal URBÁNEK, František MATĚJKA, Milan MATĚJKA

There are basically two approaches for bulk micromachining of. silicon, wet and dry. Wet bulk micromachining is usually carried out

Today s Class. Materials for MEMS

Deep-etched fused silica grating as a (de)multiplexer for DWDM application at the wavelength of 1.55µm

Heterostructures of Oxides and Semiconductors - Growth and Structural Studies

Supporting Information for the Manuscript: Dramatic. Increase In Polymer Glass Transition Temperature. Under Extreme Nanoconfinement In

IBS/e Ion Beam Sputter Deposition and Etching System. IBS/e with KDC-10 Ion Beam Sputter Deposition and Etching System with Kaufman Ion Source

Polycrystalline Silicon Produced by Joule-Heating Induced Crystallization

Manufacturer Part Number. Module 2: CMOS FEOL Analysis

Fabrication of photonic band-gap crystals

The Physical Structure (NMOS)

F. J. Cadieu*, I. Vander, Y. Rong, and R. W. Zuneska, Physics Department, Queens College of CUNY, Flushing, NY

Electrical Characterization of Tungsten Nanowires Deposited by Focused Ion Beam (FIB) *

Platypus Gold Coated Substrates. Bringing Science to the Surface

Simultaneous Reflection and Transmission Measurements of Scandium Oxide Thin Films in the Extreme Ultraviolet

Lecture #18 Fabrication OUTLINE

FIB mask repair technology for EUV mask 1. INTRODUCTION

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS

ALD of Scandium Oxide from Tris(N,N -diisopropylacetamidinato)scandium and Water

Lecture 5. SOI Micromachining. SOI MUMPs. SOI Micromachining. Silicon-on-Insulator Microstructures. Agenda:

Chapter 4 : ULSI Process Integration (0.18 m CMOS Process)

Chapter 2 Capacitive Sensing Electrodes

A Study of the Formation Modes of Nanosized Oxide Structures of Gallium Arsenide by Local Anodic Oxidation

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

EE 330 Lecture 9. IC Fabrication Technology Part 2

Amorphous and Polycrystalline Thin-Film Transistors

Procedia Chemistry 1 (2009) Proceedings of the Eurosensors XXIII conference

Fabrication and Layout

A Study of the Formation Modes of Nanosized Oxide Structures of Gallium Arsenide by Local Anodic Oxidation

Transcription:

Measurement of thickness of native silicon dioxide with a scanning electron microscope V. P. Gavrilenko* a, Yu. A. Novikov b, A. V. Rakov b, P. A. Todua a a Center for Surface and Vacuum Research, 40 Novatorov Str., Moscow 119421, Russia, E-mail: fgupnicpv@mail.ru; b A.M. Prokhorov General Physics Institute of the Russian Academy of Sciences, 38 Vavilov Str., Moscow 119991, Russia, E-mail: nya@kapella.gpi.ru. ABSTRACT We are describing a method of measuring thickness of a native silicon dioxide film using a scanning electron microscope. The method consists of etch removal of native silicon dioxide from the surface of trenches in silicon with a right-angled profile, with a subsequent measurement of an increase in trench width. The thickness of a native silicon dioxide film measured with the help of this method turned out to be 2.39 ± 0.12 nm. Keywords: silicon, silicon dioxide, native silicon dioxide, scanning electron microscopy 1. INTRODUCTION Development of modern nanoelectronics [1] which uses primarily silicon has met with a number of problems, among which the problem of how to decrease the thickness of an insulating layer between the gate and the semiconductor down to the thickness of the native silicon dioxide is of considerable importance. To solve this problem, it is necessary to know the thickness of the native silicon dioxide layer which forms on the surface of a silicon crystal when it interacts with the surrounding medium. Due to a small value of this thickness, the existing methods to measure it [2 4] are difficult to implement and are not accurate enough. Fabrication of the trenches in silicon with a profile close to the rightangled one and a certified trench width [5,6] enables one to use such structures for direct measurement of the thickness of the native silicon dioxide layer using scanning electron microscopy [7]. This paper presents the results of such measurements. 2. METHOD THEORY There is always a film of native silicon dioxide on monosilicon surface. Let us assume that we perform an etch removal of this film in a liquid etchant (e.g, in HF) and then expose the monosilicon to the air. In the course of time, the native silicon dioxide film is restored. Figure 1 shows a schematic of such process. Let N(x) be the number of atoms (molecules) of material x. In order to produce N(SiO 2 ) molecules of SiO 2 of the native silicon dioxide film, N(Si) silicon atoms are used: N(Si) = N(SiO 2 ). (1) As a result, the position of the Si- SiO 2 interphase surface is shifted by the quantity h(si) (see Fig. 1). The number of atoms or molecules can be determine from the expression N N = A ρhs, (2) A where N A is the Avogadro constant, A is the atomic weight (or the molecular weight in the case of the SiO 2 molecules), ρ is the density of the material, S is the film area, and h is its thickness. Then the thickness of the silicon that was used to create the native silicon dioxide film is given by the expression Instrumentation, Metrology, and Standards for Nanomanufacturing III, edited by Michael T. Postek, John A. Allgair, Proc. of SPIE Vol. 7405, 740507 2009 SPIE CCC code: 0277-786X/09/$18 doi: 10.1117/12.826190 Proc. of SPIE Vol. 7405 740507-1

ρ ( ) ( ) ( SiO2 ) A( SiO2 ) h Si h0 SiO2 ρ( Si) A( Si) =. (3) The same quantity h(si) determines the shift of the surface of the silicon wafer (see Fig. 1). h(si) h 0 (SiO 2 ) Si h(si) h 0 (SiO 2 ) Si Figure 1. Schematic of the shift of the surface of the silicon wafer upon performing the etch removal and the subsequent restoration of the native silicon dioxide film. In order to measure the shift of the silicon surface, let us fabricate a relief right-angled structure (RRAS) having the form of trenches, one of the walls of which is the surface of the monosilicon (). Let us assume that the material of the other trench s wall is the amorphous silicon (a-si). In this case we obtain the formula for the increase of the trench width upon performing the single etch removal of the native silicon dioxide on the both walls of the trench ( SiO ) A( Si) A( SiO ) ( m SiO2 ) ( m Si) ( a SiO ) ( ) a Si ρ 2 h0 h0 2 h n = h( m Si) + h( a Si) = +. (4) 2 ρ ρ In the case when the thicknesses of the native silicon dioxide films on amorphous silicon and monosilicon are equal ( m SiO ) = h ( a SiO ) h ( ) h =, (5) 0 2 0 2 0 SiO2 we obtain the following formula for the increase of the trench width upon performing the single etch removal of the native silicon dioxide from the both walls of the trench h n ( SiO2 ) A( Si) 1 ( ) + A SiO ρ ( m Si) ρ ( a Si) 2 ρ 1 = h0 ( SiO2 ). (6) Thus, by etch removal of the native silicon dioxide film, it is possible to determine the thickness of the native silicon dioxide film h 0 (SiO 2 ), provided that the change of the trench s width h n is known. 3. METHOD OF FABRICATING RIGHT-ANGLED TRENCHES IN SILICON An RRAS sample represents a slit-like structure in silicon and consists of about 1000 trenches aligned along the same straight line. The trenches are of 5 µm in length, and have 10 µm repetition period. The trench depth is in the range of 0.1 10 µm. The trench width is the size being certified. It lies in the 0.1 0.5 µm range. The process of RRAS creation consists of standard technological operations typical for fabrication of microelectronic devices. A schematic of this process is shown in Fig. 2. A polished side of monosilicon wafer, which is an n- or p-type conductor, was chosen as one of the trench s walls (see Fig. 2a). The trenches identity and the parallel location of the walls are achieved by the growth of SiO 2 thin film, which is uniform in thickness (see Fig. 2b). The smoothness of the second wall of the trench is due to the smoothness of the SiO 2 surface, whereas the parallel location of the walls of the trench follows from the uniformity of the SiO 2 thickness. The thickness of the SiO 2 film (see Fig. 2,b) is determined by ellipsometry (cf. [8]). We would like to note that in order to use the ellipsometric technique, the parameters of the SiO 2 film should satisfy the conditions of the applicability of the ellipsometric model for measuring the thickness of the optically-uniform film located on an absorbing isotropic substrate; the boundary between the film and the substrate should be sharp (see Ref. [8]). In order to verify the Proc. of SPIE Vol. 7405 740507-2

uniformity of the SiO 2 film thickness, measurements of the polarization angles ψ and Δ were repeatedly performed in various points on the wafer with the help of the LEF-3M ellipsometer. The thickness of the SiO 2 film and the SiO 2 refractive index were obtained using the main equations of the ellipsometry technique and the measured angles ψ and Δ (see also Ref. [8]). When the non-uniformity of the thickness of the SiO 2 film exceeded 1 nm, the wafer was rejected. (a) SiO 2 h (b) Photoresist mask (c) (d) (e) a-si (f) a-si (g) Figure 2. Fabrication process for trenches with right-angled profile. A great number of trenches (about 1000) were fabricated as a result of fabrication of a periodic grating on a silicon wafer (see Figs. 2c-2e) using the created SiO 2 film (the width of the strips was 5 µm, the grating period was 10 µm). To accomplish this, a photoresist mask was created on the SiO 2 film (see Fig. 2c), and an isotropic etching of SiO 2 is performed through this mask (see Fig. 2d). After removing the photoresist mask we obtain a silicon wafer with the grating of SiO 2 (see Fig. 2e). The grating plays a dual role. On the one hand, a great number of trenches of the same width are formed in the resulting structure. On the other hand, after performing a selective etching of the SiO 2 film, which plays the role of an intermediate layer, the space between the slit-like elements is filled with material of the upper layer which plays the role of the strengthening ribs and protects the second wall against the flexure that could lead to the trench width variation. Material that can meet the requirement of the smoothness of the second wall is deposed on the fabricated structure (see Fig. 2f). The width of the second wall is determined by the size of the region of generation of the slow secondary electrons. The size of this region is about 3 µm in the case when the energy of the primary electrons is in the 20 30 kev range. Therefore, in order to exclude the effect of the outer wall of the RRAS on the SEM image of the trench, the Proc. of SPIE Vol. 7405 740507-3

width of the second wall was taken equal to 4 5 µm. We use amorphous silicon (a-si) for the upper layer [9], the granularity of the amorphous silicon being smaller than the resolution of scanning electron microscopes. In order to fabricate amorphous silicon films of required thickness, special conditions of silicon deposition from the gas phase was used. The study of these films was performed using an electron diffractometer, scanning electron microscope, and the positron annihilation technique. Figure 3 shows the electron diffraction patterns (electron energy was 100 kev) for the inner (Fig. 3a) and outer (Fig. 3b) surfaces of the silicon film. It can be seen that the inner surface of the silicon film is amorphous, whereas the outer surface is crystal. (a) (b) Figure 3. Electron diffraction patterns for the inner (a) and outer (b) surfaces of the silicon film. The granularity of the created amorphous silicon (a-si) was studied in an SM-30 transmission electron microscope, which has the 0.15 nm resolution [5]. It was found that the SO2 boundary is localized with the uncertainty of about 0.3 nm. In the region of the SiO2 a-si boundary, the a-si film is amorphous with widely spaced impregnations of crystal grains of the 1 3 nm size. The study of the a-si films using the positron annihilation technique [9] has shown that the films are really in the amorphous state. The region near the inner film surface is also amorphous (cf. [5,9]). It is this surface that ensures smoothness of the second wall of the trench. The results of the study of the films, and the proof that they are in the amorphous state are also given in Ref. [9]. The fabricated multilayer structure was then broken across the formed grating of SiO2, and silicon dioxide was selectively etched (see Fig. 2g). After such selective etching, we obtained the trenches with the and a-si walls. Since the trench width is equal to the width of the SiO2 film being etched, by varying the oxidation time for silicon, it is possible to fabricate the required set of trenches of different width, and by varying the etching time for the SiO2 film, it is possible to fabricate the trenches of different depth. Table. The width li of the trenches of the relief right-angled structures (RRASs) fabricated using silicon of the n- and p-type conductivity (n-rras and p-rras). The results are given for k = 1. li ± Δli, nm i n-rras p-rras 1 2 3 4 92.8 ± 0.4 128.5 ± 0.3 344.4 ± 0.8 486.2 ± 0.8 98.9 ± 0.4 150.7 ± 0.3 369.7 ± 0.8 434.7 ± 0.8 Using the method described above, we fabricated four samples with four different certified trench widths on the wafers of silicon being the n- and p-type conductors (see the Table). These four samples (with different trench widths) were Proc. of SPIE Vol. 7405 740507-4

gathered in a special holder and placed on a working stage. The construction of the stage enables one to use it practically in all modern scanning electron microscopes (SEMs). Figure 4a shows a micrograph of the trenches of the RRASs with two different trench widths, whereas Fig. 4b shows a micrograph of the cleavage of one of the trenches with the 150.7 nm width and the 850 nm depth. (a) (b) Figure 4. (a) Micrograph of trenches of the relief right-angled structures (RRASs) with two different widths (150.7 and 434.7 nm); (b) micrograph of the cleavage of the trench of the RRAS with the 150.7 nm width and 850 nm depth. We would like to note that similar structures were fabricated in the National Institute of Standards and Technology (NIST, USA) [10]. The difference of the NIST-fabricated structures from the structures described above is that for the NIST-fabricated structures the second wall was made of polycrystal silicon. For the NIST-fabricated structures, the trench widths were also certified using ellipsometry [11]. 4. EXPERIMENTAL RESULTS AND DISCUSSION We performed an experiment using three samples, which consisted of trenches with the width l = 369.7 ± 0.8 nm, and with the initial depth of 3 µm. The first sample was not etched, while the second and third ones were etched 5 times and 10 times, respectively, in a 40% water solution of HF. The etching time was 10 s, and the time interval between two successive etchings was no less than two days. The study of the structures was performed using an SEM 515 scanning electron microscope, operating in the mode of collection of slow secondary electrons. For each value of the width, 20 signals from the trench were recorded. Figure 5a shows an example of such signal. For each signal, we measured the distance between the peaks L and the size of the bottom of the signal G (see Fig. 5b), and then we determined their mean values, the standard deviations, and standard deviation of the mean value. It was shown in articles [5,6] that the width of a right-angled trench l is related to the parameters L and G of the signal by the following equations l = L M 2δ, (7) l = G M + d, (8) where M is the SEM magnification, δ is the shift of the signal peak relative to the coordinate corresponding to the trench s wall, and d is the effective diameter of the SEM electron beam. These expression can be used for determination of the M, d and δ parameters [5,6]. In the course of the experiment, it is necessary to go from one sample to another. In this case, some focus tuning of the SEM electron beam is required for each sample. It can lead to the change of the electron beam diameter d and of the value of δ. Physical reasons for these effects are given in Ref. [12]. A method how to control the sameness of the focusing was proposed in Ref. [13]. The gist of the method is as follows. Proc. of SPIE Vol. 7405 740507-5

(a) L (b) G Figure 5. (a) SEM signal obtained in the mode of collection of slow secondary electrons when scanning a trench of the l = 369.7 nm width and of the h = 3 µm depth after ten-fold etch removal of the native silicon dioxide. (b) Schematic of the SEM signal obtained when scanning a trench of the RRAS, where the parameters being measured are indicated. From expressions (7) and (8), we obtain the following relation ( d + 2δ ) L G = M. (9) The left-hand side of relation (9) includes two measured quantities: L and G, whereas the right-hand side of this equation includes the SEM parameters (the magnification M and the electron beam diameter d), and the parameter δ. If the quantities M, d and δ are constant during the experiment, the difference L G should be constant for the experimental results obtained for different samples [13]. Figure 6 shows experimental results for the difference L G obtained for three samples being used (for different numbers of the etch removals n of the native silicon dioxide). It can be seen that the value of L G is constant within the uncertainty limits. It indicates that the values of M, d and δ are the same for all the experimental results. We determined the M and δ parameters as the result of the SEM calibration with the help of the trenches of the RRAS of the p-type conductivity [6] (all the experimental results are given in the present paper for k = 1): M = 90900 ± 1700, L G, mm 6 δ = 3.5 ± 2.3 nm. 5 4 0 5 10 n Figure 6. The results of the determination of the quantity L G for three samples being used (for different numbers of the etch removals n of native silicon dioxide). The thickness of the native silicon dioxide was determined using the dependence of the distance L between the peaks of the signal (see Fig. 5) on the number of etch removals n. Figure 7 shows the experimental dependence of the value of L on the number of etch removals n, which is described by the linear function L = L 0 + L n. (10) n Proc. of SPIE Vol. 7405 740507-6

L, mm 35 34 33 32 0 5 10 n Figure 7. The dependence of the distance L between the peaks located on the signal (cf. Fig. 5b) on the number of etch removals n of the film of the native silicon dioxide. The straight line corresponds to the least squares fitting for the experimental points. Using the least squares fitting, we obtain the parameters of the function (10) L 0 = 32.43 ± 0.06 mm, L n = 0.206 ± 0.009 mm. Using the parameters of the SEM calibration and the experimental results for of the L 0 and L n values, we obtain the following relations l n = L n /M = 2.27 ± 0.11 nm, l t0 = L 0 /M 2δ = 364 ± 5 nm. Here l t0 is the width of the trench for which the native silicon dioxide film was not etched, whereas l n is the increase of the trench width in the case of the single etch removal (l n = h n, where h n was taken from expression (6)). Within the error bars, the quantity l t0 coincides with the certified size 369.7 ± 0.8 nm (see the Table), which support the correctness of our experiment. In order to determine the thickness of the native silicon dioxide film, we used the following parameters for silicon ρ(fused silica) = 2.202 g/cm 3, ρ() = 2.32902 g/cm 3, ρ(a-si) = 2.03 g/cm 3, films on the surface of the amorphous silicon and on the surface of the monosilicon are equal, and that the density of the fused silica is equal to the density of the native silicon dioxide: ρ(fused silica) = ρ( SiO 2 ), we obtain with the help of relation (6) the following value for the thickness of the native silicon dioxide film h 0 (SiO 2 ) = 2.39 ± 0.12 nm, which is in a good agreement with the experimental values obtained by other methods. 5. CONCLUSIONS We measured the thickness of native silicon dioxide film by direct method using a scanning electron microscope. The method described in this paper enables one to study the formation of native oxide film on the surface of both silicon and other materials, which can be used for fabrication of slit-like structures, similar to those fabricated in silicon. REFERENCES 1. International Technology Roadmap for Semiconductors. Metrology Roadmap. 2007. / public.itrs.net. 2. G. A. Egorova, E. V. Ivanova, E. V. Potapov, A. V. Rakov, Optics and Spectroscopy, 36, No. 4, 773 (1974) (in Russian). Proc. of SPIE Vol. 7405 740507-7

3. P. Durgapal, J. R. Ehrstein, N. V. Nguyen, Thin Film Ellipsometry Metrology, International Conference Characterization and Metrology for ULSI Technology, 121-131 (1998). 4. D. A. Muller, Gate Dielectric Metrology Using Advanced TEM Measurements, International Conference Characterization and Metrology for ULSI Technology, 500-505 (2001). 5. Yu. A. Novikov, S. V. Peshekhonov, I. B. Strizhkov, The slit-like reference gauge structure for the SEM calibration and measurements of relief elements in submicron and nanometer ranges, Proceedings of the General Physics Institute, Vol. 49, 20-40 (1995) (in Russian). 6. Yu. A. Novikov, A. V. Rakov, Measurements of Submicron Pattern Features on Solid Surfaces with a Scanning Electron Microscope: 2. New Concept of Scanning Electron Microscope-based Metrology (A Review), Russian Microelectronics, 25, No. 6, 375-383 (1996). 7. Yu. A. Novikov, A. V. Rakov, S. V. Sedov, I. B. Strizhkov, Measurement of natural silicon oxide thickness by scanning electron microscopy, Physics, Chemistry, and Mechanics of Surfaces, 11, No. 1, 53-56 (1995). 8. Yu. A. Novikov, S. V. Peshekhonov, The ellipsometry method errors of evaluation of a silicon and dioxide silicon film optical characteristics, Proceedings of the General Physics Institute, Vol. 49, 107-118 (1995) (in Russian). 9. N. M. Manzha, Yu. A. Novikov, S. V. Peshekhonov, A. V. Rakov, V. P. Shantarovich, Study of the silicon films by the positron method, Surface, No. 12, 89-95 (1989) (in Russian). 10. M. T. Postek, Scanning electron microscope - based metrological electron microscope system and new prototype scanning electron microscope magnification standard, Scanning Microscopy, 3, No. 4, 1087-1099 (1989). 11. J. Geist, B. Belzer, M. L. Miller, P. Roitman, Optical calibration of a submicrometer magnification standard, J. Res. Nat. Inst. Stand. Technol., 97, No. 2, 267-272 (1992). 12. Yu. A. Novikov, A. V. Rakov, Mechanisms of secondary electron emission from the relief surface of a solid, Surface Investigation, 15, No. 8, 1177-1194 (2000). 13. Yu. A. Novikov, A. V. Rakov, I. Yu. Stekolin, Scanning electron microscope calibration with input data checking, Measurement techniques, 38, No. 6, 697-700 (1995). 14. E. M. Voronkova, B. N. Grechushnikov, G. I. Distler, I. P. Petrov, Optical materials for infrared engineering, Moscow, Nauka, 1965 (in Russian). Proc. of SPIE Vol. 7405 740507-8