Via Fill in Small Trenches using Hot Aluminum Process. By Alice Wong

Similar documents
The Berkeley Marvell NanoLab

Chapter 3 Silicon Device Fabrication Technology

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

Microelectronic Device Instructional Laboratory. Table of Contents

Czochralski Crystal Growth

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

2015 EE410-LOCOS 0.5µm Poly CMOS Process Run Card Lot ID:

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley

The Physical Structure (NMOS)

Make sure the exam paper has 9 pages total (including cover page)

ALD Film Characterization Rachel Brown 5/13/14

Lecture #18 Fabrication OUTLINE

EECS130 Integrated Circuit Devices

Marvell NanoLab Summer Internship 2011

EE143 Microfabrication Technology Fall 2009 Homework #2 - Answers

IC/MEMS Fabrication - Outline. Fabrication

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

Lecture 1A: Manufacturing& Layout

Because of equipment availability, cost, and time, we will use aluminum as the top side conductor

Total Points = 110 possible (graded out of 100)

MEMORANDUM I. OVERVIEW

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers

CMOS Technology. Flow varies with process types & company. Start with substrate selection. N-Well CMOS Twin-Well CMOS STI

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook

EE 330 Lecture 9. IC Fabrication Technology Part 2

Schematic creation of MOS field effect transistor.

Chapter 3 CMOS processing technology

Mostafa Soliman, Ph.D. May 5 th 2014

Physical Vapor Deposition (PVD) Zheng Yang

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

Photolithography I ( Part 2 )

Lab #2 Wafer Cleaning (RCA cleaning)

Lecture 2: CMOS Fabrication Mark McDermott Electrical and Computer Engineering The University of Texas at Austin

Microfabrication of Integrated Circuits

MEMS Surface Fabrication

EE 143 CMOS Process Flow

UT Austin, ECE Department VLSI Design 2. CMOS Fabrication, Layout Rules

Complexity of IC Metallization. Early 21 st Century IC Technology

Report 2. Aaron Pederson EE 432 Lab Dr. Meng Lu netid: abp250 Lab instructor: Yunfei Zhao. Steps:

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

CMOS FABRICATION. n WELL PROCESS

Thin Films: Sputtering Systems (Jaeger Ch 6 & Ruska Ch 7,) Can deposit any material on any substrate (in principal) Start with pumping down to high

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

A Deep Silicon RIE Primer Bosch Etching of Deep Structures in Silicon

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller

Fabrication Technology, Part II

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

Kinetics of Silicon Oxidation in a Rapid Thermal Processor

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

How To Write A Flowchart

Chapter 4 : ULSI Process Integration (0.18 m CMOS Process)

Fabrication and Layout

1

Fraunhofer IZM Bump Bonding and Electronic Packaging

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

Today s Class. Materials for MEMS

Plasma Etching Rates & Gases Gas ratios affects etch rate & etch ratios to resist/substrate

User Fees for the 4D LABS Fabrication Facility

Process Flow in Cross Sections

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to

Surface micromachining and Process flow part 1

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #9

Review of CMOS Processing Technology

Thermal Nanoimprinting Basics

ECE321 Electronics I

Bulk MEMS Fabrication Blog 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

Test Patterns for Chemical Mechanical Polish Characterization

Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

Photolithography Process Technology

Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

Summary of Selected EMCR650/731 Projects for Jeremiah Hebding Dr. Lynn Fuller

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development

Lifetime Enhancement and Low-Cost Technology Development for High-Efficiency Manufacturable Silicon Solar Cells. A. Rohatgi, V. Yelundur, J.

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Chapter 5 Thermal Processes

EE 434 Lecture 9. IC Fabrication Technology

This Appendix discusses the main IC fabrication processes.

Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications

CALTECH CONFERENCE ON VLSI, January 1979

VLSI Technology. By: Ajay Kumar Gautam

6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term Solution to Problem Set 2 (16 pts)

0.35 µm CMOS PROCESS ON SIX-INCH WAFERS, Baseline Report VI.

Oxidation SMT Yau - 1

4. Thermal Oxidation. a) Equipment Atmospheric Furnace

Silicon Manufacturing

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS

Lecture 22: Integrated circuit fabrication

CMOS Manufacturing process. Design rule set

Silicon Epitaxial CVD Want to create very sharp PN boundary grow one type layer on other in single crystal form High dopant layers on low dopant

Intlvac Nanochrome I Sputter System (intlvac_sputter)

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis

Transcription:

Via Fill in Small Trenches using Hot Aluminum Process By Alice Wong

Goals for Project Good Via Fill in Small contact holes using hot aluminum process Be able to get good images of the contact holes using the Scanning Electron Microscope

Goals for Project Good Via Fill in Small contact holes using hot aluminum process Be able to get good images of the contact holes using the Scanning Electron Microscope Could Pinch Off

Goals for Project Good Via Fill in Small contact holes using hot aluminum process Be able to get good images of the contact holes using the Scanning Electron Microscope Could Pinch Off Could Make Air Pocket

Equipment Furnaces Sinks Novellus Leo ASM Lithography SVG Coat 6 SVG DEV 6 Nanospec ASIQ Matrix UV Bake Microscopes Wafer Saw Centura-mxp

Procedure Start with 6 P type Prime wafers Silicon Wafer

Procedure Grow ~2 um LTO Sink 6 Tystar 11 (LTO) Tystar 2 (Anneal) LTO Silicon Wafer

Procedure Photolithography SVG Coat 6 ASML (CMOS 180 Contact Mask) SVG DEV 6 UV Bake Photoresist LTO Silicon Wafer

Procedure Etch Centura- MXP Photoresist LTO Silicon Wafer

Procedure Aluminum Deposition Novellus Aluminum LTO Silicon Wafer

Procedure Grow ~1 Micron of LTO Sink 5 Tystar 12 NO Anneal Aluminum LTO LTO Silicon Wafer

Hot Al Process Cold Al Process Al Etch Ti Glue Al Al TSP Al TSP Al Etch Ti Glue Al Al TSP Heater Temp 400 50 500 500 Heater Temp 400 300 350 Ar flow/ pres. 1.4 mt 40 sccm 4 mt 4 mt Ar flow/ pres. 1.4 mt 5 sccm 2 mt Etch/ Dep Power (kw) 25% 15% 84% 9% Etch/ Dep Power (kw) 25% 60% 75% Dep/ Etch Time(s) 45 56 21 195 Dep/ Etch Time(s) 45 19 47 Back Side Argon on? Yes Yes No Yes Back Side Argon on? Yes Yes Yes

Results 10 um Contact Vacuum.5 um Contacts.35 um Contacts Silicon Wafer 2 um Contact 1 um Contacts

Results Silicon Wafer

Results LTO Silicon Wafer

Results Aluminum LTO Silicon Wafer

Results Aluminum LTO LTO Silicon Wafer

Results LTO Pinching Off Aluminum LTO Silicon Wafer

Results LTO Pinching Off Aluminum LTO Silicon Wafer Air Pocket

2 um contacts Cold Al process Hot Al Process

2 um contacts Cold Al process Hot Al Process Al Balled up On the Edge

2 um contacts Cold Al process Hot Al Process Al Balled up On the Edge Al Flowed Over the Edge

Results C s = (T thin / T thick ) x 100 Depth.66 um.57 um 1.19 um 1.04 um 1.62 um 1.63 um 10 um 93% 68% 80% 49% 78% 72% 2 um 56% 49% 13% 30% 18% 34% Contact Size 1 um.5 um.35 um 22% 31% x 32% 18% 3% 7% 6% 2% 13% 7% 5% 16% 5% 2% 13% 9% 3%

Spiking Si Wafer Al Diffusing Into Si Wafer Vacuum

Al Alloy Planarization Methods -Standard Two Step Process -Reflow Enhanced Mobility Contact or Via 0.6 um

Al Alloy Planarization Methods -Standard Two Step Process -Reflow Enhanced Mobility Contact or Via 0.6 um

Al Alloy Planarization Methods -Standard Two Step Process -Reflow Enhanced Mobility -Low Pressure Two Step Process Directional Sputter Neutrals Contact or Via Contact or Via 0.6 um 0.35 um

Conclusion Get better step coverage using the Hot Al Process Hot Al process is designed for contacts down to.6 um Still unable to get complete contact fill Future Directions Improve the cross sectioning Use focus ion beam (FIB) Effect of Ti on this process Include Collimation

What I learned Learned about different types of equipment Learned about lab safety procedures Became familiar with Microlab jargon Became familiar with Lab Maintenance procedures Became familiar with the Wand

Acknowledgements Thank you Kim Chan, Sia Parsa, Laszlo Petho, Attila Szabo, Jimmy Chang, Joe Donnelly and Rosemary Spivey Thanks to Katalin Voros for giving me such a wonderful opportunity Thanks to Daniel Queen for being my mentor, explaining things when I didn t understand them, and for helping me get acquainted with the lab Thanks to Marilyn Kushner for taking us to Semi Con Thanks to Chris and Eric for helping me run my process Thanks to the Lab Assistants for letting me follow you around

Novellus Hot Aluminum Process Using two layer aluminum films deposited at different temperatures will improve step coverage. To do this, the Al Two Step Process (TSP) is used 1. Deposit 500 A Ti under layer (used as glue layer) cold just before Al. The Ti cold layer not only works as a glue, but also enhances capillary action that draws Al into trench.

Novellus Hot Aluminum Process 2. Deposit a 400 nm cold Aluminum layer at high deposition rate (> 190 A/sec) on a cold wafer. No back side Argon during deposition, this will keep the wafer temperature low. 3. Deposit a hot layer at a slow rate with Back Side Argon on. With the BSA on, the wafer temperature ramps up quickly to a high temperature. The low deposition rate allows time for the surface migration of Al atoms to fill in the trench.