Optical interconnect: a back end integration scheme for waveguides and optoelectronic InP components. Fedeli J.M. b Jeannot S a.,jousseaume V. b, Di Cioccio L. b, Kostrzewa M. b Orobtchouk R. c, Maury P. a, Zussy M. b a STMicroelectronics, 850 rue Jean Monnet, 38921 Crolles, France b CEA-DRT/LETI, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France C INSA/LPM, Bât. Blaise Pascal, 7 avenue Jean Capelle 69621 Villeurbanne, France ABSTRACT Photonic on CMOS represents the combination of CMOS technology with integrated optics components. It can bring either a new functionality to the electronic circuit or the driving and the amplifying means to the optical components. In the first case, as global interconnections are expected to face severe limitations in the future, optical interconnects could be an alternative to electrical ones. An integration scheme for an optical signal distribution compatible with a Back End Of the Line microelectronic process is presented. Fabrication of the waveguides on top of Integrated Circuits is followed by the molecular bonding of InP dies, needed to perform the optoelectronic components (sources and detectors). Using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, optical layers and basic components necessary for an optical distribution were developed. Waveguides with low losses (L<2.5dB@1.3µm with Si 3 N 4, L<17dB/cm @1.55µm for a:si as long as compact 90 microbends and MultiMode Interferometer Beamsplitters were achieved. The molecular bonding of InP dies on CMOS wafers was studied for the integration of active components. The InP wafers are sawed to form mm 2 square dies and are composed of the epitaxial active layers and especially with a sacrificial, etch-stop layer (InGaAs). Molecular bonding of the dies was performed at room temperature and the thickness of the SiO2 bonding layers ranges up to 1µm. After annealing, the dies can support dicing or other mechanical actions with no degradation of the optical properties. INTRODUCTION In its constant development towards new level of performance and integration, microelectronic components aim to integrate new functions and new technologies. Theses different functions can be realized by a means of different materials monolithically integrated to the IC. Recently, it was also demonstrated that the optical interconnects could increase the IC performances. In the classical IC the communication between the different devices is done thanks to the electrical connections. In the face of the further miniaturization and higher working frequencies this solution can be insufficient for future systems. To overcome theses problems, the optical interconnects could replace at least a part of metallic interconnects and in this way increase the IC features. One of a possible approach allowing the optical interconnect realization is to fabricate a passive optical layer containing waveguides, microbends etc above CMOS IC. The next step is a monolithic integration of III-V optical devices and optical coupling to the passive waveguide layer. Figure 1 presents one of possible configuration of the optical interconnect, the optical signal can be guided from source to receiver which converts the optical signal to the electrical photocurrent. The current is droved by a metallic via to the CMOS receiver which regenerates the electrical, digital output signal. Finally, this signal can then if necessary be distributed over a small zone by a local electrical interconnect network [1]. Indeed, the integration of optical functions compatible with a microelectronic process presents new interesting potentialities for integrated circuits but a monolitic integration of dissimilar functions remains still a difficult technological challenge. However, different ways are still proposed for the integration of optical functions with electronics, like free space optical interconnect [2] or using Silicon On Insulator (SOI) technology [3]. Incorporation of new functionality in a microelectronic process must fulfil technology constraints, leading basically to two kind of possible integration:
With a Front End integration scheme, the new components (waveguides, optoelectronic components) are realized at the beginning of the IC process at the same level than the transistors. Using this approach, realization of various process steps are possible, allowing SOI photonic for instance, but this requires an important modification at the level of the electronic design. It requires a totally new technology combining CMOS and photonics constraints and changes the design rules. This scheme represents the long term integration of photonics in microelectronic world. With a Back End approach, a photonic layer is defined above the transistors and the dielectric /metallic levels. This leads to the constraint of using a low temperature technology that must not exceed higher temperature than 400 C. Based on this last approach, we focused on the integration of basic optical functions, waveguides, directions changes and beamsplitters in order to perform optical link on a chip. A 200mm technological platform with high index contrast materials is needed, allowing compact devices with low optical losses. Not to disturb the behavior of the microelectronic components, optical devices are developed in the Near Infra Red (NIR) wavelength range (1.3 or 1.55µm). Silicon nitride and amorphous silicon layers were grown by Plasma Enhanced Chemical Vapor Deposition (PECVD) at low temperature. Optical development and characterization of the materials is presented, as well as characterization of basic components necessary to allow an optical distribution on a chip. The molecular bonding of InP dies on CMOS wafers was performed for the integration of active components and will be developed in the second part of the paper. Figure 1: Cross section of optical interconnect configuration [1]. INTEGRATION OF THE PHOTONIC LAYER As the microelectronic process is very mature, introduction of a new part of the process like the integration of a photonic layer is a difficult issue and the most compatible process steps are preferred. However like the introduction of copper for electrical interconnect, new materials like III-V ones can be introduced on the wafers in a dedicated part of the CMOS clean room. The obvious way to introduce a photonic layer is to treat it as a additional metallic layers on top of most of the layers for the electrical interconnect. The integration of optical component on top of ICs must then fulfil to Back End Of the Line integration constraints, which is mainly to perform all technological steps under 400 C. So, typical monocristalline silicon waveguides cannot be used directly due to the high processing temperature, but by full wafer bonding of an optical SOI, they can be reported on a CMOS wafer[4]. For back-end waveguide, Plasma Enhanced Chemical Vapor Deposited silicon nitride is deposited on low index material like PECVD SiO2 which also acts as the cladding layer. After a CMP planarizing operation, MQW layers on InP dies are then reported on top of the waveguides. The InP substrate of the dies is then removed by chemical etching and further processing steps lead to sources and detectors linked to the metallic interconnects.
Si3N4 waveguides Bonding III-V Partially processed CMOS InP Substrate removal Electrodes fabrication of source and photodetectors Figure 2: low temperature process integration scheme. WAVEGUIDE FABRICATION As the area of a CMOS circuit ranges generally from 1cm 2 to 2 cm 2, only medium (0.5) or high (2) index contrast index materials relative to silicon dioxide were considered. So, silicon oxide, silicon nitride, amorphous silicon films were deposited by a capacitively coupled plasma reactor, with a RF excitation frequency (13.56 MHz). The power can be tuned from 30 to 1200W and the operative pressure can vary from 0.2 to few torrs. Films were deposited at temperatures lower than 400 C. TEOS was used as precursor for oxide deposition. Si-H 4 /N2O chemistry was used for nitride deposition and silane/h 2 mixture for amorphous silicon. Films were characterized using a spectroscopic ellipsometer (GESP5 SOPRA) in the range 0.2 to 1.8µm FTIR Analysis was performed on a Biorad QS500 spectrometer. Intrinsic optical guided losses on full wafer during process were measured using a prism coupling technique (METRICON 5010) @1.3µm and 1.55µm. Silicon nitride has been widely used as optical layers, nevertheless to avoid light absorption due to N-H bonds, high temperature anneals were performed [5]. In this work, at low temperature, PECVD materials are highly hydrogenated. Monitoring the deposition conditions, we have been able to tune the refractive index between 1.82 and 2.3 @1.3µm. SIMS analysis shown in table 1 suggest that the variation of the refractive index is not only due to the SI/ N ratio, but certainly to the incorporation of hydrogen in the layers. Sample Normalized [Si] content Normalized [N] content Normalized Si/N ratio Normalized [H] content R.I @ 1.3µm 1 1 1 1 1 1,827 2 0,383 0,914 0,4196 0,42 1,874 3 0.541 0,737 0,734 0,734 2,23 Table 1: evolution of Refractive Index with Silicon nitride composition
Fig 3 shows the variation of Refractive Index and optical losses @1.3µm with the deposition power. Optical layers with low losses are obtained ( L<0.5dB/cm) for refractive index between 1.82 and 2. Due to the large presence of Hydrogen in the layers, rather high losses are obtained at 1.55µm. With FTIR analysis (fig 4), the losses can be correlated to the [N-H] content. 4 2,30 Optical Losses @1,3µm (db/cm) 3,5 3 2,5 2 1,5 1 0,5 2,20 2,10 2,00 1,90 1,80 1,70 Refractive Index 0 1,60 180 230 280 330 480 Deposition power (W) Figure 3: Evolution of the optical losses and the Refractive Index varying with deposition power. 14 Optical losses @1.55µm (db/cm) 12 10 8 6 4 2 0 0 0,5 1 1,5 2 2,5 3 3,5 4 [N-H] content (FTIR analysis)( A.U) Figure 4: Optical losses @ 1.55µm as a function of [N-H] content. Increasing the refractive index contrast between the cladding and the guiding medium leads to more compact devices. So amorphous silicon deposited by PECVD is a promising candidate. While silicon is still extensively studied in SOI configuration or using high temperature deposition and annealing methods, very few studies reports results on PECVD amorphous silicon used as guiding medium. By optimising the H 2 /Silane ratio in the deposition chamber, silicon films with losses as low as 0.2dB/cm @1.55µm after annealing are achievable (fig 5).
optical losses @1.55µm (db/cm) 0,8 0,6 0,4 0,2 after deposition after a 350 C 4H anneal 0,0-0,5 0,0 0,5 1,0 1,5 2,0 2,5 3,0 3,5 H 2 /SiH 4 Figure 5: Evolution of the optical losses before and after a 350 C anneal during 4 Hours for different H2/SiH4 gaz ratio. Using these materials, basic blocks for optical links like submicronic waveguides, 90 micro bends and MultiModeInterferometer (MMI) beamsplitters have been designed. The modelisation of waveguides with a strong field confinement is performed using a full vectorial finite difference mode solver including symmetries and transparent conditions at the limits [6]. Design of beam splitters and compact directional changes are performed using 2D FDTD associated with the effective index method. Optimisation was performed with more accurate 3D FDTD (Finite difference in Time Domain) calculations. Optical devices were fabricated using a standard CMOS technology on 200mm wafers and diced with a polishing edge technique. Optical characterizations of the components are performed using an integrated optical bench, composed of 3D nano-handlers. Light was injected in the circuit by butt coupling method with a lensed fiber with a waist of 2 µm. The collect was done with a multimode fiber linked to an optical spectrum analyser (Agilent 86140B). The observation was performed using an infrared linear response Hamamatsu video camera. As with monocristalline silicon on SOI, the high index difference allows the simultaneous use of refractive compact components (waveguides 0.2*0.5µm, bends with radius <3µm and MMI 1 to 2 less than 6µm²) and photonic crystals components for wavelength functionality. Preliminary characterisations of 0.3*0.3µm waveguides show loss values of 17 db/cm, which is an encouraging value, at the state of the art with deposited silicon [7]. With SiN deposited films, waveguides with a thickness of 400nm and a wideness of 800 nm were fabricated with a silicon dioxide cladding. They exhibited straight losses of 2.5dB/cm in TE polarization at 1.55µm. Ninety degrees microbends were measured for different radius of curvature. Curves with radius of 5µm showed high losses (1.55dB) while no losses were measured for radius above 30µm. Beamsplitters using MultiModeInterférence (MMI) were simulated and characterized. The division of one input to two inputs and one input to four outputs have been tested and the components showed a good equilibration ( E<0.2dB and 0.45db @1.3µm respectively (see fig 5) and with low loss (L<0.4 and 0.05dB@1.3µm respectively). The good equilibrium of our component proves the good correlation between simulation and experiment. Figure 7 shows the cross-cut of the SiN waveguide with a SiO2 cladding.these basic blocks were selected to demonstrate the possibility of distribution network for example optical clock distribution for CMOS circuitry. Light were input and output in the optical network via surface gratings. MMI one to two and 20µm microbends formed the optical circuitry.
0-2 -4 In/I0 (db) -6-8 -10-12 -14-16 1250 1300 1350 1400 λ (nm) Figure 6: FDTD simulation and experimental spectral response of a 1 to 4 MMI device. Figure 7: Cross-cut of a SiN waveguide with SiO2 cladding Fig 7: One to sixteen distribution network DIE TO WAFER BONDING Even the latest development on silicon photonics, III-V components remain more efficient for harnessing light. However the cost of the wafers and the processing on small diameter wafers lead to rather expensive components. Integration of InP components coupled to a distribution network on top of a CMOS required a new approach different from the flip-chip solution. Another objective was to process the InP components in the same way as CMOS transistor in order to reduce the cost of the introduction of III-V components. As passive components can be efficiently developed with SiN or Si technology, only the active components require the InP technology. On large CMOS circuit, a very limited surface would be occupied by the sources, modulators and photodetectors. Moreover high speed operation lead to small size components. So our approach consists in dicing an InP wafer with all the heteroepitaxial layers, bonding the dies at the specific needed spots, subtracting the InP die substrates in order to leave only the active thin films on the CMOS wafer, processing the InP components on a dedicated 200 or 300 mm fabrication line. To report the dies, molecular bonding was selected as a good bonding quality is achieved without any additional adhesive materials [8]-[9]. As a matter of fact, the presence of the bonding material could be harmful for efficient optical coupling. Additionally,
the molecular bonding satisfies the requirements in term of thermal conductivity and dissipation, transparency at the device working wavelengths and mechanical resistance. The surface morphology and chemistry are critical to the bonding quality. Prior bonding the die, surface must be flat and uniform. Required flatness and uniformity can be obtained by use of CMP. The additional role of CMP polishing is to adjust the thickness of the silicon dioxide cladding layer in order to satisfy the requirements of optical coupling conditions. The surfaces are carefully cleaned and hydrated in the chemical solution. Bonding can occur spontaneously when the prepared wafers are made of silicon. A complete physical model of such a molecular bonding was proposed and presented by Stengl et al. [10] and Gösele et al. [11]. As the materials are of dissimilar nature, one possible way to their assembly is to deposit a silicon dioxide or a silicon nitride layer on each surface. Using this approach we have succeed in the heterogeneous integration of InP 50 mm wafers on silicon and then the InP dies containing an epitaxial layer stack with multiple quantum wells (MQW). The CMOS wafer with SiO 2 top cladding is polished to reach a low roughness, cleaned in deionized water and then dried. A silicon dioxide layer is deposited and then processed on InP (100) epi-ready substrate using Electron Cyclotron Resonance plasma. Thanks to this preparation, the bonding of the both InP/SiO 2 and CMOS/SiO 2 wafers is similar to the Si/SiO 2 on Si/SiO 2 bonding. More details about InP-on-Silicon wafer bonding was described elsewhere [12]-[13]. In this paper we concentrate on the bonding of InP dies on CMOS silicon wafer. For this purpose, the above wafer-to-wafer bonding procedure was first adapted to InP dies bonding on silicon substrate. The dies are obtained by a mechanical dicing of 360 µm thick InP substrate containing an epitaxial heterostructure and a thin silicon dioxide layer. The minimal die size we have bonded is 1 x 1 mm². A pick&place apparatus can be used to report the InP dies on the Silicon substrate. The bonding itself occurs spontaneously at room temperature; however, an annealing at 200 C during several hours reinforces adhesion. Mechanical dies thinning down to 20 µm was achieved after bonding without degrading the remaining bonded material quality (Figure 8). Next, the remaining InP substrate and the sacrificial InGaAs layer can be chemically and selectively back-etched. The additional post-bonding technological steps as polishing show that the assembled InP dies on the Si substrate can endure many kind of mechanical action without debonding. The bond strength between the die and the substrate was measured using Die Shear testing equipment. The obtained shear strength is of 5 MPa ± 1.4 MPa for 1 mm², 360 µm thick InP dies. Using this approach we bonded a die containing an InAs 0.65 P 0.35 6 nm thick Single Quantum Well (SQW) confined between 120 nm thick InP barriers. In this case, the final thickness of the reported die with a SQW is reduced to 256 nm. (a) (b) 300 µm 300 µm Figure 8: SEM image of 360 µm thick InP die bonded on Silicon substrate (a) and of thinned down to 20 µm die after bonding (b). The reported optoelectronic devices kept the optical properties as showed on the Figure 9 which presents the photoluminescence (PL) cartography at 1.514 µm from the reported die after chemical back etching of the initial substrate and etch-stop layer. The intensity is homogenous on the whole die. The peak intensity at 1.514 µm and the Full Width at Half Maximum (FWHM) did not change after all the technological process. So these technological procedures do not induce any significant strain or stress in the reported heterostructure.
(a) (b) [a.u.] [0.353] [2.569] [4.784] Figure 9: Optical image of a 256 nm thick InP die containing an InAsP quantum well bonded on a silicon substrate (a) and its PL cartography (b). As mentioned above, the bonding is reinforced at 200 C during several hours. When the reported dies are thick, the thermal treatment at higher temperature could favor debonding due to the stress arising from differences between thermal expansion coefficients of silicon and InP. However, when the dies are thin, the stress induced by a thermal treatment is lower and the annealing at higher temperature is possible. Depending on the operating temperature an additional protection of exposed InP surface can be needed in order to prevent the InP from Phosphorous desorption. Using the same technology, we reported the 200 µm thick InP dies with QW on the optical layer transferred on CMOS processed 200 mm of diameter wafer [12]. The optical layer is composed of silicon waveguides. The top oxidized surface was cleaned. Then, InP dies were placed on specific spots. Figure 1a show an optical view from an InP die bonded on CMOS wafer with an optical layer and Figure 1b an in-plane view presenting the optical waveguides on a top of a CMOS wafer. (a) InP (b) CMOS Figure 10: 1.2 x 1.2 mm², 200 µm thick InP die bonded on optical layer on a CMOS substrate (a) and optical waveguides on CMOS (b) CONCLUSION In order to integrate optical functions within microelectronic development, technological platform compatible with Back-End processes is an attractive solution. Waveguides materials presenting a medium to high index contrast with low intrinsic loss were developed. With medium index contrast (0.3 to 0.5) with silicon dioxide, PECVD silicon nitride
technology exhibits very low optical losses @1.3µm with already compact components, i.e. submicronic waveguides of 2.5dB/cm and equilibrated MMI. However, its optical characteristics are less interesting @1.55µm. A one to sixteen distribution network was demonstrated with good output equilibrium. To miniaturize even more, amorphous silicon represents an interesting alternative to SOI architecture and preliminary results are encouraging. Aiming the introduction of efficient active components on CMOS, we reported 200 µm thick InP dies with epitaxial stack at specific spots of a 200 mm CMOS processed wafer with an optical layer. The optical layer is composed of silicon waveguides and silicon dioxide cladding. Future work will focus on the 200mm fabrication of InP components coupled to the underneath waveguides. AKNOWLEDGMENT This work is supported by the European community projects FP6-2002-IST-1-002131-PICMOS and FP6-RII3-CT- 2004-50623 MNTEurope.. REFERENCES [1] I. O'Connor, F. Gaffiot, "On-chip optical interconnect for low-power", in Ultra Low-Power Electronics and Design, ed. E. Macii, Kluwer, 2004 [2] N. Al-Ababneh, M. Testorf, Optics Communications,Volume 242, Issues 4-6, 8 December 2004, P 393-400 [3] Y.A Vlasov, S.J. McNab, Optics Express,.Vol 12, N 8 (2004) [4] M. Kostrzewa, L. Di Cioccio, M. Zussy, J. C. Roussin, J. M. Fedeli, N. Kernevez, P. Regreny, Ch.Lagahe- Blanchard, B. Aspar, InP dies transferred onto silicon substrate for optical interconnects application, Sensors and Actuators, submitted, 2005 [5] Zhang et al. Material Letters, 12 (1991) 63-66 [6] Worhoff and al. Sensors and actuators 74 (1999) 9-12 [7] L.Liao Low loss Polysilicon Waveguides for silicon Optics MIT report(1995) [8] Q.-Y. Tong, U. Gösele, Semiconductor Wafer Bonding, The Electrochemical Society Series, INC, Pennington, New Jersey, 1999 [9] U. Gösele, Q.-Y. Tong, A. Schumacher, G. Krauter, M. Reiche, A. Plößl, P. Kopperschmidt, T.-H. Lee, W.-J. Kim, Wafer Bonding for Microsystems Technologies, Sensor and Actuators 74, 161-168, 1999 [10] R. Stengl, T. Tan, U. Gosele, A Model for the Silicon Wafer Bonding Process, Jpn J. Appl. Phys. 28, 1735, 1989 [11] U. Gösele, Y. Blum, G. Kästner, P. Kopperschmidt, G. Kräuter, R. Scholz, A. Schumacher, St. Senz, Q.-Y. Tong, L.-J. Huang, Y.- L. Chao, T. H. Lee, Fundamental Issues In Wafer Bonding, J. Vac. Sci; Technol. A17 (4), Jul/Aug 1999 [12] M. Kostrzewa, P. Regreny, M. P. Besland, J. L. Leclercq, G. Grenet, P. Rojo-Romeo, G. Hollinger, E. Jalaguier, P. Perreau, H. Moriceau, O. Marty, High Quality Epitaxial Growth on New InP/Si Substrate, IPRM 2003, Santa Barbara, USA 2003 [13] M. Kostrzewa, L. Di Cioccio, J. M. Fedeli, M. Zussy, P. Regreny, J. C. Roussin, N. Kernevez, Die-to-Wafer molecular bonding for optical interconnects and packaging, EMPC 2005, June 12-15, Brugge, Belgium 2005