AN Handling and processing of sawn wafers on UV dicing tape. Document information. Sawn wafers, UV dicing tape, handling and processing

Similar documents
LA WW40WP4. Premium Edition Warm White 40 mil

LA WW40WP6. Premium Edition Warm White 40 mil

LA YG12WP5. Premium Edition Yellowish Green 12 mil

LA PD120HP1. Premium Edition Standard PIN photodiode 120 mil

AN Recommendations for PCB assembly of DSN1006. Document information

Recent Advances in Die Attach Film

AN Recommendations for PCB assembly of DSN Document information

TSSOP16; Reel pack, SMD, 13" Q4/T2 180 deg product orientation Orderable part number ending, 128 or HP Ordering code (12NC) ending 128.

Wafer Level Molded DDFN Package Project Duane Wilcoxen

SL3 ICS General description UCODE EPC G2

Enabling Technology in Thin Wafer Dicing

High Efficiency 40 mil ThinGaN LED (455nm) Lead (Pb) Free Product - RoHS Compliant ODB40RG

High Efficiency 40 mil ThinGaN LED (525 nm) Lead (Pb) Free Product - RoHS Compliant ODT40RG

High Efficiency 40 mil Infrared Thinfilm LED (940 nm) Lead (Pb) Free Product - RoHS Compliant F3487U. Version.0

VLSI Design and Simulation

Technical Note. Micron Wire-Bonding Techniques. Overview. Wire Bonding Basics. TN-29-24: Micron Wire-Bonding Techniques Overview

Customizing Processes for Hermetic Assembly Of Devices Designed for Plastic Packages (1 of 3)

CX Thin Fil s. Resistors Attenuators Thin-Film Products Thin-Film Services. ISO 9001:2008 RoHS/REACH Compliant ITAR Compliant

Die Attach Materials. Die Attach G, TECH. 2U. TECHNICAL R&D DIV.

Customer Guidelines for AMD Microprocessor Returns. May 28 th

This procedure shall apply to all microcircuit elements and semiconductors as follows:

3M Thermal Management Solutions for LED Assembly

Test Flow for Advanced Packages (2.5D/SLIM/3D)

Challenges of Fan-Out WLP and Solution Alternatives John Almiranez

Mixed Attachment Technology Studies in RF & Optoelectronic Packages Requiring High Accuracy Placement

AN Contact reader ICs - TDA product support packages. Document information

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Background Statement for SEMI Draft Document 4522 NEW DOCUMENT: SPECIFICATION FOR PLASTIC TAPE FRAME FOR 300 mm WAFER

Material based challenge and study of 2.1, 2.5 and 3D integration

AN QN908x 32k RCO Calibration. Document information

Development of System in Package

JOINT INDUSTRY STANDARD

Features. = +25 C, Vdd = 2V* Parameter Min. Typ. Max. Units Frequency Range GHz Gain db

Selection and Application of Board Level Underfill Materials

Microelectronic Materials CATALOG

A novel pick-and-place process for ultra-thin chips on flexible smart systems Thomas Meissner (Hahn-Schickard)

Chips Face-up Panelization Approach For Fan-out Packaging

Thin Wafers Bonding & Processing

FOR OFFICIAL USE ONLY

Package Mounting Guide SOP/QFP

TN0873 Technical note

Beam Leads. Spider bonding, a precursor of TAB with all-metal tape

Molding materials performances experimental study for the 3D interposer scheme

Microelectronic Materials. Catalog

SL3S General description. 2. Features and benefits UCODE Key features. Rev May

Package Mounting Guide BGA

OUR SPECIALTY OUR SCOPE. We specialize in the design and manufacture of thick-film hybrid microcircuits and custom packagings.

High Temperature (245 C) Thick Film Chip Resistor

Nanium Overview. Company Presentation

Flip Chip - Integrated In A Standard SMT Process

CAUTION: ELECTROSTATIC DISCHARGE SENSITIVE PART

Asia/Pacific Semiconductor Packaging and Assembly Facilities, 2002 (Executive Summary) Executive Summary

Release of Cu-wire bonding for the DHVQFN packages in ASEN and ATBK (phase 8)

High Stability Resistor Chips (< 0.25 % at Pn at 70 C during 1000 h) Thick Film Technology

Fraunhofer IZM Bump Bonding and Electronic Packaging

Features. = +25 C, 50 Ohm System

DUST FREE ACTIVE Total Home Air Purification

New Technology for High-Density LSI Mounting in Consumer Products

BGA Package Underfilm for Autoplacement. Jan Danvir Tom Klosowiak

High Current Thermal Fuse

HYPRES. Hypres MCM Process Design Rules 04/12/2016

ATSC Automotive Grade Silicon Capacitors

Automotive Electronics Council Component Technical Committee

5. Packaging Technologies Trends

Murata Silicon Capacitors - LPSC 100µm NiAu finishing Assembly by Soldering. Table of Contents

The 3D Silicon Leader. Company Presentation. SMTA Houston, 14th March 2013

FOR OFFICIAL USE ONLY

Murata Silicon Capacitors - XTSC 400µm NiAu finishing Assembly by Soldering High temperature silicon capacitor. Table of Contents

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

Wire Bonding Integrity Assessment for Combined Extreme Environments

1997 Digital Signal Processing Solutions

For MIL-STD-981 inductors or transformers, Class B lot control applies, see Para. 5.1 for requirements.

High Temperature (245 C) Thick Film Chip Resistor

Development of gold to gold interconnection flip chip bonding for chip on suspension assemblies

PRODUCT/PROCESS CHANGE NOTIFICATION

In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below.

Anisotropic Conductive Films (ACFs)

Background Statement for SEMI Draft Document 5485 NEW STANDARD: GUIDE FOR INCOMING/OUTGOING QUALITY CONTROL AND TESTING FLOWFOR 3DS-IC PRODUCTS

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V RRM

RH1078M, DICE Micropower, Dual, Single Supply Precision Op Amp

Features. = +25 C, 50 Ohm System

Features. = +25 C, 50 Ohm System

XBSC/UBDC/UBSC/BBSC/ULSC 100 µm & 400 µm - Assembly by soldering

Gold to gold thermosonic bonding Characterization of bonding parameters

High junction temperature capability Low leakage current Negligible switching losses Optimised design to give low V F and high T j(max)

RH1083CK, 7.5A Low Dropout Positive Adjustable Regulator Dice

White Paper 0.3mm Pitch Chip Scale Packages: Changes and Challenges

Table 1. Quick reference data Symbol Parameter Conditions Min Typ Max Unit V RRM

3M Anisotropic Conductive Film 5363

PCB Mount VIA Soldering Guidelines

Cree MB290 LEDs CxxxMB290-Sxxxx Datasheet

XTSC SiCap 400µm - NiAu finishing - Assembly by soldering

(2) (3) (4) (2) Lot number : 1 figure of the ends of a manufacture year (A.D.)

HTSC SiCap 400µm - NiAu finishing - Assembly by soldering

FOR OFFICIAL USE ONLY LINEAR TECHNOLOGY CORPORATION MILPITAS, CALIFORNIA ORIG DSGN ENGR RH117H AND RH117K POSITIVE ADJUSTABLE REGULATOR DICE

FORM HEADWALL. FORM HEADWALL (floating) (floating) Installation Manual

CHAPTER 11 DIE AND WAFER SHIPMENTS. Introduction. Product Carrier Guide for Die and Wafers. Carrier Designs for Singulated Die.

Advancements In Packaging Technology Driven By Global Market Return. M. G. Todd

AN1235 Application note

Transcription:

Handling and processing of sawn wafers on UV dicing tape Rev. 2.0 13 January 2009 Application note Document information Info Keywords Abstract Content Sawn wafers, UV dicing tape, handling and processing This application note gives hints and recommendations regarding correct handling and processing of sawn wafers mounted on irradiated UV dicing tape. The recommendations are based on NXP internal assembly experience and must be seen as guideline only. In addition to processing recommendations this document presents the results of various tests which have been performed by NXP in order to ensure damage-free shipment of the delivery type sawn wafer on FFC with irradiated UV dicing tape.

Revision history Rev Date Description 2.0 2009-01-13 Section 2.3.1: recommendation regarding LASER diced wafers added Chapter 3 updated: drop test results with LASER diced wafers added; typo regarding Lintec foil type corrected Document transferred to corporate NXP template 1.0 2005-02-11 Initial version Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Application note Rev. 2.0 13 January 2009 2 of 9

1. Introduction This application note gives hints and recommendations regarding correct handling and processing of sawn wafers mounted on irradiated UV dicing tape according the General Specification for 8 Wafer on UV-tape. The processing recommendations are based on NXP internal assembly experience and must be seen as guideline only. Process fine tuning and optimization remains in the full responsibility of the customer. In addition to processing recommendations this document presents the results of various tests which have been performed by NXP in order to ensure damage- and yield loss-free shipment of the delivery type sawn wafer on FFC with irradiated UV dicing tape. Application note Rev. 2.0 13 January 2009 3 of 9

2. Handling and processing recommendations 2.1 Differences between irradiated UV dicing tape and conventional tape The adhesion strength between irradiated UV dicing tape and silicon is approximately three times lower compared to non UV dicing tape (i.e. sticky tape or blue tape ). Furthermore irradiated UV dicing tape almost completely loses its adhesion strength to the silicon in case excessive shear forces are applied to the adhesive layer. This leads to the following important differences for the pick and place process of sawn wafers on irradiated UV dicing tape compared to conventional blue tape: No or only minimum spreading of the tape is advised at the pick and place process. This prevents loose dies prior to pick and place. Adjustment of the mechanical pick parameters (e.g. push up needle geometry, push up forces and profile) is advised in order to reflect the lower adhesion force of the irradiated UV dicing tape properly. 2.2 General recommendations Optimization of the assembly process in general (equipment adaption and accurate process parameter setting) by final product manufacturer is recommended in order to prevent mechanical stress and damage of the ICs. Ultrasonic cleaning is not permitted. ESD safe working environment and equipment is advised. 2.3 Conventional assembly 2.3.1 Die Attach Cleaning of wafer surface by gentle N 2 blow before push up is advised. No or minimum spreading of sawn wafer on FFC is advised. In case of LASER diced wafers it should additionally be ensured that the working area of the pick & place equipment is made large enough to comply with the increased wafer diameter due to die separation spreading. Any backside damage due to improper push up needle(s), force and profile has to be avoided. Even distribution of adhesive under the die is advised (100% of die area should be covered with adhesive). Adhesive type: conductive or non-conductive. Adhesive thickness: min. 10 µm (standard epoxy material). 2.3.2 Wire Bonding Preferable process: thermosonic bonding (Au wire) No chip out under bond pad metallization is allowed. No bond closer than 2 µm to the adjacent passivation layer at the edge of the bondpad. Application note Rev. 2.0 13 January 2009 4 of 9

2.4 Flip chip assembly 2.4.1 Pick and place Cleaning of wafer surface by gentle N 2 blow before push up is advised. No or minimum spreading of sawn wafer on FFC is advised. Any backside damage due to improper push up needle(s), force and profile has to be avoided. 2.4.2 Direct chip attach assembly (DCA) Bumped dies offered by NXP Semiconductors can be assembled by flip chip processes using ACF (anisotropic conductive film), ACP (anisotropic conductive paste), nonconductive and conductive glues. Other compatible DCA processes are TCB (thermo compression bonding) and direct conductive paste printing. Application note Rev. 2.0 13 January 2009 5 of 9

3. Packing and shipping 3.1 Conventionally diced parts (blade dicing) 3.1.1 Shipping test program The use of the specified packing method 3322 845 08351 for customer shipment of sawn wafers on irradiated UV dicing tape has been released based on the results of the following tests and field experience: 1. Test sequences : standard drop and vibration tests according UN-D 1400. a. 3 axis vibration test (frequency 7 Hz, amplitude 5.3 mm, acceleration 1.05 g, 30 min. each axis) + drop test program 1 (7 drops, 1 m drop height). b. 3 axis vibration test + drop test program 1 + 2 hours vibration test (most critical axis). c. 3 axis vibration test + drop test program 1 + 2 2 hours vibration test (most critical axis). 2. Shipment trial of all sample material used in item 1. from Hamburg to Bangkok and back. 3. Field experience from more than 30000 sawn wafers on irradiated UV dicing tape shipped to customers and NXP production sites. 3.1.2 Results 3.1.2.1 Standard drop and vibration tests The results from the standard drop and vibration test sequences are shown in Table 1. Table 1. Missing/delaminated dies vs. total dies Die size: 1 mm 2 Die size: 0.5 mm 2 Adwill D-175 Nitto UE-111AJ Adwill D-175 Nitto UE-111AJ Test sequence a. 5/31k 3/31k 3/62k 0/62k Test sequence b. 0/31k 0/31k 1/62k 0/62k Test sequence c. 13/31k 10/31k 24/124k 3/124k 3.1.2.2 Shipment trial with drop test material No additional missing or delaminated dies were observed. 3.1.2.3 Field experience To date no complaints regarding missing or delaminated dies due to shipment received. 3.2 Laser diced parts 3.2.1 Shipping test program Test sequences : standard drop and vibration tests according UN-D 1400. a. 3 axis vibration test (frequency 7 Hz, amplitude 5.3 mm, acceleration 1.05 g, 30 min. each axis) b. Drop test program 1 (7 drops, 1 m drop height) Application note Rev. 2.0 13 January 2009 6 of 9

3.2.2 Results Table 2. Missing/delaminated dies vs. total dies Die size: 0.3 mm 2 Nitto UE-111AJ Wafer 1 Wafer 2 Test sequence a. 0/99k 0/99k Test sequence b. 0/99k 60/99k 3.3 Conclusion In case excessive vibration and/or dropping is applied to the packed material few dies may delaminate from the irradiated UV dicing tape. Under normal shipping conditions, however, no delamination was ever seen on more than 30000 shipped wafers. Therefore the risk for yield loss due to wafer shipping can be considered extremely low for sawn wafers on irradiated UV dicing tape. Application note Rev. 2.0 13 January 2009 7 of 9

4. Legal information 4.1 Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. 4.2 Disclaimers General Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Application note Rev. 2.0 13 January 2009 8 of 9

5. Contents 1. Introduction...3 2. Handling and processing recommendations...4 2.1 Differences between irradiated UV dicing tape and conventional tape...4 2.2 General recommendations...4 2.3 Conventional assembly...4 2.3.1 Die Attach...4 2.3.2 Wire Bonding...4 2.4 Flip chip assembly...5 2.4.1 Pick and place...5 2.4.2 Direct chip attach assembly (DCA)...5 3. Packing and shipping...6 3.1 Conventionally diced parts (blade dicing)...6 3.1.1 Shipping test program...6 3.1.2 Results...6 3.1.2.1 Standard drop and vibration tests...6 3.1.2.2 Shipment trial with drop test material...6 3.1.2.3 Field experience...6 3.2 Laser diced parts...6 3.2.1 Shipping test program...6 3.2.2 Results...7 3.3 Conclusion...7 4. Legal information...8 4.1 4.2 Definitions...8 Disclaimers...8 5. Contents...9 Please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'Legal information'. For more information, please visit: http://www.nxp.com For sales office addresses, email to: salesaddresses@nxp.com Date of release: 13 January 2009 Document identifier: