PRESENTED BY S.SRIKANTH REDDY Y.MARUTHI III B.tech III.B.tech Sri.prince087@gmail.com St.JOHNS COLLEGE OF ENGINEERING AND TECHNOLOGY, YERRAKOTA, YEMIGANUR, KURNOOL (Dist), ANDHRA PRADESH.
ABSTRACT VLSI fabrication augmented its aggrandizement for its insatiable demand for higher operating speeds and device packing densities. The circuits fabricated on bulk Si wafer could not satisfy these requirements. The present paper seeks to ameliorate this area through Silicon-On-Insulator (SOI) technology. It elucidates a novel technology using atomic layer cleavage, which allows SOI processing to be available for many substrate materials. It also presents various other fabrication methods for SOI technology. Using the same transistor dimensions, SOI s global dielectric isolation enables IC manufacturers to pack more die on a wafer without direct transistor scaling through reduction in the wafer area needed for the device isolation. The SOI process exploits Nano cleaving, which reduces cost and creates SOI wafers with exceptional material quality and high yield. Nano cleave is highly efficient for chipmakers, relying on standard IC fabrication technologies. This paper encompasses Nano cleave process fabrication steps in a lucid manner. It also accrues major advantages of devices built on SOI wafers. ABSTRACT AABSTRACT A
1. PREAMBLE Silicon-on-insulator (SOI) technology provides opportunities to increase transistor switching and at the same time to improve performance for low-power, batterydriven electronics. With its ability to increase device density through reduction in isolation area, SOI can postpone the need to shift to smaller scale transistors. SOI can contribute to reduced manufacturing costs by simplifying IC fabrication processes, through the elimi-nation of high-energy implantation for well doping and simplification of device isolation. SOI also provides opportunities beyond conventional semiconductor devices. SOI is a key method for fabricating Silicon-on-Anything devices, which have the potential to integrate communications, smart cards, sensors and displays with portable, low-power memory and logic devices, as in Figure 1. Figure 1. SOI technology enables major performance advances in numerous applications Using a fully-integrated, proprietary SOI manufacturing process, called NanoCleave, advanced corporations have recently begun production of SOI wafers which offers lower cost and higher wafer quality than earlier generations of SOI fabrication methods.
2. SOI ADVANTAGES The major advantage of devices built on SOI wafers are: 1) 20 to 30% higher operating speeds compared to similar devices on bulk Si 2). higher device packing density for logic and analog circuits and 3). greatly increased immunity to soft-error events generated by decay products of cosmic ray showers. Using the same transistor dimensions, SOI s global dielectric isolation enables IC manufacturers to pack more die on a wafer without direct transistor scaling, through reduction in the wafer area needed for device isolation, as shown in Figure 2. This increase in the die per wafer yield is especially valuable in logic and I/O-dominated layouts such as in system-on-a-chip (SOC) devices. In addition to speed gains in mainstream applications, the negligible current leakage and lower power requirements of SOI-based chips can dramatically improve the performance of battery-powered communication and computing devices for mobile electronics.
3. SOI: AN EMERGING MARKET FOR GIGAHERTZ-SPEED, LOW POWER DEVICES The need for lower cost IC devices which operate in the Gigahertz frequency range used for mobile communications is driving the switch to SOI wafers. Broadband communication networks, operating on battery or solar cell power, need the low-power, small die size and global Isolation of SOI designs. The lower cost of Silicon device processing on large area wafers provides a key advantage for SOI over communication and computing devices fabricated with more exotic materials, such as GaAs. Today s standard processes fabricate transistors directly onto a bulk silicon wafer surface. These transistors operate at relatively low switching speed because large volumes of semiconductor material require more energy to turn on and off. For SOIbased processes, transistors are built on a thin silicon surface layer isolated from the wafer by a layer of oxide, and chips run 20% to 35% faster because less charge is needed to switch the transistor state. This speed gain is equivalent to the advantage gained by a full generation of device scaling on bulk-silicon. 4. MAKING SOI A PRODUCTION TECHNOLOGY Despite its many benefits, SOI s acceptance has been slowed by the high cost and low production-maturity of first-generation SOI manufacturing methods. These various methods were complex and often produced wafers of low or variable quality. Currently, there are five methods to produce commercially available SOI, based on either direct oxygen implantation or bonded layer transfer technologies, as shown in Table. The two commercial ways to fabricate SOI wafers, namely, SIMOX (separation by implantation of oxygen) and BESOI (bonded and etch-back) SOI, are quite expensive because of the long implantation time for the SIMOX process and the need to use two wafers to form a single SOI wafer in BESOI. Recently, a method called SMART-CUT or ion cut was proposed by SOITEC, making use of wafer cleavage after hydrogen implantation and subsequent wafer bonding. This technique is potentially cheaper than the conventional BESOI process because one of the wafers can be recycled. The materials cost of SOI can be further reduced if an alternative way can be found to reduce the time required to implant a high enough dose of oxygen (SPIMOX) or
hydrogen (ion-cutting). Plasma immersion ion implantation (PIII) is a burgeoning technique offering many applications in materials and semiconductor processing. In PIII, the sample is immersed in a plasma shroud from which ions are extracted and accelerated through a high-voltage sheath into the target. The dose rate can be as high as ions cm s which is equivalent to ten monolayers of implanted atoms per second and at least an order of magnitude higher than that of a conventional ion implanter. Since the entire wafer is implanted simultaneously, the implantation time is independent of wafer size, thereby offering an extremely attractive approach for 300-mm
wafers. The use of PIII to synthesize SOI materials has been investigated, and the results are very encouraging. In spite of the tremendous potential, the development of commercial PIII instrumentation has not caught up. The newest of these technologies, NanoCleave, represents a unique, second generation, approach that offers a streamlined process flow and the potential for significantly lower SOI manufacturing costs. One of the earlier barriers to the use of SOI for mainstream chipmaking was the higher cost of SOI wafers, up to 5 times the cost of bulk silicon wafers. With advanced SOI fabrication technology, such as NanoCleave, the cost of SOI wafers can be substantially reduced. It is expected that the price of 200 mm SOI wafers, which is currently in the range of $500 per wafer, will drop by as much as 40% in the coming year as production volumes and consumption of SOI wafers increase. 5. THE NANOCLEAVE PROCESS SOI process uses NanoCleave and other novel manufacturing methods that reduce cost and create SOI wafers with exceptional material quality and high yield. Unlike most other competing technologies, the critical layer transfer and wafer bonding steps are accomplished at room temperature. NanoCleave is highly efficient for chipmakers, relying on standard IC fabrication technologies for most of the process steps, supplemented with fully automated tools for the critical wafer bonding and separation steps. Surface roughness of the finished SOI wafer exhibits RMS roughness below 1nm, which is already within specification for use by most IC processes. As a measure of its process simplicity, this is accomplished without the CMP and post-cmp damage removal steps required in earlier generation bonded SOI wafer fabrication processes. 6. NANOCLEAVE PROCESS FABRICATION STEPS SOI layer transfer techniques involve creating a dual-layer of device-silicon and an insulator layer) (the Buried OXide or BOX ) grown on a donor wafer and bonded to a handle wafer. These silicon and buried oxide layers are then separated ( cleaved ) from the donor wafer, producing a finished SOI wafer. The NanoCleave process greatly
simplifies this layering sequence compared to earlier processes, resulting in the potential for major cost reductions in SOI production, Figure 3. FIGURE 3. THE NANO CLEAVE PROCESS FLOW The NanoCleave process includes four main steps: 1. A donor wafer is formed by forming a high-quality silicon layer (which will become the device layer in the final SOI wafer). A cleave plane situated beneath this layer acts as a guide for the cleave front during the separation process. The silicon layer does not contain the yield-limiting crystal defects and oxygen
precipitates present in bulk silicon grown by CZ methods. A thermal oxide is grown on the silicon layer that becomes part of the buried oxide layer in the finished SOI wafer, Figure 4. The thermal oxide growth process produces a buried oxide layer that is free of pinholes and silicon inclusions. The NanoCleave silicon/oxide interface, Figure 5, has the low interface trap and fixed charge densities that are required to control the signal frequency dependence of transistor threshold voltage. 2. The NanoCleave process uses implantation in combination with other proprietary process steps to promote low-energy cleaving along the desired wafer separation plane. A standard beam line implanter is presently used for 200mm production in the SiGen pilot line. However, looking ahead towards the needs of high-volume 200mm and 300 mm SOI wafer production, the implant step can be more cost-effectively performed by Plasma Immersion Ion Implantation (PIII) using tools, such as the SiGen PIII implanter. 3. Plasma treatment of the wafer surfaces enables the donor wafer to be bonded to a bare or oxidized handle wafer with a bond interface far stronger than the cleave plane. Because the device silicon layer is separated by the buried oxide layer, a handle wafer with considerably relaxed electrical and chemical specifications, and therefore lower cost, can be used in this process.
4. Using Controlled Cleave Process (CCP), the donor and handle are separated at room temperature. Using a controlled propagation along a single cleave front, as in Figure 6, this atomic layer cleaving process results in an as-cleaved surface roughness less than 1nm (typically 2-5 Angstroms). This is an order of magnitude smoother than the 80 Angstroms of typical hydrogen-induced thermal cleaving, Figure 7. Such a smooth surface is acceptable for many IC applications with no additional surface polishing. Figure 7 AFM images of as-cleaved surfaces of NanoCleave and Hydrogeninduced thermal separation methods
The edge of the SOI layer has a smooth and regular character without the need for edge polishing, Figure 8. 7. USING A STANDARD TOOL SET FOR SOI The fabrication sequence has 20-40% fewer steps than other bonded wafer SOI fabrication methods and uses widely available IC fabrication tools, such as ion implantation, thermal furnace and wet benches, for most of the process steps. The key wafer bonding and atomic layer cleaving steps are done by fully-automated tools which have been developed to be easily integrated into a high-volume SOI wafer fabrication environment. 8. CONCLUSION The advances in SOI wafer manufacturing technology are lowering the cost of SOI wafers through a simpler, more cost-effective process flow. The NanoCleave process accomplishes this productivity breakthrough by using conventional semiconductor manufacturing tools for most of the process flow and by accomplishing the wafer bonding and cleaving steps at room temperature. The as-cleaved SOI wafer surface is smooth to sub-nanometer dimensions and can be used directly without any post-cleave mechanical polishing or edge treatment.
REFERENCES: 1. Se-Jeong Park, Jeong-Su Kim, Ramchan Woo, Se-Joong Lee,Kang-Min Lee, Tae- Hum Yang, Jin-Yong Jung and Hoi-Jun Yoo, A Reconfigurable Multilevel ParallelGraphics Memory with 75GB/s Parallel Cache Replacement Bandwidth, Symposium on VLSI Circuits 2001, C21p3, in press, Jun. 2001. 2. Sean P.Cunningham and J. George Shanthikumar, Empirical Results on the Relationship Between Die Yield and Cycle Time in Semiconductor Wafer Fabrication, In IEEE Transactions on Semiconductor Manufacturing, 9: 273-277, 1996. 3. J.Kook, et al, A Low Power Reconfigurable I/O DRAM Macro with Single Bit line Writing Scheme, 26th European Solid-State Circuits Conference, pp.384-387,sept., 2000. 4. T. Nishikawa, et al., A 60 MHz 240 mw MEPG-4 Video-Phone LSI with 16 Mb Embedded DRAM, ISSCC Digest of Technical Papers, pages 230-231, 2000.