Deep Silicon Etching An Enabling Technology for Wireless Systems Segment By Carson Ogilvie and Joel Goodrich Commercial Product Solutions Abstract The recent installation of a new etch tool, the Surface Technology System s High Rate Module, had given the Silicon semiconductor group the opportunity to simplify processing steps in the HMIC and CermaChip product lines for trench isolation. Some of the other immediate advantages include etch separation of plated heat sink (PHS) varactors, GaN on silicon backside via, perforated silicon substrates, and back via isolation etch. This paper will describe the observed benefits of using this technology over WSS s previous processing options. Introduction The commercial products group have several product lines that use a glass isolation process. This process involves removing background silicon and then filling the voids with glass. In order to accomplish this process, different methods have been used including orientation dependent etching (ODE) chemical etch, and Reactive Ion Etching (RIE). While these methods could adequately perform the task, they had their drawbacks in that the etch depth and mesa geometry were tied together. They also required a NiCr film hard mask to stand up to the etchants. A newer technology emerged that radically changed the etch characteristics and could allow a vertical etch profile. This process, developed by Bosch, used alternating sequences of depositing a thin film of polymer, followed by a short etch step. This provided the sidewall passivation necessary to prevent undercutting of the feature while still allowing sufficient etch power to get through the built-up polymer as the etch progressed. This paper will discuss how this new technology has simplified manufacturing of these glass isolated features and the possibilities for future technology development. Commercial Product Solutions purchased a Bosch process Deep Silicon Etcher from Surface Technolgy Systems and completed installation and qualification in May 2007. This High Rate Module (HRM) unit has been used to simplify the processing of several product flows in the IPBU wafer processing fab. Cermachip Process The CermaChip process that is still processed in the Anatech etcher requires a NiCr/nitride hardmask to withstand the etch process. Since it is a simple parallel plate reactor, the etch profile is mostly isotropic which means that the distance
etched vertically is almost the same as the distance etched horizontally. This gives rise to the dependence of the depth and diameter measurements. Another issue with the Anatech etcher is the etch rate dependency on dopant concentration in the silicon. The cross-section in Fig. 1-1 shows a nail head feature due to the P-type dopant at the surface of the wafer etching at a slower rate than the underlying intrinsic layer. This leads to an estimate of the mesa diameter because the undercut feature is the true measurement seen at electrical test. The Anatech etcher holds 4 wafers per run and must have all positions filled in order to maintain the constant exposed area for loading effects. The cross-pallet uniformity is ~20%. In order to minimize the depth and diameter variation, the operators are required to open the chamber after 30 minutes and rotate the wafers to different pockets. This process is repeated every 30 minutes until the etch depth is achieved. Once the etch is completed, the hardmask layers need to be stripped off before the glassing procedure can be performed. These extra strip processes add time and operator costs to the price of the device. Fig. 1-1 Anatech etched CermaChip shows nailhead top The HRM Bosch process uses positive resist for the etch mask which means that there is no need to deposit nitride or NiCr, and also no need to etch it, then strip the remaining film after the pedestal etch. This simplified process saves processing steps and resources. The system is a single-wafer etch system with cassette-to-cassette handling. The operator loads a cassette of wafers onto the load station, selects the recipe, starts the sequence, and then comes back when the cassette is complete. Etch rate uniformity is better than 10% across wafer and <2% wafer-to-wafer across a cassette. Etch rate is 4.5 to 12 um/min depending upon open area to be etched.
The STS HRM provides vertical profiles which de-couples the Depth/diameter dependency. This allows us to stop measuring the diameter of the pedestal because the photo resist pattern is exactly transferred into the etched feature. The anisotropic etch also eliminates the dopant concentration etch rate variation and undercutting seen in the Anatech etch process. Fig. 1-2 STS HRM etched 3KV PIN Pedestal HMIC Pedestal Etch HMIC pedestal etch was originally done using ODE chemical wet etch solutions. While wet chemistry is very selective, the isotropic etch requires that the pedestals be placed far enough apart so that they will be isolated in the final device. The ODE etch is very dependent upon bath conditions and if it is not mixed properly, will generate pyramid defects on the wafer.
Fig. 2-1 ODE etched HMIC Pedestals Fig. 2-2 ODE etched pedestal with LPCVD nitride hardmask
Fig. 2-3 ODE etched HMIC pedestals with pyramid defects. Again, the HRM process simplifies the process by being vertically etched. The diameter is again based on photo patterning rather than etch depth. This allows closer spacing of the pedestals and the depth only has to be deep enough to allow glassing defects to be below the final device thickness. HRM etched wafers provide near-vertical profiles with etch rates >4.5 um/min.
Fig. 2-4 Vertical HMIC Pedestal etch in HRM Fig. 2-5 Cross-section of HRM vertically etched Silicon Pedestal. CSV Separation Etch Most devices can be separated by sawing or scribing along a defined street. Some devices, however, can have a greater packing density on the wafer by
interspersing them so that there isn t a straight street to saw or scribe. These devices require mounting on a backing substrate and then separate them by etching through the excess silicon. The separated pieces are then collected in a bottle after dismounting. These varactor diodes are stacked together in the final package and had electrical failures due to several issues. Recent experiments showed that pulling the gold back from the edge of the silicon mesa increased the yield substantially. The problem with separation etching in the Anatech system, like the previous examples of CermaChip and HMIC devices, is that it causes undercutting of the plated Au bump. By switching to the HRM for separation etch, the profile of the silicon mesa is preserved. Fig. 3-1 Anatech Etched Separation of CSV017 device
Fig. 3-2 HRM Separation etch of CSV018 Fig. 3-3 HRM vertical sidewall maintains mesa profile
Fig. 3-4 Edge of CSV018 mesa. GaN on Silicon Back Via Etching GaN on silicon back vias require near-vertical sidewalls to maintain geometry constraints but they also need a slight positive slope for sputtered metal deposition (to prevent voids in the metal). The HRM is able to produce the tapered sidewall and still have aspect ratios >4:1. This will allow the designers to shrink the footprint necessary for back vias. Fig. 4-1 GaN Back side silicon via etch test wafer
Fig. 4-2 GaN on Silicon device with back via. Debris in the via is from SEM sample preparation. HMIC Cavity Isolation Etch. Backside cavity etch is currently performed in a wet etch bath using 6-1-1 Nitric:Hydrofluoric:Acetic acid solution. This process allows 2 wafers to be etched at a time and the operator must continuously agitate the wafers in the solution the entire time. The process is very operator dependent and suffers from wetability issues which result in extremely non-uniform etch patterns. The bath solution also deteriorates after 20 wafers and a new bath must be made up. This process was transferred to the HRM which now etches uniformly across the wafer, requires minimal operator time (loading, selecting the recipe, unloading and inspection) and is repeatable from lot to lot.
Fig. 5-1 HRM Cavity etch Conclusions Since the installation of this new etcher, we have demonstrated process improvements by reducing the number of steps required to produce silicon mesa structures (NiCr elimination), defect reduction by switching from ODE etch, improved cavity etch uniformity, improved yield for CSV separation process, and new product development with GaN on silicon back vias. While some of this work had been done previously by paying an outside vendor to complete the etch process, having the toolset in-house allows WSS more opportunities to develop novel processes to meet next generation products. To date, the Six Sigma cost avoidance since the tool was installed in May 2007 is calculated at $834,000 based on the price paid to the outside vendor for each wafer processed. Acknowledgements Many thanks to Mark Surgent, Peggy Barter, Todd Dixon, Mark Buliszak, and Joel Goodrich for their knowledge, suggestions, and support during the development and installation of the STS HRM etch processes.