EE 457 : Multilayer Devices

March 1, 2010 EE 457 : Multilayer Devices by prepared for: Prof. K. Westra M. Mohammed

EE 457: Multilayer Devices Objectives...1 Process Flow...1 1.Cleaning...1 2.Thermal Oxidation...1 3.Aluminum Sputtering...1 4.Apply Photoresist...1 5.Expose Photoresist...1 6.Develop Photoresist...2 7.Etch Aluminum...2 8.Remove Photoresist...2 9.Deposit Silicon Nitride...2 10.Apply HMDS...2 11.Apply Photoresist...2 12.Align and Expose Wafer...2 13.Develop Photoresist...2 14.Etch Silicon Nitride...3 15.Remove Photoresist...3 16.Aluminum Sputtering...3 17.Apply Photoresist, Align Wafer, Expose, and Develop...3 18.Etch Aluminum...3 Test Results and Discussion...3 Large Serpentine Resistor...4 Electrical Measurements...4 Large Inductor...5 Large Kelvin Cross...5 Small Greek Cross...6 Large Via Chain...7 Conclusions...8 Bibliography...1

1 Objectives The goal of this project was to go through the major processes involved in fabricating a standard 3-layer microelectronic wafer, inspecting features in every step and testing its post-production electrical properties. 9 blocks of 12 electrical test features and 8 process evaluation features were constructed on a 4-inch silicon wafer. The base insulator is silicon oxide, the metal layers, including interconnects, are aluminum, and the interconnect insulator silicon nitride. Process Flow The first three steps were carried out by the lab technicians. 1. Cleaning The wafers were purchased polished, but needed to be thoroughly cleaned using hot piranha solution1. It is a strong oxidizer, capable of reacting (removing) most organic matter, and not to be handled by untrained students. This also partially oxidizes and hydroxylates the silicon surface, making it more hydrophilic, which is helpful for the next stage. 2. Thermal Oxidation Approximately 300 nm of silicon dioxide is then grown on the surface of the water in a wet thermal oxidation process2. Though technological methods exist to measure and predict the current thickness of the oxide during the baking process, its colour reveals the same information to the accuracy required for this project. The optical properties of thin films, specifically its effective refractive index, changes with thickness, resulting in changes in interfering wave frequencies (different colours)3[1]. 3. Aluminum Sputtering The final step performed by the Nanofab technicians is sputtering about 80 nm of aluminum onto the insulator. The actual thickness ended up being 140 nm. During the first lab, the first photoresist mask was applied to the aluminum wafer, developed, then etched. 4. Apply Photoresist HPR 504, a positive broadband photoresist, was spin-coated onto the aluminum toplayer at 500 rpm for 10 seconds, then 4000 rpm for 40 seconds, as per the manufacturerʼs specifications[2], resulting in a film thickness of approximately 1.5 µm. It was then baked on a hot plate at 115 C for 90 seconds. Afterwards, it is left for about 15 minutes to allow rehydration, an important ingredient for the chemical process in the next step. 5. Expose Photoresist Using the multi-functional workstation Oscar, The wafer was roughly aligned with its flat towards the user, but, since there are yet not alignment marks, excessive straightening was not necessary. After putting the mask in place and securing the wafer to it with a vacuum, a broadband exposure light is activated. 3 seconds of 405 nm (50.2 1 3:1 mixture of sulphuric acid to hydrogen peroxide, with an activation temperature around 110 C ( hot ). 2 Bake wafers at about 900 C for 2 to 4 hours with steam from a deionized water bubbler. 3 Film thicknesses are in the same order as optical wavelengths (~400 nm to ~800 nm in air; shorter in SiO2), so the effects of interference are prominent. Roughly, wavelengths that are odd fractions of the film thickness will interfere constructively and even fractions, destructively, giving rise to amplitude division.

2 mw/cm2) and 365 nm[3] (mw/cm2) light was applied at an exposure factor4 of 0.8320 to activate the photoresist. 6. Develop Photoresist The wafer was then developed in Shipley Microposit 354 Developer, a solution of water, sodium tetraborate (decahydrate), and sodium hydroxide[4]. After 24 seconds of agitation the exposed photoresist was completely removed. The photoresist thickness was measured using the Alphastep contact profilometer at this time. 7. Etch Aluminum Nanofab stock aluminum etchant, 457 Etch 5, was used to etch the aluminum layer. It required about 5 minutes of agitation, after which the surface entirely changed to a purple colour, then washed away. 8. Remove Photoresist The remaining photoresist mask was removed with acetone, rinsed in IPA, rinsed in DI water, then dried with nitrogen. The aluminum step height was measured at this point, reaching 140 nm. Having completed the first metal layer, the lab technicians completed the next step, depositing the interconnect insulator using Plasma Enhanced Chemical Vapour Deposition (PECVD) and primed the surface with hexamethyldisilazane (HMDS). We then applied a photoresist mask to the wafer surface, developed it, and etched. 9. Deposit Silicon Nitride Silicon nitride was deposited onto the mostly-silicon oxide layer using the PECVD (Trion) machine to a thickness of 150 nm. 10. Apply HMDS HMDS was applied to the wafer automatically in the YES HMDS Oven, taking 17 minutes. 11. Apply Photoresist First, we attempted to measure the thickness of the silicon nitride layer using the Filmetrix measurement system, but did not get reliable results; the Si3N4 layer measured 193.49 nm. HPR 504 was then spin-coated and baked onto the wafer as indicated in step (4). 12. Align and Expose Wafer The mask alignment component of the alignment and exposure workstation ( Oscar ) was used to align the alignment marks on both sides of the wafer with that of the mask, as shown in Figure 1. It was then exposed for 3.2 seconds. 13. Develop Photoresist The photoresist was developed as indicated in step (6). Figure 1: 1st layer and 2nd mask alignment marks. 4 Exposure factor: A figure by which the exposure indicated for an average subject and/or processing should be multiplied to allow for non-average conditions.[3] 5 12 parts phosphoric acid (H3PO4), 1 part acetic acid, 1 part nitric acid (HNO3), and 2 parts water.

3 14. Etch Silicon Nitride Anisotropic vias and the alignment marks were etched into the silicon nitride layer was etched using a Reactive Ion Etching (RIE) process; specifically, the Trion RIE machine, using Fluorine gas. 15. Remove Photoresist The photoresist was removed, as indicated in step (8), and the insulator step height measured with the Alphastep contact profilometer to be 193.49 nm. Technicians sputtered the top aluminum layer using a Magnetron Sputtering system before our next lab session. 16. Aluminum Sputtering The Magnetron Sputtering system ionized its target material by confining a plasma cloud with magnetic fields along their surfaces (there was only 1 target in our case, but the system can a few), then accelerating the radicals towards the wafer with a DC field. The top aluminum layer was sputtered to 200 nm thick. 17. Apply Photoresist, Align Wafer, Expose, and Develop HPR 504 was spin-coated and baked onto the wafer and the alignment marks aligned, as shown in Figure 2. It was then exposed for 3.2 seconds, then developed with 354 Developer in 27 seconds, as indicated in steps (4), (5), and (6). The aluminum plus photoresist step height was characterized at this time. 18. Etch Aluminum Figure 2: The aluminum was etched in about 8 minutes and 50 1st & 2nd layer and top layer seconds with the stock etchant, as described in step (7). mask alignment marks. Test Results and Discussion Spatial measurements were taken using a Zygo optical profilometer, the Alphastep profilometer, and the Filmetrix system. Electrical measurements were taken with a voltmeter, a current source, and 4 small contact probes, using the Wentworth probing station. The only smaller version of a feature profiled was the small Greek cross. The Zygo optical profilometer operates on the principle of interference. Light in the optical regime forms interference patterns based on only material composition and thickness, which can therefor be determined. If our use of this tool were more than a demonstration, our sample would have been covered in another material, such as gold, to make it more reflective. The Alphastep is a contact profilometer. It drags a fine point at the end of an arm along a sample, registering height changes by capacitive fluctuations with the arm itself. The Filmetrix system uses what they call spectral reflectance. It also requires that the sample reflect its operating wavelengths well.

4 Large Serpentine Resistor Zygo Measurements Trace Width: 23 µm Gap: 37 µm Height: 1262 µm Figure 3. Profile and 3D-view of the large serpentine resistor, showing dimensions. 25.0000 Electrical Measurements I2 = 21.93 ma V2 = 1.647 V These measurements were used to calculate the total resistance of the structure and approximate the sheet resistance of the material, sputtered aluminum. R= V 75.0513 I RS = R/squares = R/ L/W RS = 75.0513 23 m / 11 37 m 10 1262 m 20.0000 Current [ma] I1 = 10.96 ma V1 = 0.822 V 15.0000 10.0000 5.0000 0.0000 0.5000 1.0000 1.5000 Voltage [V] Figure 4. I-V curve of the large serpentine resistor. RS = 0.1325 per square The thickness measurements obtained were not accurate, partly due to silicon nitride not being reflective enough. The top of the metal layer registered as having a linear slope from 700 nm to 1200 nm, when, in reality, it had a roughness of less than 10 nm (generous estimate from Alphastep measurements). Figure 5. Profile graph of the optical interferometer measurements, showing erroneous slope in metallization layer height. 2.0000

5 Large Inductor Zygo Measurements Width: 674 µm Trace Width: 20 µm Gap: 23 µm Electrical Measurements I1 = 10.44 ma V1 = 0.716 V I2 = 20.34 ma V2 = 1.398 V These measurements were used to calculate the bulk resistance of the structure. Figure 6. Profile and 3D view of the large inductor. R = V / I 68.657 Inductance can be approximated with the following formula: 45 0 n2 a 2 n : number of turns, L a : mean radius 22r 14a n 1 1 a = r n = 8 674 m 56 43 m = 373 m n 0 8 45 0 8 2 373 m 2 L = 17.14 H 22 674 m 14 373 m This reveals the cutoff frequency of this inductor, f = R, to be 638 khz. 2 L Large Kelvin Cross This structure is normally used to calculate contact resistance to high accuracy using a Van der Pauw method. Averaging values and reversing polarity minimizes measurement and asymmetrical material irregularity errors. No electrical measurements were taken, however. Zygo Measurements Via Height1: 732.84 nm ½-Trace Length: 426 µm First, the interfacial contact resistance, RC, is determined as the average Figure 7. Graph of height measurements along a line from the lower trace to the upper trace, across the center interconnect. 1 This is really Via Height + 2nd Metal Layer Height.

6 resistance calculated after forcing a known current between two opposite pads and measuring the voltage between the other two; the measurements are repeated and averaged with opposite polarities. The specific contact resistance is then calculated by multiplying the interfacial contact resistance by the contact area. C = RC A Small Greek Cross This structure is normally used to measure the sheet resistance to a high degree of accuracy, also employing the Hall effect in a Van der Pauw method and averaging symmetric measurements. Though no physical measurements were taken, the dimensions can be estimated, comparing sizes from photos of the Kelvin cross. Kelvin Cross Greek Cross Overlaid Images Figure 8. Graph of height measurements from the Zygo interferometer. Figure 9. 3D depiction of the Greek cross, showing contacts on the top layer and the main traces on the bottom (1st) metal layer. Using imaging software, the arm extending from the center of the feature was found to be 1.5094 times longer on the Greek cross than that on the Kelvin cross, yielding a length of 643 μm. Electrical Measurements I1 = 79.58 ma I2 = 121.9 ma I3 = 194.8 ma Figure 10. Comparison of Greek and Kelvin cross dimensions. V1 = 0.001 V V2 = 0.002 V V3 = 0.003 V The sheet resistivity was calculated as follows: V CD S = = 0.6704 per square ln 2 I AB There was considerable disagreement between the measurements, however, with individually calculated resistances of R = 0.126Ω, 0.164Ω, 0.154Ω. This amounts to errors of +10.9% and -15.0%. This could have been reduced by measuring the voltage more accurately.

7 Large Via Chain Zygo Measurements Trace Width: 22.2 Trace Gap Width: 37 Top Span Length: 84.2 Bottom Span Length: 35.2 µm µm µm µm Electrical Measurements I1A = 10.95 ma I2A = 21.42 ma V1A = 1.032 V V2A = 2.024 V I1B = 5.07 ma I2B = 12.21 ma V1B = 0.512 V V2B = 1.370 V The bulk resistance of this structure on wafers A and B were Figure 11. Diagram of measurement terms. calculated to be the following: R =V /I = { 94.369 ±0.1 %, wafer A 106.59 ±5.3 %, wafer B } The measurements for wafer A were within 1% of their mean, while those for wafer B were 5.3% away from the mean. Serpentine Via Chain Approximate 2-dimensional (not taking via height into acount) electrical path length was taken to be the same as for the serpentine resistor: 1.3027 mm. Since the trace width is about the same, the difference in resistance will be primarily due to the interconnects and process irregularities. Overlaid Images Figure 12. Comparison of the large via chain and serpentine resistor dimensions. resistance [ Ω] difference difference per with serp. [Ω] via [mω/via] serpentine 75.05 via chain A 94.37 19.32 96.59 via chain B 106.59 31.54 157.69 This difference in resistances per via would normally be compared to the contact resistance measured with the Kelvin cross, taking the latter as more accurate. Wafer B has an interconnect resistance 63% higher than that of wafer A. This is likely due to mask misalignment and poor photomask development. An example of interconnect misalignment is shown in Figure 13. Poor development leaves some photoresist where a via is supposed to go, leading to problems in the etching stages.

8 Conclusions Collaboration of the experience and results between 5 parallel processes by 5 people greatly enriched the learning experience. Processing quality ranged from optimal1 to relatively poor, with layer misalignment, large defects (larger than 15 m), and visible scum. Qualitative comparison of the effects of these defects was an effective tool for teaching the importance of certain processes. Future experiments will focus analysis on the Kelvin cross, the Greek cross, and the radiofrequency properties of energy storage devices (capacitors, inductors, junctions). The crosses are capable of precise measurements from which more in-depth process quantities can be calculated, such as majority carrier concentrations. Charge storage Figure 13. Effects of mask misdevices have a specific frequency2 response, which alignment. can be used to investigate other material properties. The experience from this lab will prove to be a key cornerstone from which we can expand our understanding of micro and nanoscale device and materials fabrication. 1 Very good mask alignment and no noticeable defects larger than 50 nm is what is meant by optimal. 2 Note that test driving signals other than the sine wave, such as the square wave, impulse, and ramp function, reveal important characteristics as well.

Bibliography [1] F. L. Pedrotti, S.J., L. S. Pedrotti, L. M. Pedrotti. Introduction to Optics -- 3rd Ed.. Pearson Prentice Hall. 2007. pp. 175-180. ISBN 0-13-149933-5. [2] (2010, Feb.). HPR 500 Positive Resist Series g-line Performance. [Online]. Available: http://www.smfl.rit.edu/pdf/productinfo/productinfo_hpr_500.pdf [3] (2010, Feb.). A Glossary of Photographic Terms: E. [Online]. Available: http://www.mir.com.my/rb/photography/glossary/terms_e.htm [4] (2010, Feb.). SecStart. [Online]. Available: http://grover.mirc.gatech.edu/data/msds/275.html