Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering Jack Kavalieros, Brian Doyle, Suman Datta, Gilbert Dewey, Mark Doczy, Ben Jin, Dan Lionberger, Matthew Metz, Willy Rachmady, Marko Radosavljevic, Uday Shah, Nancy Zelick and Robert Chau Contact Information: Robert.S.Chau@Intel.com Intel Corporation Components Research Technology Manufacturing Group June 13 th, 2006
Outline Introduction Why Tri-Gate Trigate CMOS Fabrication Trigate Physics Electrostatics Parasitics High-k / Metal Gates Carrier Transport Trigate Performance Conclusions 2
Fully Depleted Transistor Structures Planar Single Gate (FDSOI) Planar Double-Gate Non Planar Tri-Gate Gate W Si LG Gate Source Drain Gate H Si 1. Ultra thin Tsi 2. Limited to SOI 1. Wider Tsi than planar 2. Non Self-aligned 1. FIN W Si is wider than planar T Si 2. Self-Aligned gates 3. Bulk-Si or SOI Fully depleted thin-body devices improve SCE performance. Tri-Gate is the most favorable architecture for L G scaling. 3
Tri-Gate CMOS Fabrication 1. Tri-Gate Critical Dimensions 2. FIN / Channel profile engineering 3. Poly / Metal Gate / High-k Stack Etch 4. 3-D Spacer formation 5. Dual Epitaxial raised Source/Drains 4
Tri-Gate Critical Dimensions L G W eff X UD Metal Gate High - k N+ N+ L eff BOX Side Gate Top Gate High-k High-k W Si High-k Side Gate STI STI H Si I DSAT is normalized by Z T = W Si + 2*H Si Tri-gate electrostatics strongly depend on the ratio of L eff / W eff as defined by: L eff = L G 2 * X UD W eff = W Si + 2(ε Si / ε OX )*T OX 5
Tri-Gate FIN Critical Dimensions HfO 2 High-k Dielectric Near Mid-Gap Metal Gate CVD Poly W Si H Si Si FIN Z Total 6
FIN Profile Optimization W Si SOI Stringer Notched FIN Narrowing FIN W Si - Better SCEs Yield Impact - Poly / MG stringers W Si SOI Gate Bulk Si Tapered FIN FIN widens - Degraded SCEs SOI Bulk Si Gate Vertical FIN Ideal Improved SCEs No additional process complexity 7
3-D Poly/Metal Gate Stack Etch Challenge: Significant over-etch required to clear the Poly/Metal spacers on the FIN sidewall GATE Flared FIN Isolation GATE L G GATE Notched FIN GATE L G Selectivity Loss GATE FIN Damage GATE Etch Charging, Micro-Loading lead to variable L G Selectivity Loss during over-etch damages Si-FIN 8
3-D Poly/Metal Gate Stack Etch Nested FIN & Gate Array Gates 3-D Gate Profiles Vertical Gates FINs GATE FIN Isolation GATE Careful optimization of dry and wet etch modules has produced 3-D gates with no L G variation or FIN loss. 9
3-D Spacer Formation Challenge: Significant over-etch required to clear the offset spacer on the FIN sidewall for epi-raised S/D growth Spacers Gates Gate FIN FINs Gate FIN FIN Spacer Blocks Raised S/D Epi Growth which will Increase R EXT Standard Dry Spacer Over-etch Is non-uniform & leaves behind Spacer Stringers FIN Spacer Removed! For a 2:1 Gate:FIN ratio we optimize the etch to remove the FIN spacer 10
3-D Spacer Formation Gate EPI Gate Gate Epi Growth Si FIN FIN Spacer STI Si FINs Epi Growth Blocked by the FIN Spacers Spacers completely removed allowing for epitaxial raised S/D formation 11
Dual Epitaxial Raised S/D Blanket Epitaxial Si Raised S/D Growth HM Poly Selective Undercut Etch PMOS regions HM Poly In-Situ doped p + SiGe Epitaxy HM Poly Si FIN Si FIN SiGe FIN SiGe NMOS PMOS PMOS T UC Raised Si Epitaxy Undercut Etch p + SiGe EPi 12
Tri-Gate Physics 1. Trigate Electrostatics L G Scaling FIN Profile FIN Doping 2. Parasitics FIN aspect ratio R EXT Corner Device suppression 3. Carrier Transport <001> vs. <011> mobility Process Induced Strain 13
Impact of Fin Profile SS SAT [mv/decade] 180 160 140 120 100 80 Vertical Fin Tapered Fin DIBL [mv/v] 150 125 100 75 50 Vertical Fin Tapered Fin 60 0 0.5 1 1.5 2 L eff / W eff 25 0 0.5 1 1.5 2 L eff / W eff 45% FIN Taper Vertical FIN Rectangular Fin profile 24.8nm FIN 34.3nm 28.8nm improves SCEs for L G scaling: FIN 27.9nm Lowers S SAT Lowers DIBL 14
FIN Doping & L G Scaling SS SAT [mv/decade] 180 160 140 120 100 80 FIN dopant Profile Optimization DIBL [mv/v] 150 125 100 75 50 FIN dopant Profile Optimization 60 0.00 0.50 1.00 1.50 2.00 L eff / W eff 25 0.00 0.50 1.00 1.50 2.00 L eff / W eff High-k with near mid-gap workfunction metal gates enable lower dopant values for targeting V T 3-D dopant profile optimization further improves SCE s S and DIBL 15
Tri-Gate R EXT : Fin Aspect Ratio 1 Hsi = 26nm W Si Normalized R DSLin 0.9 0.8 0.7 0.6 0.5 0.4 Hsi = 30nm Hsi = 40nm Hsi = 50nm H Si STI Si FIN body STI Bulk Si substrate 0 0.02 0.04 0.06 0.08 Leff (µm) Z T = W Si + 2*H Si For a given W Si increasing H Si will lower R EXT as the larger FIN/channel x-section improves current flow 16
Equivalent Tri-Gate on Bulk and SOI 120 120 SS SAT [mv/decade] 110 100 90 80 70 Tri-Gate on Bulk Tri-Gate on SOI DIBL [mv/v] 100 80 60 40 20 Tri-Gate on Bulk Tri-Gate on SOI 60 0.01 0.02 0.03 0.04 0.05 0.06 Leff [µm] 0 0.01 0.02 0.03 0.04 0.05 0.06 Leff [µm] Trigate on Bulk-silicon and SOI substrates have similar short channel performance. 17
FIN Corner Rounding Tapered FIN R C =5.2nm Decreasing Corner Radius Vertical FIN R C =4.8nm Notched FIN R C =4.2nm Does FIN Corner impact SCE? Is Tri-Gate Corner Dominated? 18
Tri-gate a Corner Device? High FIN doping Na=1e19 cm -3 Corner Charge (electrons/um) 1E+04 1E+03 1E+02 1E+01 1E+00 1E-01 1E-02 1E-03 1E-04 1E-05 1E-06 Rc=0nm Qc/Qt Rc=2nm Qc/Qt Rc=4nm Qcorner/Qtotal 0 0.5 1 1.5 Intel TCAD V Vg G (V) (V) 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 0% % Charge in Corner Even for high FIN N A = 1x10 19 cm -3 an Rc 4nm reduces the corner transistor turn-on. Charge in Corner 19
Tri-gate a Corner Device? Perfect square corner (R C =0nm) Total Total # of Electrons (/um) (/um) 1.E+05 1.E+04 1.E+03 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 Na=1e19, Qcorner/Qtotal 3e18, Qc/Qt 1e18, Qc/Qt 3e17, Qc/Qt 1e17 Qc/Qt 1.E-05-0.5 0 0.5 1 Intel TCAD V G (V) Vg (V) 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% High-k dielectrics & mid-gap metal gates enable lower FIN doping resulting in volume inversion and hence No corner effect 0% % Charge in Corner 20
Corner Transistor Signature Poly/SiO 2 case: High N A High-k / MG case: Low N A Electron density at V G =0.2V Electron density at V G =0.2V Corner transistor is revealed at high body doping N A The Hi-k/Metal Gate enables low body doping suppressing corner transistor turn-on. 21
Tri-Gate Carrier Transport 22
NMOS Tri-Gate Mobility (Long Channel) Tri-Gate Low doping Volume inversion (110) Sidewall Universal Mobility Planar (100) Low Doping Impurity scattering Planar (100) High Doping 40% long channel mobility improvement comes from low body doping in Tri-Gate at low to moderate vertical fields Minimal mobility degradation due to <110> sidewall and surface roughness scattering 23
PMOS Long Tri-Gate Channel Mobility Tri-Gate (Long : Holes Channel) Tri-Gate Low doping Volume Inversion 110 Sidewall Universal Mobility 2X Planar (100) Low Doping Planar (100)-High Doping Low doping and the <110> sidewall surface leads to over 2x increase in hole mobility 24
Tri-Gate Performance (110) Sidewall vs. 45 Rotated (100) NMOS Tri-Gate 45 Rotated <100> Sidewall PMOS 45 Rotated <100> Sidewall Tri-Gate Tri-Gate <110> Sidewall SOI -35% SOI Tri-Gate <110> Sidewall Hybrid (45 - rotated) orientation substrates not needed for high performance CMOS Tri-Gates. 25
NMOS Tensile Nitride Film Stress Compressive S YY <100> Tensile S ZZ <110> Tensile S XX <110> Current Flow Gate Stress (MPa) 500 400 300 200 100 0-100 -200-300 -400-500 Tensile Channel Stress Compressive S XX S ZZ S YY 0 20 40 60 80 100 120 Tensile Nitride Film (nm) S XX & S YY scale with nitride thickness, S ZZ is invariant S XX tensile, S YY compressive, & S ZZ slightly tensile 26
Tri-Gate NMOS Mobility vs. Strain % Mobility Gain 30% 20% 10% 0% -10% -20% -30% Surface Normal S YY Current Direction S XX Compressive Tensile In-Plane S ZZ -500-250 0 250 500 Stress (MPa) FIN Top Normal <001> S XX : Tensile Current S YY : Compr. Normal S ZZ : Tensile In-Plane S ZZ <110> <110> S XX S YY <001> All tensile film stresses improve NMOS Tri-Gate µ. Compressive S YY stress has strongest impact on µ. 27
Tri-Gate NMOS Mobility vs. Strain % Mobility Gain. 30% 20% 10% 0% -10% -20% -30% In-Plane S YY Current Direction S XX Compressive Tensile Surface Normal S ZZ -500-250 0 250 500 Stress (MPa) FIN Sidewall Norm. <110> S XX : Tensile Current S YY : Compr. In-plane S ZZ : Tensile Normal S ZZ <110> <110> S XX S YY <001> All tensile film stresses improve NMOS Tri-Gate µ. Compressive S YY stress has strongest impact on µ. 28
Short Channel Tri-Gate NMOS Mobility vs. Film Stress Normalized Mobility. 1 0.8 0.6 0.4 0.2 0 Tensile Neutral 0.2 0.3 0.4 0.5 0.6 0.7 0.8 V G -V T [V] Tensile nitride film stress significantly enhances short channel electron µ Mobility vs. W Si (Tensile) Normalized Mobility. 1 0.9 0.8 0.7 0.6 0.5 W Si = 25nm W Si = 35nm 3 4 5 6 7 8 9 10 Q INV (10 13 cm -2 ) Tensile nitride film stress and electron µ increase as the FIN W Si decreases 29
Short Channel Tri-Gate PMOS Normalized R DS-Lin 1 0.8 0.6 0.4 0.2 0 Raised SiGe S/D Embedded SiGe S/D with Undercut Etch 0 10 20 30 40 50 60 L eff [nm] Embedded SiGe S/D Raised SiGe S/D Embedding the p + SiGe S/D regions with under-cut etch provides 40% lower R DSLIN Uniaxial compressive strain is observed in short-channel Tri-Gate 30
Short Channel Tri-Gate PMOS Ioff (A/µm) 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 Raised SiGe S/D 15% Embedded p + SiGe 0.2 0.4 0.6 0.8 1 1.2 1.4 I DSAT (ma/µm) IOFF (A/µm) 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 Embedded Raised SiGe S/D SiGe S/D 40% Raised SiGe S/D Embedded p + SiGe 0.02 0.06 0.1 0.14 0.18 0.22 I Dlin (ma/µm) Embedding the p + SiGe S/D regions with an undercut etch provides a 15% I DSAT & 40% I DLIN benefit. 31
IOFF [A/µm] 1E-04 1E-05 1E-06 1E-07 1E-08 1E-09 1E-10 Industry Leading Performance NMOS Planar 65nm IEDM 2004 30% 0.6 0.8 1 1.2 1.4 1.6 1.8 2 I DSAT [ma/µm] Tri-Gate High-k/MG IOFF (A/µm) 1E-05 Planar 65nm 1E-06 IEDM 2004 1E-07 1E-08 1E-09 1E-10 1E-11 1E-12 Integrated CMOS Tri-Gate with: PMOS 60% 1. High-k dielectrics & metal gate 2. Strain engineering for NMOS & PMOS 3. Dual epitaxial raised source/drains Tri-Gate High-k/MG 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 I DSAT (ma/µm) 32
Integrated Tri-Gate CMOS NMOS PMOS SRAM SRAM Cell IREAD (a.u.) 1.5X Planar Trigate Z Total Demonstrated functional Tri-gate SRAM cells For equivalent cell size Tri-Gate SRAM cell shows 1.5x higher cell I READ due to higher Z T =2*H Si +W Si 33
Conclusions 1. Highly scalable Tri-Gate architecture with excellent short channel effects and record performance. 2. Bulk-Si Tri-Gate demonstrates equivalent scaling and performance to SOI Tri-Gate. 3. High-k/Metal Gate, corner rounding and low doping eliminate any parasitic corner device turn-on. 4. Tri-Gate PMOS mobility shows 2x enhancement due to <110> sidewalls over <100> planar devices while NMOS is neutral. 5. Functional Tri-Gate SRAM cell demonstrated with 1.5X the cell read current due to the increase in Z Total per cell footprint. 34