Interconnects Outline Interconnect scaling issues Aluminum technology Copper technology 1 Properties of Interconnect Materials Metals Silicides Barriers Material Thin film Melting resistivity point ( C) (µ! " cm) Cu 1.7-2.0 1084 Al 2.7-3.0 660 W 8-15 3410 PtSi 28-35 1229 TiSi 2 13-16 1540 WSi 2 30-70 2165 CoSi 2 15-20 1326 NiSi 14-20 992 TiN 50-150 ~2950 Ti 3 0 W 7 0 75-200 ~2200 N+ polysilicon 500-1000 1410 2 1
Interconnect Architecture SILICIDES - Short local interconnections which have to be exposed to high temperatures and oxidizing ambients, e.g., polycide and salicide structures. REFRACTORY METALS Via plugs, future gate electrodes, local interconnections which need very high electromigration resistance. TiN, TiW Barriers, glue layers, anti reflection coatings and short local interconnections. Al, Cu - for majority of the interconnects 3 Why Aluminum? Al has been used widely in the past and is still used Low resistivity Ease of deposition, Dry etching Does not contaminate Si Ohmic contacts to Si but problem with shallow junctions Excellent adhesion to dielectrics Problems with Al Electromigration lower life time Hillocks shorts between levels Higher resistivity 4 2
Electromigration Electromigration induced hillocks and voids Electromigration due to electron wind induced diffusion of Al through grain boundaries Hillock Void void Metal Dielectric Metal SEM of hillock and voids formation due to electromigration in an Al line 5 F field + Electromigration Theory E field F scat current density is related to E field by Diffusivity is given by Therefore Meantime to failure is thus of the form of F TOTAL = F SCAT + F FIELD " qz r # E " D = µ r # = q! * kt " D " r E J = " r E = r E # D = D o e " Ea kt " D = J # qz * kt D 0 e $ MTF " e Ea kt Where qz* is effective ion charge Using Einstein s relation E a kt A phenomenological model for MTF is A MTF = " m J n e Ea kt 6 γ is the duty factor M, n are constants 3
Thermal Behavior in ICs Chip Area [cm 2 ] 9 8 7 6 5 Source: ITRS 1999 175 150 125 100 Maximum Power Dissipation [W] 4 75 50 70 90 110 130 150 170 190 Technology Node [nm] Energy dissipated is increasing as performance improves Average chip temperature is rising 7 Parametric Dependencies of Electromigration Temperature Current Density Mean time to failure is A MTF = r m J n exp! # E a $ & " kt % r is duty cycle J is current density E a is activation energy T is temperature A, m, and n are materials related constants 8 4
Electromigration-Induced Integration Limits A MTF = r m J n exp! # E a $ & " kt % EM Limited Interconnect Width r = duty cycle J =current density EM Limited Device Integration Density Ref: Yi, et al., IEEE Trans. Electron Dev., April 1995 Better packing techniques will be needed in the future to minimize the chip temperature rise 9 Electromigration: Material and Composition Materials Composition E a (ev) Failure Time (hours) Temperature (K) Materials with higher activation energy have higher resistance to electromigration Cumulative failure (%) Adding Cu to Al decreases its self diffusivity and thus increases resistance to electromigration 10 5
Electromigration: Grain Structure Top view Near bamboo structure Self Diffusion in Polycrystalline Materials D S D GB For Al grain boundary diffusion D GB >> D s or D L (D s = surface diffusion, D L = lattice diffusion) D L In a bamboo structure grain boundary diffusion is minimized 11 Effect of Post Patterning Annealing on the Grain Structure of the Film. Bamboo Structure Increasing time and/or temperature With sufficient grain boundary migration a "bamboo structure" may develop No grain boundary diffusion in the bamboo structure 12 6
Microstructural Inhomogeneities and Stress Induced Electromigration On an average the flux is uniform in a uniform grain size textured film. If the grain size is non uniform the flux will vary accordingly. spanning grain A electric current, J e - atomic flux B polygranular cluster cluster back Polygranular flux from cluster stress cluster! ss!(t 1 ) t e ns i l e Spanning Tensile stress grain metal atom depletion Compressive Spanning grain stress metal atom accumulation! o t o! (stress) t" t 1 comp. build up of stress within polygranular cluster with time due to electromigration L 13 Build up of stress within polygranular cluster with time due to electromigration.! ss!(t 1 )! o t" t 1 t o t e ns i l e! (stress) comp. L Eventually, a steady-state is approached where the forward flux is equal to the backward flux due to stress. A criterion for failure of an interconnect under electromigration conditions could be if the steady-state stress is equal to or greater than some critical stress for plastic deformation, encapsulent rupture, large void formation, etc. The maximum steady state stress would occur at x=0 or x=l 14 7
e -! ss! crit!! crit! ss!! crit! ss! ss! crit L 1 L 2 For very large line width/grain size (w/d) values, no spanning grains are present. No points of flux divergence are present and the time to failure is relatively high. As w/d decreases, some spanning grains occur. This results in divergences in the flux, causing stress to develop that can be greater than the critical stress for failure (with L > L crit for most or all of the polygranular clusters). The lines would fail and the median time to failure would decrease. As w/d decreases more, more spanning grains are present, but the lengths of the polygranular cluster regions between them are shorter, many of them shorter than L crit. The stresses that develop, which create the back fluxes and which in turn eventually stop the electromigration flux, are in many cases smaller than the critical stress. For small enough values of w/d bamboo or near-bamboo structures are present. The polygranular clusters are few, and for some lines, all the clusters are shorter than L crit and the lines will not fail by this mechanism. The MTTF thus increases dramatically. 15 Electromigration: Grain Texture Empirical relationship (for Al & Al alloys) MTF! eµ " 2 log[ I (111) I (200) ] 3 S. Vaidya et al., Thin Solid Films, Vol. 75, 253, 1981 10 7 263 238 213 188 C Time-to-Failure (sec) 10 6 10 5 10 4 (111) CVD Cu E a = 0.86 ev (200) CVD Cu E a = 0.81 ev 10 3 1.8 1.9 2.0 2.1 2.2 2.3 1/T (10-3 /K) Ref: Ryu, Loke, Nogami and Wong, IEEE IRPS 1997. 16 8
Layered Structures: Electromigration Layering with Ti reduces Electromigration Structure Al-Si Cumulative failure Layered Al-Si/Ti Time (arbitrary units) Improvements in layered films due to redundancy 17 Mechanical properties of interconnect materials Material Thermal expansion coefficient (1/ C) Elastic modulus, Y/(1- ) (MPa) Hardness (kg/mm2) Melting point ( C) Al (111) 23.1 x 10-6 1.143 x 10 5 19-22 660 Ti 8.41 x 10-6 1.699 x 10 5 81-143 1660 TiAl 3 12.3 x 10-6 - 660-750 1340 Si (100) 2.6 x 10-6 1.805 x 10 5-1412 Si (111) 2.6 x 10-6 2.290 x 10 5-1412 SiO 2 0.55 x 10-6 0.83 x 10 5 - ~1700 18 9
Layered Structures: Hillocks Pure Al Homogeneous Al/Ti Layered Al/Ti Surface profile Layering with Ti reduces hillock formation 19 Stress due to Thermal Cycling Difference in the expansion coefficients of the film and substrate causes stress in the thin film. (a) Film as-deposited (stress free). (b) Expansion of the film and substrate with increasing temperature. (c) Biaxial forces compress the Al film to the substrate dimension 20 10
Process Induced Stress Expansion of Al with respect to Si Aluminum Silicon Si pulls inward on Al at interface, inducing compressive stress on Al.! (in Al)! (in Si) Stress (MPa) 300 200 100 0-100 Elastic deformation Heating Cooling Plastic deformation Pure Al 0.64 micron thick 0 100 200 300 400 500 Temperature ( C) 21 Stress Measurement Biaxial stress in the film % E " = s ( 2 t s ' * & 1#$ s ) 6t f R f E s is Young s modulus of the substrate, v s is Poisson s ratio for the substrate, (E s /1-v s ) is the biaxial modulus of the substrate, t s is the substrate thickness, t f is the film thickness, and R f is the radius of curvature induced by the film 22 11
Hillocks Al ILD Al ILD Al Hillock formation due to compressive stress and diffusion along grain boundaries in an Al film. 23 Current Aluminum Interconnect Technology Fabrication of Vias barrier Glue W oxide 1. oxide deposition 3. barrier & W fill resist W Plug Oxide 2. via etch 4. W & barrier polish 0.5 micron 24 12
Current Aluminum Interconnect Technology Fabrication of Lines Ti Al(Cu) Ti / TiN oxide 5. metal stack deposition 7. oxide gapfill 6. metal stack etch 8. oxide polish 25 Current Aluminum Interconnect Technology Oxide W Al(Cu) - Metal 2 Al(Cu) - Metal 1 W TiN TiN Ti TiN TiN Ti Silicon N + TiSi 2 TiN (Curtsey of Motorola) 26 13
Low Dielectric Constant (Low-k) Materials Oxide Derivatives F-doped oxides (CVD) k = 3.3-3.9 C-doped oxides (SOG, CVD) k = 2.8-3.5 H-doped oxides (SOG) k = 2.5-3.3 Organics Polyimides (spin-on) k = 3.0-4.0 Aromatic polymers (spin-on) k = 2.6-3.2 Vapor-deposited parylene; parylene-f k ~ 2.7; k ~ 2.3 F-doped amorphous carbon k = 2.3-2.8 Teflon/PTFE (spin-on) k = 1.9-2.1 Highly Porous Oxides Xerogels k = 1.8-2.5 Air k = 1 27 Thermal Conductivity for Commonly Used Dielectrics Dielectric Film Thermal Conductivity (mw/ cm C) HDP CVD Oxide 12.0 PETEOS 11.5 HSQ 3.7 SOP 2.4 Polyimide 2.4 Dielectric Constant 4 3 2 1 0 35 50 70 100 130 180 Technology Node [nm] 1.2 1 0.8 0.6 0.4 0.2 0 [ W / mk ] Thermal Conductivity 28 14
Embedded Low-k Dielectric Approach MET V I A MET SiO 2 (k~4.2) LOW k SiO 2 (k~4.2) LOW k MET V I A MET Why embed Low-k dielectric only between metal lines? Mechanical strength Moisture absorption in low-k Via poisoning/compatibility with conventional dry etch and clean-up processes CMP compatibility SiO 2 (k~4.2) Source: Y. Nishi, TI Ease of integration and cost Thermal conductivity 29 SiO 2 Al Air Al Air-Gap Dielectrics Cumulative Probability 99 90 70 50 30 10 Capacitance Air-Gap Structure HDP Oxide Gapfill Electromigration K eff 30 4.5 4.0 3.5 3.0 2.5 2.0 1 6.0 9.0 12.0 15.0 18.0 21.0 24.0 Total Capacitance (pf) K eff vs. Feature Size Reduced capacitance between wires Heat carried mostly by the vias Electromogration reliability is better because of stress relexation allowed by free space Experimental Simulated 0.2 0.4 0.6 0.8 1 Line/Space (um) 15