LANDOLT-BÖRNSTEIN. Zahlenwerte und Funktionen aus Naturwissenschaften und Technik. Neue Serie. Gesamtherausgabe: K.-H. Hellwege O.

Similar documents
LANDOLT-BORNSTEIN. Zahlenwerte und Funktionen aus Naturwissenschaften und Technik. Neue Serie. Gesamtherausgabe: K.-H. Hellwege

VLSI Technology. By: Ajay Kumar Gautam

Fabrication Technology

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS

Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University

Physics and Material Science of Semiconductor Nanostructures

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

Chapter 2 Crystal Growth and Wafer Preparation

Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Chapter 3 CMOS processing technology

LANDOLT-BÖRNSTEIN. Zahlenwerte und Funktionen aus Naturwissenschaften und Technik. Neue Serie. Gesamtherausgabe: K.-H.Hellwege O.

Microelettronica. Planar Technology for Silicon Integrated Circuits Fabrication. 26/02/2017 A. Neviani - Microelettronica

LANDOLT-BÖRNSTEIN. Zahlenwerte und Funktionen aus Naturwissenschaften und Technik. Neue Serie. Gesamtherausgabe: O. Madelung

Doping and Oxidation

A discussion of crystal growth, lithography, etching, doping, and device structures is presented in

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width

Wafer (1A) Young Won Lim 4/30/13

Fabrication and Layout

IC/MEMS Fabrication - Outline. Fabrication

Crystal Growth and Wafer Fabrication. K.Sivasankaran, Assistant Professor (Senior), VLSI Division, School of Electronics Engineering, VIT

PY2N20 Material Properties and Phase Diagrams

Contents. Abbreviations and Symbols... 1 Introduction... 1

CHAPTER - 4 CMOS PROCESSING TECHNOLOGY

Microstructure of Electronic Materials. Amorphous materials. Single-Crystal Material. Professor N Cheung, U.C. Berkeley

EE6303 LINEAR INTEGRATED CIRCUITS AND APPLICATIONS 2 MARK QUESTIONS WITH ANSWERS UNIT I IC FABRICATION

Czochralski Crystal Growth

EE 5611 Introduction to Microelectronic Technologies Fall Tuesday, September 02, 2014 Lecture 01

Silicon Manufacturing

VLSI Design and Simulation

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

Agenda o Semiconductor Materials o Crystal Growth o Intrinsic Semiconductors o Extrinsic Semiconductors

Lecture 22: Integrated circuit fabrication

This Appendix discusses the main IC fabrication processes.

Chapter 3 Silicon Device Fabrication Technology

EE 5611 Introduction to Microelectronic Technologies Fall Tuesday, September 04, 2012 Lecture 01

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

VLSI Digital Systems Design

Lecture 1. Introduction to Microelectronic Technologies: The importance of multidisciplinary understanding. Reading: Chapters 1 and parts of 2

Lecture 0: Introduction

Hydrogen in Crystalline Semiconductors r

Low Power VLSI Circuits and Systems Prof. Ajit Pal Department of Computer Science and Engineering Indian Institute of Technology, Kharagpur

Instructor: Dr. M. Razaghi. Silicon Oxidation

EECS130 Integrated Circuit Devices

EE CRYSTAL GROWTH, WAFER FABRICATION AND BASIC PROPERTIES OF Si WAFERS- Chapter 3. Crystal Structure z a

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook

Lecture 2 Silicon Properties and Growth

INTEGRATED-CIRCUIT TECHNOLOGY

Chapter 2 MOS Fabrication Technology

COOPERATIVE PATENT CLASSIFICATION

Semiconductor Technology

Radiation Tolerant Isolation Technology

UT Austin, ECE Department VLSI Design 2. CMOS Fabrication, Layout Rules

CMOS VLSI Design. Introduction. All materials are from the textbook Weste and Harris, 3 rd Edition CMOS VLSI DESIGN. Introduction

Assignment Questions

The Physical Structure (NMOS)

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

VLSI. Lecture 1. Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University. Based on slides of David Money Harris

KOREA UNIVERSITY. Ch. 4 Basics of device fabrication Reference: S. M. Sze, Semiconductor Devices, ISBN Photonics Laboratory

Technology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS

PROCESS FLOW AN INSIGHT INTO CMOS FABRICATION PROCESS

Semiconductor device fabrication

Semiconductor Device Fabrication

Making of a Chip Illustrations

Technology process. It s very small world. Electronics and Microelectronics AE4B34EM. Why is the integration so beneficial?

Lect. 2: Basics of Si Technology

CRYSTAL GROWTH, WAFER FABRICATION AND BASIC PROPERTIES OF Si WAFERS- Chapter 3. Crystal Structure z a

Today s agenda (19-JAN-2010)

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

TOWARD MEMS!Instructor: Riadh W. Y. Habash

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

Thermal Evaporation. Theory

Some Aspects of Sublimation Growth of SiC Ingots p. 41 Growth of Highly Aluminum-Doped p-type 6H-SiC Single Crystals by the Modified Lely Method

EE 434 Lecture 9. IC Fabrication Technology

Review of CMOS Processing Technology

Lecture #18 Fabrication OUTLINE

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam

Halbleiter Prof. Yong Lei Prof. Thomas Hannappel

FABRICATION OF GaAs DEVICES

Mikrosensorer. Microfabrication 1

Theory and Technology of Semiconductor Fabrication

PHYSICAL ELECTRONICS(ECE3540) Brook Abegaz, Tennessee Technological University, Fall 2013

P. G. Baranov, Yu. A. Vodakov, E. N. Mokhov, M. G. Ramm, M. S. Ramm and A. D. Roenkov

Most semiconductor devices contain at least one junction between p-type and n-type material. These p-n junctions are fundamental to the performance

l Inert gas o o A.l.2 Material preparation 184 Integrated Circuit Design. Fabrication and Test

How to Make Micro/Nano Devices?

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

Chapter 2 Manufacturing Process

Summary and Scope for further study

MATERIALS. Silicon Wafers... J 04 J 01. MATERIALS / Inorganics & thin films guide

Manufacturing Technologies for MEMS and SMART SENSORS

EE 330 Lecture 8. IC Fabrication Technology Part II. - Masking - Photolithography - Deposition - Etching - Diffusion

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects

Structural changes of polycrystalline silicon layers during high temperature annealing

EE 143 FINAL EXAM NAME C. Nguyen May 10, Signature:

PROCESSING OF INTEGRATED CIRCUITS

Processing of Semiconducting Materials Prof. Pallab Banerjee Department of Material Science Indian Institute of Technology, Kharagpur

Transcription:

LANDOLT-BÖRNSTEIN Zahlenwerte und Funktionen aus Naturwissenschaften und Technik Neue Serie Gesamtherausgabe: K.-H. Hellwege O. Madelung Gruppe III: Kristall- und Festkörperphysik Band 17 Halbleiter Herausgeber: O. Madelung M. Schulz H. Weiss f Teilband c Technologie von Si, Ge und SiC W. Dietze E. Doering P. Glasow W. Langheinrich A. Ludsteck H. Mader A. Mühlbauer W. v. Münch H. Runge L. Schleicher M. Schnöller M. Schulz E. Sirtl E. Uden W. Zulehner Herausgegeben von M. Schulz H. Weiss f Springer-Verlag Berlin Heidelberg New York Tokyo 1984

Table of contents Semiconductors Subvolume c: Technology of Si, Ge and SiC (edited by M. SCHULZ H. WEISS f) A Introduction (M. SCHULZ) 1 General remarks 1 2 Frequently used Symbols 2 3 Conversion of units 5 4 Abbreviations frequently used in semiconductor technology 6 B Technology of semiconductors 6 Tetrahedrally bonded semiconductors 12 6.1 Silicon and germanium 12 6.1.1 Technological data (A. MÜHLBAUER) 12 6.1.1.0 Introduction 12 6.1.1.1 Phase diagrams and liquidus curves 12 6.1.1.2 Solubility in solid Si and Ge 13 6.1.1.3 Equilibrium distribution coefficient 14 6.1.1.4 Melt diffusion coefficient 16 6.1.1.5 Evaporation rate 16 6.1.1.6 Tetrahedral covalent radius 17 6.1.1.7 Thermophysical properties 17 6.1.1.8 Properties of liquid Si and Ge 19 References for 6.1.1 20 6.1.2 Crystal growth 23 6.1.2.1 Deposition of polycrystalline Silicon (W. DIETZE) 23 6.1.2.1.0 Introduction 23 6.1.2.1.1 Deposition technology 23 6.1.2.1.2 Processes connected to deposition 25 6.1.2.1.3 Deposition conditions 26 6.1.2.1.4 Alternative processes 26 6.1.2.2 Preparation and purification methods of Ge (W. DIETZE).... 28 6.1.2.3 Czochralski growth of Si and Ge (W. ZULEHNER) 28 6.1.2.3.0 Introduction 28 6.1.2.3.1 Czochralski pulling technique 28 6.1.2.3.2 Starting materials 32 6.1.2.3.3 Crucible materials 33 6.1.2.3.4 Heating and furnace equipment 35 6.1.2.3.5 Growth ambients 36 6.1.2.3.6 Automatic control 37 6.1.2.3.7 Recharging methods 37 6.1.2.3.8 Czochralski pulling apparatus 38 6.1.2.3.9 Impurity incorporation 39 6.1.2.3.10 Oxygen incorporation 39 6.1.2.4 Zone melting (A. MÜHLBAUER, subsection 6.1.2.4.6 P. GLASOW). 41 6.1.2.4.0 Introduction 41 6.1.2.4.1 Silicon float-zone technology 41

X Table of contents 6.1.2.4.2 Forces in a floating zone 43 6.1.2.4.3 Doping of float-zone grown crystals 43 6.1.2.4.4 Redistribution of impurities 45 6.1.2.4.5 Faceting 46 6.1.2.4.6 Growth of high purity germanium 47 6.1.2.5 Unconvendonal Si crystallization techniques (M. SCHULZ, E. SIRTL) 50 6.1.2.5.1 Directional solidification 50 6.1.2.5.2 Mould casting 51 6.1.2.5.3 Sheet growth 52 6.1.2.6 Wafer preparation (W. ZULEHNER) 54 6.1.2.6.1 Ingot preparation 54 6.1.2.6.2 Slicing, lapping, and edge rounding 55 6.1.2.6.3 Etching, polishing, wafer finishing 56 References for 6.1.2 57 6.1.3 Characterization of crystal properties 62 6.1.3.1 Properties of polycrystalline Silicon (W. DIETZE) 62 6.1.3.2 Properties of Czochralski Silicon (W. ZULEHNER) 62 6.1.3.2.1 Doping profiles 63 6.1.3.2.2 Oxygen in CZ Silicon 64 6.1.3.2.3 Impurities in CZ Silicon 66 6.1.3.2.4 Lattice defects 67 6.1.3.3 Properties of float-zone Silicon (A. MÜHLBAUER) 69 6.1.3.3.1 Doping profiling 69 6.1.3.3.2 Impurity striations 70 6.1.3.3.3 Impurities 71 6.1.3.3.4 Defects 72 6.1.3.4 Properties of high purity germanium (P. GLASOW) 73 6.1.3.4.1 Impurities in the starting material 73 6.1.3.4.2 Impurities in purified Ge 73 6.1.3.5 Diagnostic techniques (A. MÜHLBAUER, subsection 6.1.3.5.3 P. GLASOW) 77 6.1.3.5.1 Doping profiling 77 6.1.3.5.2 Impurity and defect analysis 77 6.1.3.5.3 Characterization - techniques for high purity germanium 82 References for 6.1.3 83 6.1.4 Device technology 90 6.1.4.0 Basic device structures (H. MADER, subsection 6.1.4.0.9 P. GLASOW) 90 6.1.4.0.0 Introduction 90 6.1.4.0.1 Diodes 91 6.1.4.0.2 Transistors 94 6.1.4.0.3 Bipolar transistors 101 6.1.4.0.4 MOS-transistors 101 6.1.4.0.5 Thyristors 102 6.1.4.0.6 Bipolar integrated circuits 102 6.1.4.0.7 MOS-integrated circuits 103 6.1.4.0.8 CMOS integrated circuits 104 6.1.4.0.9 Nuclear radiation detectors 104 References for 6.1.4.0 115 6.1.4.1 Diffusion (W. LANGHEINRICH under assistance of K. HABERLE). 118 6.1.4.1.0 Introduction 118

Table of contents XI 6.1.4.1.1 Diffusion coefficients 119 6.1.4.1.2 Introduction of impurities by diffusion 129 6.1.4.1.3 Properties of diffusion source material 134 6.1.4.1.4 Diffusion in the System Si0 2 /Si 135 6.1.4.1.5 Diffusion profiles 139 6.1.4.1.6 Properties of masking layers 141 6.1.4.1.7 Gettering 144 References for 6.1.4.1 145 6.1.4.2 Ion implantation (H. RUNGE) 150 6.1.4.2.0 Introduction 150 6.1.4.2.1 Depth distribution of implanted ions 150 6.1.4.2.2 Annealing 154 6.1.4.2.3 Implantation of dopants in Si 154 6.1.4.2.4 Implantation of dopants in Ge 156 6.1.4.2.5 Useful formulas 156 6.1.4.2.6 Range tables 157 6.1.4.2.7 Evaluation of ion implanted layers 166 6.1.4.2.8 Implantation apparatus 170 References for 6.1.4.2 179 6.1.4.3 Nuclear transmutation doping (M. SCHNÖLLER) 185 6.1.4.3.0 Introduction 185 6.1.4.3.1 Nuclear transmutation 185 6.1.4.3.2 Radiation defects 185 6.1.4.3.3 Side reactions of neutron irradiation 186 6.1.4.3.4 Irradiation exposure time 188 6.1.4.3.5 Selection and preparation of the starting Silicon..188 6.1.4.3.6 Neutron irradiation 188 6.1.4.3.7 Radioactivity of the irradiated Silicon 189 6.1.4.3.8 Annealing 189 References for 6.1.4.3 190 6.1.4.4 Silicon epitaxy (A. LUDSTECK) 192 6.1.4.4.1 Introduction 192 6.1.4.4.2 Basic technology 193 6.1.4.4.3 Scope of the data collection 196 6.1.4.4.4 Properties of materials used in Si epitaxy 197 6.1.4.4.5 Epitaxial Silicon growth 202 6.1.4.4.6 Doping during epitaxy 205 6.1.4.4.7 Low-pressure deposition 206 6.1.4.4.8 Defects in epitaxial layers 207 6.1.4.4.9 Evaluation of epitaxial Silicon films 207 References for 6.1.4.4 210 6.1.4.5 Fabrication of layers (subsections 6.1.4.5.0- -7, E. DOERING, 6.1.4.5.8--12 L.SCHLEICHER) 213 6.1.4.5.0 Introduction to insulating films 213 6.1.4.5.1 Thermal oxidation of Silicon 213 6.1.4.5.2 Modified thermal oxidation processes 217 6.1.4.5.3 Chemical vapour deposition 219 6.1.4.5.4 Evaporation 223 6.1.4.5.5 Sputtering 224 6.1.4.5.6 Anodization 225 6.1.4.5.7 Properties of insulating films 225 References for 6.1.4.5.0- -6.1.4.5.7 233 6.1.4.5.8 Requirements on metal layers 593 6.1.4.5.9 Metal deposition 595 6.1.4.5.10 Properties of metals used for deposition 604 6.1.4.5.11 Intrinsic properties of metal layers 610

Table of Contents 6.1.4.5.12 Residual gas dependent properties of metal layers.. 613 References for 6.1.4.5.8- -6.1.4.5.12.. 621 6.1.4.6 Litography (H. MADER) 250 6.1.4.6.0 Introduction 250 6.1.4.6.1 Resists 250 6.1.4.6.2 Photolithography 251 6.1.4.6.3 Electron-beam lithography 260 6.1.4.6.4 X-ray lithography 265 6.1.4.6.5 Ion-beam lithography 270 References for 6.1.4.6 274 6.1.4.7 Etching processes (H. MADER) 280 6.1.4.7.1 Wet etching 280 6.1.4.7.2 Wet etching techniques 281 6.1.4.7.3 Wet etching processes for pattern generation.... 281 6.1.4.7.4 Wetetchants 282 References for 6.1.4.7.1---6.1.4.7.4 301 6.1.4.7.5 Dry etching 305 6.1.4.7.6 Ion etching processes 307 6.1.4.7.7 Reactive dry etching processes 319 6.1.4.7.8 Systems used for reactive dry etching 325 6.1.4.7.9 Gases used in reactive dry etching 328 References for 6.1.4.7.5- -6.1.4.7.9 351 6.1.4.8 Final device preparation (E. UDEN) 367 6.1.4.8.1 Survey of package groups 367 6.1.4.8.2 Package components and materials 375 6.1.4.8.3 Assembly methods 387 6.1.4.8.4 Properties of packages 395 References for 6.1.4.8 398 6.2 Silicon carbide (W. v. MÜNCH) 403 6.2.0 Introduction 403 6.2.1 Technological data 404 6.2.1.1 Figures of merit for devices 404 6.2.1.2 SiC phase diagram 404 6.2.1.3 Solubility of carbon in Silicon 404 6.2.1.4 Vapour pressure of silane Compounds 404 6.2.2 Crystal growth 404 6.2.2.0 Introductory remarks 404 6.2.2.1 Melt growth 405 6.2.2.2 Vapour growth 405 6.2.2.2.1 Deposition of polycrystalline SiC 405 6.2.2.2.2 Lely technique 406 6.2.3 Characterization of crystal properties 407 6.2.3.1 Polytype verification and crystal defects 407 6.2.3.2 Electrical properties 408 6.2.3.3 Luminescence 408 6.2.4 Devices technology 408 6.2.4.0 Introductory remarks 408 6.2.4.0.1 General processing Steps 408 6.2.4.0.2 Diode-(rectifier)-fabrication 409 6.2.4.0.3 Field-effect transistor fabrication 409 6.2.4.0.4 Light-emitting diode fabrication 409 6.2.4.1 Diffusion 410 6.2.4.2 Ion implantation 410 6.2.4.3 Epitaxy 411

6.2.4.4 6.2.4.5 6.2.4.6 Table of contents 6.2.4.3.1 Vapour-phase epitaxy (VPE) 411 6.2.4.3.2 Liquid-phase epitaxy (LPE) 412 Thermal oxidation 412 Surface preparation 413 6.2.4.5.0 Introductory remarks 413 6.2.4.5.1 Gaseous etching 413 6.2.4.5.2 Molten salt etching 414 6.2.4.5.3 Electrolytic etching 414 Contact fabrication 414 References for 6.2 415 Figures 590 ff. 591 591 ff. XIII