Part 3: Test Structures, Test Chips, In-Line Metrology & Inspection CTO, Maydan Technology Center Applied Materials, Inc. Mike_Smayling@amat.com
Topics Introduction to Test Chips Test Structures Basic Concepts Problems / Issues Real Wires Test Chips Different Functions In-Line Structures Metrology Inspection Future Design Style Impact on Testchips Summary 2
Introduction to Test Chips What are they used for? Technology Development Design Guidelines Spice Models Technology File parameters Design Rules Fab Process Development Unit Processes Process Flow Production monitoring Who designs them? Process Integration + Driver-Product Designers Who tests / analyzes them? Process Integration + Product Engineering 3
Test Structures: Basic Concepts Partition the device / interconnect What is being tested / stressed? What isn t being tested / stressed? Defining the Design Space Focus on the target dimensions for what is being tested, create the space around the target Use relaxed rules for what isn t being tested Analyze the results based on the design space DUTs, not just the target DUT 4
Test Structures: Design Space Design Space is the Width / Space / Overlap combinations covering what is expected in manufacturing Should cover a region which will show passing results as well as failing results May be limited by patterning capability Examples 5
Test Structures: Design Space Example This chip had a design space covering several pitches with many combinations of width and space The same combinations were applied to line-width resistors, combs, and comb-serpents Line Space (nm) 200 180 160 140 120 100 80 60 Pitch:185nm Pitch:190nm Pitch:195nm Pitch:200nm Pitch:205nm Pitch:210nm Pitch:220nm Pitch:240nm CD-65E_Line Width vs Line Space 40 20 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Line Width (nm) 6
Test Structures: Problems / Issues The root cause of many test structure problems is the failure to Partition the device / interconnect Examples Via Chain Other problems are caused by just looking at the target device, not the entire design space Examples Line-Width Resistors Comb-Serpents 7
Test Structure Problem: Via Example Short Via Chain Hook-up Because of the details of the hook-up, this DUT had a high failure rate even though the other vias had good yield Last via is different from the other nine. Wide metal hook-up pulls back and rounds, leaving the via uncovered 8
Test Structure Problem: Resistor Example Need to look at the entire design space In this case, the 115nm lines in one orientation had an OPC problem; if this had been the target size, with no other DUTs measured, incorrect conclusions would follow 9
Test Structure Problem: OPC Comparison Comb-Serpent Low Yield at a non-minimum Width/Space KrF OPC was aggressive, ended up with a small space at one pitch ArF OPC required much less layout adjustment, had no problem The issue was found on diagonal structures, but Manhattan DUTs had the same problem Post-OPC E-Test KrF Yield, % Pass ArF Yield, % Leakage Current, A 10
Test Structures: Real Wires Many of the structures used on test chips to evaluate copper interconnect look nothing like wires on real chips Structures used to evaluate the copper CMP unit process are typically much larger in area and include very wide lines to determine dishing Structures used for interconnect modeling should look like Real Wires Asymmetric neighborhoods Non-regular local and global lines 11
Test Structures: Real Wire Examples Global Lines Local Lines Bond Pad DUT Full module Connection detail DUT Line and global line detail 3 local lines Global spacing to local lines Every other DUT adjacent to bond pads 12
Test Structures: Real Wire Results Line Resistance (Ohms) 110 100 90 80 70 60 50 40 30 20 Line Resistance 20 30 40 50 60 70 80 Density (%) 110nm 220nm 330nm Dense line results 220, 330nm modeled okay 110nm model not correct The need for a new model was clear for 90nm technology Line Resistance (Ohms) 110 100 90 80 70 60 50 40 30 20 Line Resistance 110nm 220nm 330nm 110nm* 220nm* Global density impact Consistent for a given W/S Different for a different W/S Another new model needed to account for global density 20 30 40 50 60 70 80 Dens ity (%) Two interesting results came from these modules: - Increase in R for 110nm line at 20% density - Difference in R at a given density depending on global W/S 13
Test Structures: Real Wire Physical Data Array Width 40µm 40µm X-axis N. Distance > array width 5µm each side 90 Step Height (nm) 70 50 30 10-10 -30-50 110/110 (220/880) 110/110 (440/440) 110/110 (880/220) 220/220 (220/880) 220/220 (440/440) 220/220 (880/220) -70 5 15 25 35 45 55 65 75 Scan Length (µm) Density P. Distance 20% 20µm 50% 15µm 80% 10µm 14
Test Structures: More complex Real Wires Connection detail DUT Line and global line detail Variable local lines Top/bottom W/S for local and global lines Segmentation of global lines, vertical global lines Newer modules are much more complex in the number of options and the capability to study more density effects 15
Test Structures: Real Wire Buss 70 Series1 Series2 Series3 Series4 Series5 65 Series6 Series7 Series8 Series9 60 Series10 Series11 Series12 Series13 Series14 R, Ohms 55 50 Series15 Series16 Series17 Series18 Series19 Series20 Series21 Series22 Series23 45 Series24 Series25 Series26 Series27 Series28 40 35 1 3 5 7 9 11131517192123252729 Line number Series29 Series30 Series31 Series32 Series33 Series34 Series35 Series36 Series37 Series38 AFM of DUT by Susie Yang. 29 lines are in each DUT, the line resistance is measured for each position DUT by DUT This shows the variation within one die, and within one wafer This is a realistic structure representing a real data-buss on a chip. It can help chip designers do better statistical design. 16
Test Structures: More Real Wire Results R, Ohms 50 48 46 44 42 40 38 36 34 32 30 1 Max-die Average Min-die 3 5 7 9 11 13 15 Line 17 19 21 23 25 27 29 R, Ohms 95 94 93 92 91 90 89 88 87 86 85 New Process, OPC Older Process Within-buss variation is much smaller in the new process and with better OPC. Within-wafer variation is smaller in the new processes. It is very helpful to have the same test structures available to use with different kinds of processes. 1 Average 3 5 7 9 11 13 15 Line 17 19 21 23 25 27 29 17
Test Chip Functions Big Enchilada chips for evaluating design space for devices and interconnect, usually during the technology development phase Large number of DUTs which can be individually probed or accessed through decoding / multiplexing circuits Unit process chips focus on a particular piece of equipment and a specific process, like oxide or copper CMP Yield chips, which cover a smaller design space and allow separating systematic and random defects Production monitoring, often in the scribe lines, with a subset of test structures at the target dimensions 18
Big Enchilada Test Chip: XD-90 >900 test modules >12500 DUTs >3700 Transistors Real Wires (>1800 DUTs) X Architecture Duts Inspection regions OCD sites Auto-Dummy Fill 100 10 The Transistor Dimension XNA XNB XNC XND XNE XNF Gate Width (um) 1 XNG XNH XNJ XNK XNL XNM XNS XNT XNR 0.1 0.1 1 10 100 Gate Length (um) XNW 19
Unit Process Test Chip: STI-130 10% 70% 20% 60% OCD 50% 40% 40% 40% 30% 40% 500um Trench in 40% array 200um Trench in 40% array 100um Trench in 40% array 40% 40% 100um Active in 40% array 200um Active in 40% array 40% 40% Alt-40% 40% 40% 40% 40% 10 60% Pattern Density Trench and Active Test sites OCD sites DRAM-like pattern No Dummy Fill The chips is used for fill rule development! No Sub-resolution structures Do not want yield to limited by litho 20
Defectivity Test Chip: DM-1 120 250nm features Horizontal, vertical lines Line Lengths 1 200um No Dummy Fill No Sub-resolution structures Post-Processing break in a line pattern 21
In-Line Structures for Metrology Thin Dielectric Film Thickness, n, k Squares large enough to include the measurement beam spot size, typically 50-100um The pattern layers over and under the thin film being measured are important Critical Dimensions (CD) Lines, Holes for top-down CD-SEM measurements; use tools like OPC-Check to create recipes for the VeritySEM from layout database tags Lines for Scatterometry (OCD) measurements Lines, Holes for cross-section SEM measurements Surface topography Lines for High Resolution Profilometer and AFM measurements Doping profile Squares large enough for SIMS measurements, typically 100-200um 22
In-Line Structures for Metrology: Data Flow Design / EDA Wafer Fab Layout DRC RET Tagging Review XML GDS Images & CD OPC-Check Recipes Images & CD GDS VeritySEM Mask Shop Fracturing MPC DRC Writing CD Inspect Mask Deposition Etch CMP Clean Pattern Inspect 23
In-Line Structures for Inspection Systematic Defects Large arrays with different dimensions to determine sensitivity of different structures Analysis tools to bin the defects depending on the pattern dimensions Most systematic defects show an increase in the variability of parametric values prior to a hard fail Random Defects Range of patterns expected in real chips Arrange structures in the floor plan to simplify recipe creation Include intentional defects for calibration and location markers Link data from defect review SEM like SEMVision to the original layout database 24
In-Line Structures for Inspection: Binning Systematic Defects These structures were designed to take defect data from the ComPlus and overlay with the design information to create defect binning by orientation and line-width 200 180 160 140 120 Counts 100 80 60 40 20 0 1 2 3 4 5 6 7 Horizontal 8 9 10 11 14 W/S 15 16 17 18 19 20 21 22 Vertical 23 24 25 26 27 28 S N K G L D A 25
Systematic Defects Structures: Variability 20%, 50% σ = 4% Yield, % 80% σ = 8% Line R, Ohms Before the line resistance goes out of spec, the variability has already increased by 2X. 26
In-Line Structures for Inspection: Random Defects Yield, % Via Chain R, Ohms The yield on long via chains with identical rules shows the random defect density. 27
Future Design Style Impact on Testchips Today s problem Random Logic layout has many OPC problems, this is going to get worse. The number of RET steps gets longer for each technology generation 2-D layout is the main contributor to the problem; this also causes DUT hook-up problems in testchips Future solutions Business-as-usual. Fabs will spend more and more for steppers, designers will spend more and more for RET -OR Designers will adopt much more regular design styles. The layout will mimic gratings, extending the resolution for a given wavelength and numerical aperture. This style will also reduce line-width variability. 28
Design Style Examples Random logic The wiring for random logic today uses bends in the M1 to connect transistors. For the 90nm lines shown below, the bent wires print. For 65nm lines, without different rules for spaces and widths, the vertical lines don t appear at all. Even when they appear, the edges are wavy. The 65nm only horizontal layout resolves well. Testchips This implies that a problem is coming for testchip DUT hookup! 90nm 65nm 65nm only horizontal Aerial Imaging by Sequoia Cell Designer 29
Summary Test Structures Need to separate different pieces of devices into testable elements Details in the structures make a difference Try to make the structures more like real chip layout Test Chips Separate big enchilada designs from unit process and defectivity designs In-Line Structures Specific structures for metrology are needed; tools are available to link the design database to VeritySEM recipes Inspection can be made more effective with proper design and floor planning Upcoming Issues 2-D test structures and DUT hook-up will become more difficult to pattern 30
Acknowledgements Applied Materials MTC staff, especially Michael Duane, Hui Chen Raymond Hung, Bingxi Wood, CP Chang Applied Materials executive sponsors Other collaborators David Overhauser: Overhauser-Li Consulting Karl Smayling: Atalanta Designs Valery Alexrad, Andrei Shibkov: Sequoia Design Systems Scott Becker 31
References, Michael Duane, Raymond Hung, Susie Yang, Shiany Oemardani, Real Wires: Test Chips Close Gap between Design and Process, Nanochip Technology Journal, 1-2006, pp 22-29. 32