New Applications for CMP: Solving the Technical and Business Challenges Robert L. Rhoades, Ph.D. NSTI Conference (Houston, TX) May 5, 2009
Outline Background and Business Climate for CMP Technical Approach STORM Development CMP Applications and Examples Conclusions 2
What is CMP? CMP = Chemical Mechanical Polishing (Planarization) Developed by IBM in late 1980 s. Licensed to and quickly adopted by both Intel and Micron in the early 1990 s Key manufacturing process required to improve device performance and achieve yield advancements No CMP Traditional Device (a) Side View (b) Top View Carrier (head) Slurry Feed Pad Conditioner Carrier (head) 4 Basic CMP Steps Newer Device Platen Wafer W Via Polishing Pad ILD Slurry Feed PMD W Plug Pictures courtesy of Medtronic, Inc. 3
CMOS Life Before CMP Topography at ILD levels (some severe) Sloped wall vias generally limited designers to only 2 or 3 levels of metal Even for fabs that adopted tungsten plugs and SOG, stacked plugs were generally not allowed 4
CMOS Life After CMP Topography under control CMP enabled multiple levels of metal Stacked plugs no longer an issue Shallow trench isolation widely adopted Drove several generations of shrinks and more complicated stacks However this technology also started to run out of steam for the most advanced CMOS devices AMD K6 microprocessor (circa 1996) 5
CMOS Life with Cu CMP IBM PC603 microprocessor (circa 1998) Dual damascene process integration for patterning Cu lines and vias Primary process issues: Robust clear, defect density, dishing, erosion Fastest growing CMP application for past few years, but still smaller than oxide and tungsten overall 6
Interconnects at Intel Interconnect Technology CMP Evolution 1000 nm Two Our Al Expertise, Metal layers, BPSG 350 nm Four Al metal layers, W polish, PSG 500 nm ILD planarization, W plugs w etch back 180 nm STI, 6 Al Metal layers 250 nm STI, Five Al metal layers, SiOF Process, Application, Equipment, & Slurry Evolve, but not as much on Pads Source: Courtesy of Ken Cadien Former Intel fellow 130 nm 3-6 Cu Layers, PMD, W, STI 65 nm 4-11 Cu Layers PMD, W, STI, OSG 90 nm 3-9 Cu Layers, PMD, W, STI OrganoSilicate Glass (OSG) CMP Applications Oxide Polish Pre-Metal Dielectric Interlevel Dielectric STI Polish Poly Polish Tungsten Polish Copper Polish Barrier Polish High k Gate 7
Driving Forces Today Since 2005, consumer products have become primary industry driver. Source: 2007 Industry Strategy Symposium Hans Stork, CTO, Texas Instruments Short product life cycles. Consumers demand More for Less. Consumers demand More in Less Space. Source: 2007 Industry Strategy Symposium Steve Newberry, CEO, Lam Research Corporation Contributing factors for Moore s Law device shrinks, multi-level stacks & larger wafers. Result = Fierce Competition + Control Unit Costs + Develop Technology Fast + Ramp Volume Quickly 8
Competitive Advantage Revenue Loss from Being Late to Market Acceleration with CMP Outsourcing: Scenario 1: First time CMP implementation Customer Internal Technology Integration Project: Equipment Purchase & Delivery Design, Integrate, Optimize & Quality CMP Implementation with Entrepix: Optimize & Qualify Ramp Customer Generating Revenue Ramp Strategic Factors in the IC Industry, FSA Forum, June 05 Dr. Handel Jones, Chairman & CEO IBS, Inc. Project Phases Scenario 2: CMP capacity expansion Customer Internal Capacity Expansion Project: Equipment Purchase & Delivery Qualify Ramp Customer Gen. Rev. CMP Capacity Expansion with Entrepix: Qualify Ramp Customer Generating Revenue Scenario 3: CMP burst or flex capacity absorption Customer Internal Capacity Expansion Project: Equipment Purchase & Delivery Qualify Ramp Customer Gen. Rev. CMP Capacity Expansion by IDM already qualified at Entrepix: Ramp Customer Generating Revenue Scenario 4: CMP technology improvement or cost reduction Customer Internal Capacity Expansion Project: Develop, Optimize & Qualify Ramp Customer Generating Revenue CMP Capacity Expansion with Entrepix: Qualify Ramp Customer Generating Revenue TIME 9
Business Realities Time IS Money Labor cost + cycles of learning + opportunity cost Competition in most markets is fierce Quality & reliability can not be compromised Each process module must be efficient 10
Business Response Minimize Manufacturing Costs Benchmarking Yield Enhancement Optimize Unit Processes Focus on Efficiencies Preserve Capital Extend Equipment Life Keep Depreciated Fabs R&D Consortia Install Less Overcapacity Delay Capital Expenditures Accelerate Development While Reducing Costs Reduce Cycles of Learning Extend Proven Technologies Lower % of Engineering Wafer Starts Leverage Outside Expertise 11
Comprehensive CMP Solution #1 Accelerate Time to Revenue #2 Reduce Cost and Risk 12
Applications for CMP Continue to Expand Numerous complex puzzles 2009 - Qty 36 1995 - Qty 2 2001 - Qty 5 CMOS CMOS CMOS New Apps Substrate/Epi Glass (oxide) Glass (oxide) Glass (oxide) Doped Oxides GaAs Tungsten Tungsten Tungsten Nitrides GaN Copper Copper NiFe & NiFeCo InP Shallow Trench Shallow Trench Noble Metals CdTe & HgCdTe Polysilicon Polysilicon Al & Stainless Ge and SiGe Low k Polymers SiC Cap Ultra Low k Ultra Thin Wafers Diamond & DLC Metal Gates Direct Wafer Bond Si & Reclaim Gate Insulators Through Si Vias SOI High k Dielectrics 3-D Packaging Quartz Ir & Pt Electrodes MEMS Titanium Magnetics Nanodevices Integrated Optics Each application of CMP requires an optimized process that meets both performance and cost targets 13
CMP Metrics Five key metrics for a CMP process Removal Rate and Uniformity Defectivity Planarization (step height, dishing/erosion, surface roughness, etc.) Process Stability (consistent performance from wafer-to-wafer) Cost per Wafer 14
CMP Development CMP Development Sequence Generate Test Wafers Consumables Screening Process DOE's Optimize Uniformity Optimize Planarity Optimize Defectivity Repeatability (multiple runs) Stability (marathon) Release for Device Qualification Zoom in on CMP process development Screening Tests Assumes fundamentals of pad/slurry research are already done by suppliers Test wafer availability and quality often impact timeline, validity of results, etc. Optimization Initial process DOE s generally focus on removal rate and gross surface quality Optimization stages can be interchanged or executed in parallel Repeatability Planarity can mean step height, dishing, erosion, roughness, etc. depending on the material and intended application Marathon Failure at any stage usually means backing up at least one stage to try again 15
STORM STORM Screening Tests Optimization Repeatability A proven approach to successfully developing new CMP processes Marathon 16
Intro to CMOS Example Project launched to develop a planarized integration for an existing facility running mostly 0.5um and larger devices which did not require CMP. Integration included 2 levels of oxide CMP (PMD and ILD) and 2 levels of tungsten CMP (contact and via1). Initial estimate was roughly 24 months to purchase, install, and qualify CMP equipment plus develop the integration and be ready for production ramp. By leveraging an outsource CMP provider, integration work was started almost immediately and executed in parallel with the equipment lead time. 17
Timeline Comparison Key aspects of predicted time savings: Development could begin as soon as test wafers were ready. Equipment purchase, lead time, and installation in parallel. Faster cycles of learning, fewer wafers, lower cost compared to internal. Project Phases Initial Project Timeline for Tool Purchase and Internal Development Production Ramp Qualification Development Install Equip. Purchase Timeframe Acceleration = 12+ months Adjusted Project Timeline with CMP Outsource through Entrepix: Production Ramp Volume Production Revenue Enabled Qualification Development Install Equip. Purchase 3 mos 6 mos 9 mos 12 mos 15 mos 18 mos 21 mos 24 mos 27 mos 30 mos Time 18
Timeline Detail Detailed Timeline for CMP Process Module Development Patt. Wafers Blanket Wfrs CMP Lab Days Week #1 Week #2 Week #3 Week #4 Week #5 Week #6 Week #7 Week #8 Week #9 Week #10 Week #11 Week #12 Week #13 Week #14 Task or Milestone Details Phase 1: PMD Planarization Duration ~6-8 wks X Generate test wafers BPSG X CMP process - Initial characterization 12 25 2 X Polar evaluation of results X PMD 2nd round optimization 13 25 1 X Week #15 Week #16 Week #17 Week #18 Week #19 Week #20 Week #21 Week #22 Week #23 Week #24 Week #25 Week #26 Week #27 Week #28 Week #29 Week #30 Week #31 Week #32 Week #33 Week #34 Week #35 Week #36 Week #37 Week #38 Week #39 Week #40 Week #41 Week #42 Phase 2: Tungsten Contacts Duration ~8 wks X Mask layout and photo optimization X Generate test wafers 3rd party tungsten CVD X CMP process - Initial characterization Incl. SEM X-sections 12 25 3 X Polar evaluation of results X Contact 2nd round optimization 13 25 2 X Phase 3: ILD1 Planarization Duration ~6 wks X Generate test wafers X CMP process - Initial characterization 12 15 2 X Polar evaluation of results X ILD 2nd round optimization 13 10 1 X Phase 4: Tungsten Vias Duration ~6 wks X Mask layout and photo optimization X Generate test wafers 3rd party tungsten CVD X CMP process - Initial characterization 12 25 2 X Polar evaluation of results X Via 2nd round optimization 13 25 1 X Prototype Run (Begin Qual Lots) Duration 4-6 wks X Mask layout and photo optimization X Verification of entire process flow 25 25 4 X Evaluation of prototype devices In-line and EOL (ongoing) Polish processes developed: 4 (PMD, W Contact, ILD, W Via1) Total patterned wafers: < 125 Total blanket test wafers: < 200 Total CMP lab shifts: < 12 19
Issues Resolved As might be expected, a few issues were encountered during the project. Examples are given below and further detail is provided in a few cases. Issue Composition and thickness of ILD dielectric layer Alignment marks (inconsistent contrast on wafers with CMP) Pattern density effects Ti/TiN liner and CVD W deposition thicknesses Poor contact fill (seen on first contact lot) High NMOS leakage and poor p- field inversion How Resolved Technical inputs from Entrepix with confirmation on 1 st engineering lot Technical dialogue between Entrepix and customer engineering team Verbal description of effects confirmed with data from test structures adjustments made in design rules Starting point suggestions followed by optimization on 1 st and 2 nd engineering lots Suggestions from Entrepix and Novellus helped solve issue in one cycle of learning (Traced to insufficient strip after contact etch) Changed PMD dielectric composition from TEOS to PSG or BPSG 20
Issue #1 High Rc Hollow contact Improved contact Hollow contacts with high resistance on first lot. Initial brainstorming between customer and outsource provider led to short list of likely causes. 4485A001 80 W-PLUG 3.JPG 4485A001-09 NOTCH A1.JPG Resolved with one round of optimization. Resolution involved optimizing post etch strip and was confirmed on next product lot. 21
Issue #2 - Leakage The first integration lot showed unexpectedly high NMOS leakage and p-field inversion issues. Technical brainstorming identified trapped charge in TEOS layer as a possible cause of the observed issue. NMOS leakage by PMD oxide Result 10000 3000 1000 300 100 30 10 3 1 0.3 0.1 0.03 0.01 BPSG PSG TEOS PMD glass composition P-field inversion by PMD oxide 60 50.01.05.10.25.50.75.90.95.99 TEOS BPSG -3-2 -1 0 1 2 3 Normal Quantile.01.05.10.25.50.75.90.95.99 BPSG 40 Split lot data confirms that changing to either BPSG or PSG for pre-metal dielectric resolves both issues. Result 30 20 10 0 BPSG PSG TEOS TEOS -3-2 -1 0 1 2 3 PMD glass composition Normal Quantile 22
CMOS Summary By leveraging the capabilities of an outsource CMP provider, the project timeline for developing a 0.35 um integration in a fab was accelerated by roughly one year. Acceleration was driven by two primary factors. First, the team did not have to wait on internal CMP equipment to be purchased and installed, thus avoiding 6-9 months of delay. Second, several key cycles of learning were assisted by insights and guidance from the external technical staff. Substantial benefits and time savings realized through effective utilization of CMP outsourcing. 23
MEMS over CMOS Key Process Metrics & Constraints Metric Incoming Value Post-CMP Target Actual Oxide film thickness 6.5 um 3.0 um 3.02 um Step Height 2.8 um < 0.4 um 0.2 um Removal Rate (um/min) n/a 0.5 0.488 Critical Concerns: Thick oxide layer over CMOS Final topography must be < 0.4um Smooth No sharp corners anywhere Batch to batch consistency Removal Rate (Ang/min) 6000 5000 4000 3000 2000 1000 0 1 2 3 4 5 6 7 8 9 10 11 12 Run # Photos downloaded from web sites, including Sandia National Lab 24
Direct Wafer Bonding Example #1: TEOS on X Oxide surfaces tend to bond well when polished to sufficiently low Ra Incoming roughness driven by surface prep of underlying material Sufficient oxide thickness must be deposited to remove at least 2x initial peak-to-valley roughness Material Stack Incoming Ra (A) Post-CMP Ra (A) TEOS on Silicon 7 3 TEOS on SiC 72 7 TEOS on Polysilicon 87 7 TEOS on AlN 187 11 TEOS on Metal 332 8 Example #2: Inlaid Cu in TEOS Incoming topography >2.5 ka Goal of <200 A total topography Flat across Feature POST-CMP TOPOGRAPHY ACHIEVED 70-90 Angstroms 25
Conclusions Efficient development of new products is required for any device manufacturer to remain competitive CMP process development involves a sequence of stages (STORM) to efficiently hit technical goals Screening Tests Optimization Repeatability Marathon Proper utilization of CMP outsourcing enables Accelerate timelines Preserve capital Reduce cost and risk 26
Contact info Anyone desiring copies of this presentation or any other information please contact: Rob Rhoades Chief Technology Officer Tel: 602 426-8668 Fax: 602 426-8678 rrhoades@entrepix.com 27
Appendix Slides providing additional details on STORM 28
Screening Tests Early stage development efforts often involve: Immature deposition or growth processes Poorly characterized materials or integrations Technologists who may not be familiar with CMP and how it interacts with other process modules Wide variation in pattern density/feature sizes Wafer sizes smaller than 200 mm Limited availability of test wafer These factors can create huge challenges for CMP 29
Rate Screening Removal Rate Metal CMP application Removal Rate (Ang/min) 8000 7000 6000 5000 4000 3000 2000 1000 0 Slurry #1 Slurry #2 Slurry #3 Slurry #4 Slurry #5 Slurry #6 Slurry #7 Slurry #8 Slurry #9 Slurry #10 Pad selection frozen Goal of 4 ka/min Multiple slurry candidates Slurry #8 was chosen for further optimization 30
Process DOE s Resources Consumables (Pad and slurry) Blanket film test wafers (all mtrls) Defect monitor wafers (if available) Desired Outputs Rate and uniformity responses to changes in major process variables Identify a process to start further optimization Experimental Plan Inputs Goal is to get preliminary process responses to major variables Preston s Equation (RR=k*P*V) is only an approximation Keep % changes below 25% to keep DOE s as linear as possible Responses to slurry flow and back pressure are not usually linear Successive 2x2 or 3x3 DOE s are generally preferable to massive designs Include defectivity as an output metric if wafers are available 31
Optimization Resources Consumables (Pad and slurry) Blanket film wafers (selected mtrls) Defect monitor wafers Patterned wafers for planarization Desired Outputs Single process recipe that meets all required process metrics Data supporting chosen recipe and responses in nearby process space Experimental Plan Inputs Be careful using DOE s single-variable curves often more helpful at this stage Focus on variables with strongest link to parameter being optimized Uniformity: Carrier-to-table speed ratio, back pressure or carrier zones Planarization: Downforce, table speed (keep in mind rate tradeoffs) Defectivity: Downforce, slurry flow, final recipe steps (remember tradeoffs) Number of wafers can quickly get large 32
Repeatability Resources Consumables (multiple batches) Blanket film wafers Defect monitor wafers Patterned wafers (optional) Desired Outputs Consistent process performance data using same process settings across multiple consumable sets Experimental Plan Inputs Keep process recipe consistent throughout trials Measure all relevant metrics, not just removal rate Planarization monitor can be low sampling frequency Defect monitor can likewise be low frequency if confident in process 33
Marathon Run Resources Consumables Blanket film wafers (selected mtrls) Defect monitor wafers Patterned wafers Desired Outputs Data showing process consistency through pad life (or at least a reasonably large number of wafers) Experimental Plan Inputs Generally want to prove stability for duration of pad life, or at least 250 wafers Different than repeatability focus is on process stability of a single pad set Can be a continuation of the last pad set of the repeatability trial Liberal use of filler wafers can save cost Sample at some low frequency for defects and planarization 34
Blanket wafer marathon 5000 4000 Oxide CMP Qualification Run Polisher: AMAT Mirra Mesa Pad: IC1010 Slurry: Klebosol 1501-50 Conditioning: In-situ Metrology: 49-point diameter scan, 3mm EE Removal Rate % NU 20.0 15.0 Removal Rate (Ang/min) 3000 2000 10.0 5.0 Uniformity (% 1-sigma) 1000 Start 25 50 75 100 125 150 175 200 225 250 Wafer Number 0.0 35