Proceedings of The National Conference on Undergraduate Research (NCUR) 2003 University of Utah, Salt Lake City, Utah March 13-15, 2003 Semiconductor Device Fabrication Study Tsung-Ta Ho and Michael R. Shealy Department of Electrical and Computer Engineering Virginia Military Institute Lexington, VA 24450. USA Faculty Advisor: Dr. J. Shawn Addington Abstract Our study involves the design and fabrication of semiconductor devices in the first semiconductor fabrication laboratory at the Virginia Military Institute. As this is a new laboratory, preliminary wet and dry silicon oxidation studies are performed to 1) develop necessary photolithography skills, 2) thoroughly characterize oxidation equipment, and 3) determine the proper processing parameters for both barrier and transistor gate oxide layers for device realization. The final portion of our study involves the fabrication of semiconductor devices, including resistors, p-n junction diodes, and n-channel E-MOS transistors. Here, our preliminary studies are extended to include mask design, dopant diffusion processing, aluminum contact deposition, and device characterization. Results of the study include oxide thickness measurements, sheet resistivity measurements, and device I-V curves. In addition, each device is replicated across the surface of the wafer to provide multiple data, and to allow us to evaluate process uniformity. The experiences and the results of this study will benefit the students at Virginia Military Institute who are interested in the semiconductor fabrication field. In this regard, we have completed processing guidelines and equipment-use instructions for students who will attend this laboratory in the future. Keywords: Semiconductor, Photolithography, Silicon 1. Introduction Through the guidance of the Electrical and Computer Engineering Department of Virginia Military Institute (VMI), the first semiconductor device fabrication study in the history of VMI has been performed. The laboratory, which was outfitted for the purpose of entry-level semiconductor device fabrication, was equipped with a thermal oxidation furnace module, photolithography module, wet process module, an aluminum physical vapor deposition (PVD) module and a device characterization module. The purpose of this study is to fabricate semiconductor devices including resistors, p-n junction diodes and enhancement mode n-channel MOS (n-emos) transistors on a pre-doped p-type silicon wafer. In order to achieve this goal, it is necessary to develop skills in oxidation, photolithography, diffusion, metal deposition, and device characterization. These tasks are described in detail in Section 2, below. 2. Procedures 2.1 wet oxidation The wet oxidation process grows a thick layer of silicon dioxide on the silicon wafer. In the study, for wet oxidation, silicon wafers are loaded into the thermal oxidation furnace at 600 o C with high purity nitrogen gas purging the furnace to prevent premature oxidation on the wafer. After the furnace reaches 1000 o C, the nitrogen gas is cut off and the wafers are then oxidized for the desired amount of time with the presence of high purity oxygen gas and water vapor. After the oxidation time passes, the oxygen and water vapor sources are cut off, the furnace is set to 600 o C, and the furnace is purged with nitrogen to prevent excessive oxidation on the silicon wafer. When the furnace reaches 600 o C, the silicon wafers then can be unloaded and the wet oxidation process is complete.
2.2 dry oxidation The dry oxidation process is used to grow a thin, dense, high quality layer of silicon dioxide on the silicon wafer. This process is usually required to produce the thin gate oxide layer on the n-emos transistor. The process for dry oxidation is fairly similar to that of wet oxidation. The only difference is that there is no water vapor source provided during the dry oxidation process. 2.3 silicon dioxide growth rate characterization Wet, dry and ambient air oxidations are performed to characterize the growth rate of silicon dioxide on the silicon wafer. With the knowledge of growth rate, the required time duration to grow a certain necessary thickness of silicon dioxide can be determined. This is necessary to successfully produce a sufficient thickness of barrier layer for the diffusion process and the desired gate oxide layer for the n-emos transistor. For both wet and dry oxidation, wafers are oxidized through the standard procedure for 1, 3 and 5 hours. For the ambient air oxidation, wafers are oxidized for 1, 4, and 8 hours without any high purity oxygen and water vapor supply. The thickness measurements are performed by using a Filmetrics Model F20 thin film measurement system at the Virginia Polytechnic Institute and State University (Virginia Tech). 2.4 photolithography Photolithography is the process used to transfer the pattern on the mask to the silicon wafer. In our study, the AZ 5214-E (positive) photoresist produced by Clariant Corporation is used. Even though we have only positive photoresist available, we are able to perform both negative and positive photolithography processes through different process procedures. For positive photolithography procedures, the photoresist is applied to the oxidized silicon wafer on a wafer spinner. Next, a ninety-second bake is performed on a 100 o C hot plate, followed by the 120-second ultra-violet (UV) light exposure with mask. Next, the wafer is developed in the AZ 400K Developer produced by Hoechst Celanese Corporation. A 6:1 ratio of de-ionized (DI) water to Developer is used for better process control. The wafer is then etched in the Buffer-HF Improved (BOE) produced by Transene Company. Finally, the silicon wafer is rinsed by acetone on the wafer spinner to wash away the remaining photoresist. For the negative photolithography process, the positive photoresist is applied to the oxidized silicon wafer on a wafer spinner. Next, a ninety-second soft bake is performed on a 100 o C hot plate, followed by the sixty-second ultraviolet (UV) light exposure with mask. Next, the wafer is heated on the 100 o C heat plate to perform the hard bake process for 180 seconds. Then, the silicon wafer is exposed for 240 seconds, this time without mask (flood exposure). Next, the wafer is developed in the AZ 400 K Developers and then etched in the BOE. Finally, the silicon wafer is rinsed by acetone on the wafer spinner to wash away the remaining photoresist. 2.5 diffusion Diffusion in the semiconductor fabrication process is performed to convert the exposed (not covered by the silicon dioxide barrier layer) p-type silicon wafer into n-type material or vice versa. In our study, a two-step diffusion process is performed and the phosphorus serves as an impurity dopant to selectively convert the p-type silicon wafer into n-type material. The two-step process includes pre-deposition, a short constant-source diffusion, followed by a drive-in process, a limited-source diffusion. [2] During the diffusion process, high purity nitrogen gas constantly purges the furnace to prevent unnecessary oxidation growth on the silicon wafer. In the predeposition process, a PhosPlus solid-state phosphorus source and two silicon wafers are loaded into the furnace at 600 o C. Next, the furnace temperature is ramped up to 810 o C and the pre-deposition process is performed for fortyfive minutes. After forty-five minutes, the furnace temperature is decreased to 600 o C and the phosphorus source is unloaded. Next, the furnace temperature is increased to 1100 o C and the drive-in process is performed for sixty-five minutes. Next, the furnace temperature is decreased to 600 o C and the silicon wafers are unloaded. 2.6 metal deposition Metal deposition in the semiconductor device fabrication is performed at in the end of the fabrication process to deposit metal film on the silicon wafer. The metal film layer is later selectively etched away by the photolithography process to leave the desired electrical contact points. In this research, aluminum is deposited on the silicon wafer through physical vapor deposition (PVD) techniques. The silicon wafers are mounted facedown near the top of the vacuum chamber, approximately four inches above a tungsten filament. Small pieces of aluminum are placed on top of the filament. Evaporation of the aluminum is performed by gradually increasing the filament temperature. 2
2.7 device fabrication The semiconductor devices fabricated in this research include twelve meander resistors, twelve straight-line resistors, twenty-four p-n junction diodes and twelve n-emos transistors on each of the two four-inch diameter p-type silicon wafers. In order to examine the uniformity of the fabrication process and device characteristics over the wafer surface, devices are distributed uniformly on each wafer. The device fabrication in this research is a four-mask process using 200µm design rules. The masks and device design guidelines are followed using design rules developed by Mead and Conway [2]. In summary, the device fabrication procedure includes: (a) Wet Oxidation: a two hour wet oxidation was performed to grow a thick layer of silicon dioxide serving as a barrier layer for the diffusion process. (b) Negative Photolithography (mask 1): to selectively etch off the silicon dioxide in order to expose the regions in which n-wells will be diffused. (c) Diffusion: diffuse the exposed silicon substrate into n-type silicon. (d) Negative Photolithography (mask 2): to selectively etch off the silicon dioxide in order to expose the p-type silicon in the p-n junction diode, and the gate region of the n-channel EMOS transistor. (e) Dry oxidation: a 45-minute dry oxidation was performed to grow a thin layer of silicon dioxide serving as the gate oxide for the n-channel EMOS transistor. (f) Negative Photolithography (mask 3): to selectively etch off the thin silicon dioxide layer in order to expose the electrical contact points for each device. (g) Metal Deposition: to deposit a thin layer of aluminum. (h) Positive Photolithography (mask 4): to selectively etch the aluminum layer and leave the desired electrical contact points. Figure 1 Device fabrication procedure [5] 3
3. results Figure 2 Devices on the 4-inch silicon wafer 3.1 silicon dioxide growth rate Thickness vs. Time of Dry & Wet Oxidation 10.000000 Thickness, micrometer 1.000000 0.100000 0.0000 0.100 1.000 Time, hour 10.000 Wet, Theoretical Wet, Experimental Dry, Theoretical Dry, Experimental Ambient Figure 3 Theoretical oxidation thickness vs. experimental result 3.2 resistors Resistor Current vs Voltage 1.00E-03 8.00E-04 6.00E-04 4.00E-04 Current (ma) 2.00E-04-2.00E-04 Wafer 1 Meander Wafer 2 Meander Wafer 1 Straight-line Wafer 2 Straight-line -4.00E-04-6.00E-04-8.00E-04-1.00E-03-2.50E+00-2.00E+00-1.50E+00-1.00E+00-5.00E- 5.00E- 1.00E+00 1.50E+00 2.00E+00 2.50E+00 Voltage (V) Figure 4 Resistor I-V characteristic 4
3.3 diodes P-N Diode I-V Characteristic 3.00E-04 2.50E-04 2.00E-04 Current(A) 1.50E-04 1.00E-04 5.00E-05-5.00E-05-2.00E+ -1.50E+ -1.00E+ -5.00E+ 00 0.00E+ 00 5.00E+ 00 1.00E+ 1.50E+ 2.00E+ 2.50E+ 3.00E+ Voltage(V) Figure 5 Diode I-V characteristic Figure 5 shows the diode I-V characteristic. The appearance of exponential growth is expected with diodes [2] [6]. However, the figure also illustrates both non-ideal diode behavior, as well as the presence of significant series resistance. 3.4 transistors Current vs. Voltage 2.00E-03 1.50E-03 Average Current (A) 1.00E-03 5.00E-04-5.00E-04 Vgs = -7.5V Vgs = -5.0V Vgs = 0.0V Vgs = 2.5V Vgs = 5.0V Vgs = 7.5V -1.00E-03-1.50E-03-4.00E+00-2.00E+00 2.00E+00 4.00E+00 6.00E+00 8.00E+00 1.00E+ 1.20E+ 1.40E+ Voltage (V) Figure 6 Current vs. voltage for the transistors 5
4. Analyses 4.1 resistors Table 1 average resistor values and standard deviation Average Value, Standard Meander Resistor Straight-line Resistor Resistance Ratio (Meander/straight-line) Deviation Wafer 1 3.9KΩ, 0.31KΩ 2.52KΩ, 0.31KΩ 1.54 Wafer 2 4.6KΩ, 0.56 KΩ 3.15KΩ, 0.87 KΩ 1.46 R = ρ L/A (1) Where R = resistance, ρ = resistivity, L=length of resistor, and A=cross-sectional area. Theoretically, resistivity and cross-sectional area of both the meander and straight-line resistors are assumed to be the same, because they are diffused under the same conditions. Since the length of the meander resistor is about 1.69 times the length of the straight-line resistor, so, according to equation (1), the resistance of the meander resistor is expected to be 1.69 times of the resistance of straight-line resistor. The experimental ratios, meander resistance vs. straight-line resistance, are 1.54 and 1.46 respectively for wafer 1 and 2, which are rather close to the theoretical value. One of the factors influencing accuracy of device measurement is The exposure of the component to light. This is due to the photoconductive nature of silicon. A short experiment is performed to see the effect of light during the device measurement by flashing a 110V 8W light source over the resistor while the device is being tested. Resistor Measurement While Flashing Light 8.00E-04 6.00E-04 4.00E-04 Current, (A) 2.00E-04-2.00E-04-4.00E-04-6.00E-04-8.00E-04-2.50E+00-2.00E+00-1.50E+00-1.00E+00-5.00E- 5.00E- 1.00E+00 1.50E+00 2.00E+00 2.50E+00 Voltage, Volts Figure 7 The effect of light on device characterization The light was flashed ten times during testing, resulting in ten spikes, as shown in Figure 7. Therefore, it is proven that light dramatically influences the accuracy of the device characterization results. [5] 4.2 p-n junction diodes Referring to Figure 5 diode I-V characteristic, the shape of the plot is very similar to the theoretical plot. That is when the applied voltage is less than zero, there is almost no current flowing, but for voltages greater than zero, the current starts to flow through the diode. However, the turn on voltage of the fabricated device is rather high. The theoretical turn on voltage is about 0.7 V, however, the experimental result appears much higher. After investigation, the series, including contact resistance, is a contributing factor, because when the device measurement probes were moved from place to place, the results differed dramatically. 6
In order to obtain a better analysis, Figure 8 diode I-V characteristic is plotted by zooming in Figure 7 from V = -10 volts to V = 1.5 volts. The theoretical mathematical model of diode I-V characteristic is: I = I s [(exp(v/nv t )-1) [4] (2) Where I s = saturation current, n = adjustment factor, theoretically between 1 and 2 and V t = thermal voltage = 25.2 mv at room temperature. By fitting the diode I-V characteristic in Figure 8 to the theoretical equation, n is obtained to be approximately 50, which is outside the expected range of n = 1 to 2. [1] This discrepancy may be a result of the undesired large series resistance due to the mask or device structure design. In the future, for the improvement of the diode characteristic, we may enlarge the electrical contact area between the aluminum and the n-type silicon in order to reduce the impact of the series resistance on the diodes. Diode I-V Characteristic 1.50E-05 1.00E-05 Current (A) 5.00E-06-5.00E-06-1.00E-05-1.50E-05-2.00E-05-1.20E+ -1.00E+ -8.00E+00-6.00E+00-4.00E+00-2.00E+00 2.00E+00 4.00E+00 Voltage (V) Figure 8 diode I-V characteristic 4.3 n-channel EMOS transistor Referring to Figure 6 transistor I-V characteristic, the experimental results are as expected for an n-channel EMOS transistor. As shown in Figure 6, the I D curves, corresponding to Vgs = -7.5V, -5.0V and 0.0V are expected to be zero. However, because of the light source in the laboratory environment, a noticeable current is observed. [1][5] 5. Conclusions The successful semiconductor device fabrication and characterization of our research have led the microelectronics study at VMI to another stage. Although the semiconductor device fabrication laboratory used in our study is a not a cleanroom environment, semiconductor devices including resistors, p-n junction diodes and n-channel EMOS transistors are successfully fabricated and characterized. In most cases, we have been able to recognize and account for experimental variations from theoretical expectation. During fabrication, the photolithography process is the process that posed the most problems; however, it is one of the most critical and most used practices in the fabrication process. Compared to other parts of the fabrication process, such as oxidation, diffusion and metal deposition, photolithography requires the most human intervention, which in turn, may induce the most error in the fabrication process. Furthermore, the laboratory used in this study is not climate-controlled. This increases the difficulty of performing photolithography, as the chemical processes therein are temperature-dependent. Nonetheless, with many trial-error procedures and engineering investigations, the problems encountered during fabrication and characterization have been recognized and solved. For example, without a cleanroom, dust may adhere to the photoresist surface on the silicon wafer and compromise the uniformity of the photoresist. This, in turn, may result in an undesirable etch pattern on the wafer or failure of devices. In the non-cleanroom environment, our solution is to deposit a second layer of photoresist on the wafer in order to cover the portions of first photoresist ruined by dust. Although dust may still adhere to the second layer of photoresist, the probability is rather small that the dust on the second layer will align exactly with the affected areas on the first layer of photoresist. Furthermore, given our laboratory environment and for better control and results during our device fabrication process, we have modified several process procedures. For example, during photoresist development, the suggested process is to mix a 5:1 DI water to AZ 400K Developer ratio. However, with the 5:1 ratio, the developing process was too quick to 7
control at times, causing several failures in the photolithography process during the early stages of our study. This problem was solved by diluting the developer with more DI water, using a 6:1 or even 7:1 ratio, instead. By doing this, we have greater control over the developing process, and have better results, as well. Our study of semiconductor device fabrication has opened the door for the students willing to study the semiconductor area at VMI. Over the duration of our study, we have written the laboratory manual for the device fabrication process, which can be used to teach students who are interested in attending the class or laboratory in the semiconductor area. Currently, VMI is planning to reconstruct the engineering building in summer 2003, and the semiconductor fabrication laboratory is part of the plan. We hope that within a few years, the semiconductor laboratory of our study will be filled with ambitious and tenacious undergraduate students carrying on novel semiconductor research projects and moving the technology in this discipline to another new level. 6. Acknowledgements The authors would like to thank the following people and corporations for their support throughout our study: Rich Winder, Electro-Mechanical Systems, Inc. Dr. Bob Hendricks. Mr. David Gray, Mr. Charlie French. Virginia Tech Virginia Semiconductor, Inc. silicon wafer donations Techneglas - solid source wafer donations Doe and Ingalls, Inc. - aluminum etch donation and BOE Mr. Ted Grigorieff - VMI Chemistry Dept. - lab technician Clariant Corp. - photoresist and developer 7. References [1] Gray, D.T., Hendricks, R.W. A Semiconductor Characterization System for an Undergraduate Fabrication Laboratory, Materials Science and Engineering Department, Virginia Polytechnic Institute and State University, Blacksburg, Virginia. [2] Jaeger, R.C. Introduction to Microelectronic Fabrication. Vol.5, Ed. Second (2002). Prentice Hall, New Jersey. pp. 67-225. [3] Hendricks, R.W. An Undergraduate Microchip Fabrication Facility. Proc. of ASEE Annual Meeting, Albuquerque, NM, (June 20). [4] Sedra, Adel S, Kenneth C. Smith Microelectronics Circuits Fourth Edition. Oxford University Press, Inc, New York, New York. Pp122-134. [5] Timmons, C.T., Gray, D.T., & Hendricks, R.W., Process Development for an Undergraduate Microchip Fabrication Facility. Proc. ASEE Annual Meeting, Albuquerque, NM, (June 20). [6] Plusquellic, J., MOS Transistor Definitions [online] http://www.csee.umbc.edu/~plusquel/vlsi/slides/chap2_1.html 8