Lezioni di Tecnologie e Materiali er l Elettronica Danilo Manstretta danilo.manstretta@univ.it microlab.univ.it
Outline Passive comonents Resistors Caacitors Inductors Printed circuits technologies Materials and fabrication stes Assembling Monolithic IC technologies Fabrication stes (thermal oxidation, thermal diffusion, ) IC technologies (CMOS, BiCMOS) Packaging and Thermal Design Lezioni di Tecnologie e Materiali er l'elettronica 2
HOW A MOS TRANSISTOR IS BORN CMOS PROCESS FLOW Lezioni di Tecnologie e Materiali er l'elettronica 3
CMOS Technologies n well TOP VIEW S G D S G D + + + POLY POLY NMOS PMOS CROSS SECTION NMOS GND G S D + PMOS G S + D + VDD n well Lezioni di Tecnologie e Materiali er l'elettronica 4
MOSFET Oeration 2 VDS L 2 W ID ncox VGS VTH VDS B KT ln q N n i A V TH V FB 2 B 4qN C A ox S B C ox t ox ox C gs Vds0 C ox WL SOURCE GATE DRAIN n i =1.45 10 10 cm -3 at 300K Lezioni di Tecnologie e Materiali er l'elettronica 5
CMOS Process Flow (1) SiO 2 a) Oxidation P / As resist - - - - - - - - - - - - - - - - - - - b) N-well imlant Lezioni di Tecnologie e Materiali er l'elettronica 6
CMOS Process Flow (2) - - - - - - - - - - - - - - - - - - - AREAS WHERE PMOS TRANSISTORS CAN BE CREATED c) N-well diffusion (drive-in) The active areas areas are the regions where active devices are imlemented. Active areas are surrounded by isolation regions. Si nitride is deosed over active areas to rotect it from doing and oxidation carried out over isolation regions. NMOS active area PMOS active area Si nitride - - - - - - - - - - - - - - - - - - - ~m d) Active area definition: Si nitride shield deosition and etching Lezioni di Tecnologie e Materiali er l'elettronica 7
CMOS Process Flow (3) P / As - - - -- - - - - - - - - - - - - - - e) Field n-tye imlant on s B + + + + + + + + - - - -- - - - - - - - - - - - - - - f) Field -tye imlant on Lezioni di Tecnologie e Materiali er l'elettronica 8
CMOS Process Flow (4) active areas A thick oxide layer is formed over isolation regions n n g) Field oxidation and diffusion Lezioni di Tecnologie e Materiali er l'elettronica 9
Shallow Trench Isolation (STI) STI Trench etching by RIE oly Oxidation SiO 2 Twi CMOS Trench filling by deosition of oly Si STI -well n + - - - - n + + + STI STI Oxide deosition Shallow (e.g. 0.35m deth) trench isolation in a twinwell rocess allows tighter well sacing. Lezioni di Tecnologie e Materiali er l'elettronica 10
CMOS Process Flow (5) Creation of active devices (e.g. MOS transistors) n n h) Gate (dry) oxidation B n n i) (Selective) Threshold adjustment imlants Lezioni di Tecnologie e Materiali er l'elettronica 11
CMOS Process Flow (6) Poli-Si n n j) Poly deosition and doing n n k) Poly etching: S/D definition SELF - ALIGNMENT Lezioni di Tecnologie e Materiali er l'elettronica 12
CMOS Process Flow (7) n n k) Poly etching: S/D definition (SELF - ALIGNMENT) B Self-alignment oly-si GATE is used as a mask to define the SOURCE/DRAIN regions + + + + n n l) Source/drain MOS imlant Lezioni di Tecnologie e Materiali er l'elettronica 13
Source/Drain Self-Alignment 1. Perfect Alignment 2. Misalignment (no self-alignment) 3. Misalignment (self-alignment) S G D S G D S G D POLY POLY POLY NMOS NMOS NMOS In case of mask alignment error, if source, drain and gate are drawn indeendently, the device may non work at all (case 2.). If source/drain are imlanted/diffused using the gate as a mask, self-alignment occurs and any mask misalignment has minimal influence Lezioni di Tecnologie e Materiali er l'elettronica 14
Self-aligned silicide (salicide) Ti 2Si TiSi 2 Ti reacts with Si to form Ti-silicide. Ti then removed by selective chemical etching. Poly with silicide (TiSi 2 ) has much lower sheet resistance P+oly Rsh with silicide 10W/sq P+oly Rsh without silicide 400W/sq The same is true for and Si diffused regions P+diff.with silicide 10W/sq P+diff.without silicide 150W/sq Lezioni di Tecnologie e Materiali er l'elettronica 15
CMOS Process Flow (8) As - - - - + + n n m) Source/drain nmos imlant - n + - - n + - + + n n n) Inter-layer oxide deosition and via oening Lezioni di Tecnologie e Materiali er l'elettronica 16
CMOS Process Flow (9) Al - n + - - n + - + + n n o) Al deosition Passivation - n + - - n + - + + n n ) Passivation and ad oening Lezioni di Tecnologie e Materiali er l'elettronica 17
Trile-well Process Passivation G D B - n + - - n + - n + n + -well -well dee S - ei A trile-well rocess allows to define a different bulk terminal for NMOS devices built in different -wells. Advantages: o Imroved isolation o Bulk node can be biased at voltages above GND (reduced bulk effect) Lezioni di Tecnologie e Materiali er l'elettronica 18
Dual Damascene Process VIA resist Si 3 N 4 Cu Cu a) VIA resist deosition and definition b) Etch sto definition METAL resist Cu Cu c) etching d) METAL resist deosition and definition Lezioni di Tecnologie e Materiali er l'elettronica 19
Dual Damascene Process (2) Cu Cu e) Etch sto definition f) etching Seed layer Cu Cu g) Etch sto definition h) Seed layer deosition Lezioni di Tecnologie e Materiali er l'elettronica 20
Dual Damascene Process (3) Cu Cu Cu i) Cu j) a) VIA resist deosition and definition b) Etch sto definition c) etching d) METAL resist deosition and definition e) Etch sto definition f) etching g) Etch sto definition h) Seed layer deosition i) Cu deosition j) CMP Lezioni di Tecnologie e Materiali er l'elettronica 21
Latch-u S A B NW + Rw2 + Rs1 Rw1 n well Rs2 Positive feedback loo! B NW Rw1 Latch-u revention: Rs1, Rw1 as small as ossible Low resistivity (high doing) Bulk contact close to active devices Rs2 Rs1 S A Rw2 Lezioni di Tecnologie e Materiali er l'elettronica 22
The MOS of the Future Lezioni di Tecnologie e Materiali er l'elettronica 23
Biolar Technologies Standard Buried Collector + TOP VIEW E B C S Al E B C + CROSS SECTION n ei + + Tecnologie e Materiali er l'elettronica 24
Biolar Process Flow SiO 2 a) Thermal oxidation As / Sb b) Buried layer deosition The buried layer is used to rovide a low imedance ath for the collector current from the active collector area to the collector contact. Tecnologie e Materiali er l'elettronica 25
Biolar Process Flow (2) n ei ~few m buried layer c) N-ei growth The eitaxial layer thickness and resistivity vary: large thickness (~10m) and resistivity (>10Wcm)) are required for high voltage/ower alications B n ei d) P-well isolation definition Tecnologie e Materiali er l'elettronica 26
Biolar Process Flow (3) Isolation diffusions require long time (hours) and high temeratures (1200 C) n ei + + e) Isolation diffusion B n ei + + f) base region definition and imlant Tecnologie e Materiali er l'elettronica 27
Biolar Process Flow (4) + n ei + + g) Base diffusion (drive-in) P / As n ei + + + h) Emitter/collector definition and imlant Tecnologie e Materiali er l'elettronica 28
Biolar Process Flow (5) + n ei + + The transistor base width deends on the difference of the base and emitter diffusion deths. Transistor s f T is inversely roortional to base width. i) Emitter/collector diffusion (drive-in) Al E B C + n ei + + j) Contact oening and metal deosition Tecnologie e Materiali er l'elettronica 29
Biolar Process Flow - Summary As / Sb n ei + + b) d) Al E B C n ei n ei + + + buried layer c) j) a) Thermal oxidation b) Buried layer deosition c) N-ei growth d) P-well isolation definition e) Isolation diffusion f) Base definition and imlant g) Base diffusion (drive-in) h) Emitter/collector definition and imlant i) Emitter/collector diffusion (drive-in) j) Contact oening and metal deosition Tecnologie e Materiali er l'elettronica 30
References Reading Material: Disense di G. Torelli. Introduzione alla tecnologia dei circuiti integrati su silicio. 2006. (IC Technologies) Disense del corso Microfabrication Technology, UCB htt://organics.eecs.berkeley.edu/~viveks/ee143/ Tecnologie e Materiali er l'elettronica 31