Bulk MEMS Fabrication Blog 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Bulk MEMS Fabrication Blog 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Email: Lynn.Fuller@rit.edu Department webpage: http://www.microe.rit.edu Bulk_MEMS_Fabrication_Blog_2017.pptx Page 1

INTRODUCTION This document is a blog addressing the fabrication and testing of the MEMS wafers that were made as part of the MCEE770 MEMS Fabrication class. The students in the class provided individual design layouts that were merged into a single project chip design used to create the reticles for this project. Other documents provide details addressing the design, layout and fabrication for this project. Page 2

INTRODUCTION This document shows layout details for the 2017 Bulk MEMS class project. Pressure sensors and other devices based on a thin diaphragm (10um) of single crystal silicon can be realized. Resistors in the diaphragm will exhibit large changes in resistance in response to stress through the piezoresistance effect. This version of the process has three photolithographic layers applied to the top side of the wafer and one to the back side of the wafer. The starting wafer is a special double sided polished 150mm SOI wafer with 10 um silicon on a 1um buried oxide (BOX) on a 500um handle wafer. Page 3

GENERIC DEVICE CROSS SECTION n - type p - type 1 um BOX 10um hole etched from back side 500um Diffusion (Green) Layer 1.gds #1 Backside Hole (Purple Outline) Layer 2, gds#4 Contact Cut (White) Layer 3, gds#6 Metal (Blue) Layer 4, gds#7 Outline (Yellow Outline), gds# 9 Outline is only for layout, drawing a 4.5mm by 4.5mm outline, the maximum area for individual device designs. Page 4

STARTING WAFER N-type, Phosphorous, (100), 10um+/-1um, 1-10 ohm-cm BOX Oxide 1um +/-5% Handle Wafer Thickness 500um +/- 10um 1-10 ohm-cm 150mm diameter SOI wafers, Polished both top and bottom Page 5

10 mm MEMS MULTICHIP PROJECT TEMPLATE Total 10 mm by 10 mm including 1 mm for sawing into 4 chips. Wafer sawing is easier if all chips are the same size R1 R3 R2 R4 Your Design 4.5mm by 4.5mm design space for each project 4 different projects 5 mm Page 6

10 mm Total 10 mm by 10 mm including 1 mm for sawing into 4 4.5mm by 4.5 mm chips. 2017 BULK MEMS CHIP FINAL LAYOUT Page 7

PRESSURE SENSOR + HEATER Pressure Sensor Heater Overlay and Resolution Diffused Resistors Length = 200um Width = 20 um Note: upper left is not connected so individual resistances can be measured. Page 8

LAYOUTS USING MENTOR GRAPHICS SOFTWARE Students did their design and layout using the computers in our VLSI Lab. Mentor Graphics software, Pyxis layout editor Page 9

MASK ORDER FORM Dr Fuller RIT BULK-MEMS-2017-Final.gds 4 10mm x 10mm x X yes, 4 levels per plate Page 10

MASK ORDER FORM DETAILS Layer Reticle Name Design.gds Layer # s Boolean Function Dark/ Clear Comment 1 st Diffusion 1 1 Inverted Dark Mirror 2 nd Cut 6 6 Inverted Dark Mirror 3 rd Metal 7 None Clear Mirror 4 th Hole 2 2 Inverted Dark No mirror Hole pattern is put on the back side of the wafer so it does not get mirrored. All the other layers are mirrored. Design Layer 9 Out (outline) is not used. It is only for placement of projects on the multi-project reticle template. Page 11

LAYER 1 DIFFUSION AND LAYER 2 CUT DIFFUSION.gds #1 CUT.gds #6 Page 12

LAYER 3 METAL AND LAYER 4 BACKSIDE HOLE METAL.gds #7 BACKSIDE HOLE.gds #4 Page 13

MASK PROCESS FLOW Data Prep Barcode, Titles, other Plus Layer Files CAD GDSII CATS Layer Files Job Files Pyxis by Mentor Graphics Computer Aided Transcription Software Etch Cr Inspect Develop Expose Coat Plate Maskmaking Inspect Clean Ship out This process can take weeks and cost between $1000 and $20,000 for each mask depending on the design complexity. Page 14

HEIDELBERG LASER WRITER The masks were made using the Heidelberg LASER writer at RIT. This tools is capable of writing on glass or quartz plates or wafers with spot size down to 0.5um. Page 15

4 LEVELS PER PLATE RETICLE FOR ASML Metal Four Levels on One plate Holes Contact Cut Layer Diffusion Layer Page 16

RETICLE FOR ASML CHROME SIDE NON-CHROME SIDE Page 17

BULK MEMS PROCESS FLOW 1. Starting wafer, 10um SOI 2. Grow 5000Å oxide, Recipe 350 3. PH03 level 0, Marks 4. ET06 Wet Etch Alignment Marks 5. Strip resist and clean 6. Grow another 5000Å oxide, Recipe 350 7. PH03 level 1 Diffusion + Hand Coat back of wafer with PR + oven bake 8. ET06 Wet Etch Oxide 9. ET07 Resist Strip, Solvent Strip 10. CL01- RCA Clean 11. IM01 - Implant 2E15, B11, Energy 80Kev 12. OX05 3000Å Steam Oxide, Anneal 13. PH03 level 2 Contact Cut + Hand coat back of wafer with PR + oven bake 14. ET29 Etch CC Oxide 15. ET07 - Resist Strip, Solvent Strip 16. CL01 RCA Clean two HF dips 17. Sputter metal 1um, 30min 18. Coat Backside with 2um Oxide - TEOS 19. PH03 level 3 Metal 20. ET55 Metal Etch wet 21. Strip Resist Solvent Strip 22. Sinter wafers 23. PH03 level 4 Back Hole +Hand Coat Front with PR +oven bake 24. Etch Oxide in Holes on Back 25. Solvent Strip Resist, Rinse, SRD 26. STS Etch Silicon from Back 27. TE01 wafer level testing 28. SAW1 Saw wafers 29. Packaging and Testing 30. Documentation 12-8-17 Page 18

LAB SCHEDULE Monday 9:00 am Sai Rohit, Nicholas, Adam, Justin Tuesday 1:00 pm Kavana, Kartik, Jeff Friday 8:30 am Matthew, Eddie, Ryan, Arshia Students are expected to come to lab once per week. What was done to the wafers is documented in this Blog so that all students can have data and know about the progress. The Blog is updated after each lab session. Page 19

1 ST OXIDE GROWTH Today s goal: Step 1 and 2, Get starting wafers and grow 5000Å Oxide 1. Starting wafers were inspected and front side was identified. Front and back are both polished. The front was identified by the supplier in the shipping box. We could also see a ring around the wafer edge on the front side. 2. Recipe 350 on the Bruce Furnace will grow 5000Å oxide. Mean 5046Å Authors: Amendola, Chimakurthi, Rosenfeld, Zwick 13 Nov 2017 Page 20

1 ST OXIDE GROWTH Oxide Measurements Contour map Oxide Measurements 3D map 13 Nov 2017 Authors: Amendola, Chimakurthi, Rosenfeld, Zwick Page 21

ZERO LEVEL LITHOGRAPHY Today s goal: Steps 3,4,5,6 Resist coat, ASML Zero marks photo & develop, BOE etch, and Oxide Growth on two wafers. 1. Coated Ori620 Resist using Recipe Coat on the SSI Track 2. Measured Resist thickness on SpectraMap, 10,001Å 3. ASML Zero mark exposure. 4. Developed on SSI track using recipe DEVELOP. 5. 10:1 BOE Etch of alignment marks, 10 min, Rinse, SRD. 6. Strip Resist and Clean Wafers 7. Bruce Furnace Tube 1: Recipe #350, 5000 Å growth Authors: Amendola, Chimakurthi, Rosenfeld, Zwick 13 Nov 2017 Page 22

INSPECT ALIGNMENT MARKS Today s Goal: Verify that the alignment marks are good following second oxide growth. The purple lines have 5000Å oxide on silicon. The Blue/Green area has 8000Å oxide on silicon. There is a step in the silicon of 1200Å necessary for the ASML diffraction grating for alignment. ASML Alignment Marks on Device Wafers 8000Å 1200Å Step 5000Å Oxide Silicon Authors: Huang, Sasson, Thorna, Rolleston November 17, 2017 Page 23

EXPOSING GLASS WAFERS ON THE ASML Today s Goal: No reticle available today, so we can not do the next steps in the process. Instead we work on a way to verify alignment of back side pattern to front side pattern. We verified that the ASML will accept a glass wafer and expose it using only the ASML wafer flat pre align capability. The idea is to use the photoresist pattern on the glass wafer to check alignment by simply placing the glass wafer on top of a patterned wafer. Blank Glass wafer Authors: Huang, Sasson, Thorna, Rolleston November 17, 2017 Page 24

LEVEL 1 PHOTOLITHOGRAPHY Today s Goal: Step 7, Level 1 photolithography (Diffusion), hand-coat back of the wafer with photoresist, oven bake the wafer. Coated the wafers with photoresist OiR-620 on SSI Coat and Develop Track (1). (While coating the device wafers one after the other, both the wafers got stuck together in the HMDS vapor prime. This happened because these wafers were lighter in weight and thinner than the usual wafers that the track is programmed to work with. Later the wafers got coated properly.) Exposed the Photo level-1 (Diffusion) on the device wafers using ASML: Stepper Job: MCEE770_MEMS4X Energy: 250 mj/cm 2 Developed the wafers on SSI track. SSI track used to coat and develop wafers. Authors: Amendola, Chimakurthi, Rosenfeld, Zwick November 20, 2017 Page 25

LEVEL 1 PHOTOLITHOGRAPHY Today s Goal: Step 7, Level 1 photolithography (Diffusion), hand-coat back of the wafer with photoresist, oven bake the wafer. Wafer in the SSI track #2 getting hard baked after getting developed. The diffusion regions in Adam s design patterned on the wafer after photo level-1. Authors: Amendola, Chimakurthi, Rosenfeld, Zwick November 20, 2017 Page 26

HAND-COAT WAFERS AND OVEN BAKE Today s Goal: Step 7, Level 1 photolithography (Diffusion), hand-coat back of the wafer with photoresist, oven bake the wafer. The back side of the device wafers were hand-coated with photoresist OiR-620. After coating the wafers, they were baked in Blue M oven for 15 minutes at 90. Placing the wafer on the spintrack with back-side up to coat it with photoresist. Blue M Oven to bake the wafers for 15 minutes at 90. Authors: Amendola, Chimakurthi, Rosenfeld, Zwick November 20, 2017 Page 27

Today s Goal: Step 8, Wet etch oxide, ET06- Wet oxide etch in 10:1 BOE (586Å/min) for 16 minutes. Rinse and SRD. WET ETCH OXIDE Authors: Rolleston November 21, 2017 Page 28

SOLVENT STRIP RESIST AND RCA CLEAN Today s Goal: Step 9 and 10, solvent strip, RCA clean device wafers ET07- Solvent strip for 10min, rinse for 5min CL01- RCA clean Heated PRS-2000, 90 C RCA clean Authors: Rolleston November 21, 2017 Page 29

ION IMPLANT B11 FOR RESISTORS Today s Goal: Step 11, Ion Implant Boron, B11, Dose of 1E15, 100KeV Set up implanter. We obtained a beam current of 300uA, which gave us an implant time of ~10 min. Varian 350D Remote Control One wafer was completed then the Ion Implanter went down and the second wafer was not done. Varian 350D End Station Authors: Jeff Salzmann, Casey Gonta November 21, 2017 Page 30

GROW 3000Å OXIDE Today s Goal: Step 12, Grow 3000A Oxide in the one wafer that was ion implanted last week Recipe #330, 1100C 50 min, Steam Authors: Adam Rosenfeld November 28, 2017 Page 31

OXIDE GROWTH AND PHOTO LEVEL 2 Today s Goal: Steps 12,13,14; Oxide Growth, Resist coat, ASML Level 2 contact cut photo & develop, Hand coat back of the wafer, Oven bake and BOE etch on one wafer. 1. Bruce Furnace Tube: Recipe #330, 3000 Å growth completed 2. Coated Ori620 Resist using Recipe Coat on the SSI Track. 3. ASML level 2 contact cut exposure. 4. Developed on SSI track using recipe DEVELOP. 5. Hand coated back of the wafer and oven bake @ 110C for 20 min. 6. 10:1 BOE Etch the wafer for 10 min, Rinse in water for 5 min. No overlay error seen in x or y Spin Coat Resist Box Oven Authors: Jeff, Kavana, Kartik Wafer after etching Contact cut oxide November 28, 2017 Page 32

OXIDE GROWTH AND PHOTO LEVEL 2 Authors: Jeff, Kavana, Kartik November 28, 2017 Page 33

IMPLANTER FIXED WORK ON WAFER LEFT BEHIND Today s Goal: One wafer did not get implanted because the implanter went down after the first wafer was implanted. Today, now that the implant is fixed, we did two steps to move the one wafer forward. Step 11, Ion implant wafer, B11, 100KeV, Dose= 1E15 cm-2 Step 12, Grow 3000Å Oxide, Recipe #330, 1100C 50 min, Steam This wafer is still behind the first wafer because we moved the first wafer forward several steps. Next for this wafer is to do the contact cut lithography, etch the contact cuts, strip the resist and deposit metal. Authors: Nicholas November 30, 2017 Page 34

VERIFYALIGNMENT (BACK OF WAFER TO FRONT) Today s Goal: Earlier we learned that we could expose a glass wafer using the ASML stepper. The idea was to coat the glass wafer with photoresist, expose it with our reticle level 4 for back side holes, and after developing the glass wafer lay it on top of one of our patterned silicon wafers to see if hole pattern aligns with the resistors on the front side of the wafer. The alignment is based on using the ASML pre align sensor which is specified to be ~+/- 20um using the wafer flat only. The reticle patterns are normally mirrored prior to writing the mask so that the images and lettering are right reading on the front of the wafer. The reticle pattern for the back side of the wafer are not mirrored. We placed the glass wafer on top of a patterned wafer by hand and using a microscope verified that the reticles were made correctly and the alignment will be good. (better than by hand) Authors: Eddie November 30, 2017 Page 35

RESIST STRIP, RCA CLEAN (TWO HF DIPS) Today s Goal: The one wafer that already has the contact cuts etched is ready for steps 15 and 16, resist strip and RCA clean. Step 15: Resist strip is done in the solvent strip because there is photoresist on both the front and back side of the wafer. 5 min in bath 1, 5 min in bath 2, 5 min in DI, and SRD Heated PRS-2000, 90 C Step 16: RCA clean prior to metal deposition. Normal RCA clean but with a 2 nd HF dip at the end of the process to remove the chemically grown oxide from the SC2 bath. Followed by SRD. Wafers now ready for Aluminum deposition. Authors: Nicholas November 30, 2017 Page 36

ALUMINUM METAL DEPOSITION Today s Goal: Step 17: sputter Aluminum CVC 601 sputter tool No Heater during pump down 2 hour pump down time 5 min pre sputter at 2000 watts 30 min sputter of aluminum at 2000 watts, 5mTorr Measure thickness after patterning. Target 1um Authors: Jeff November 30, 2017 Page 37

P5000 DEPOSIT 2UM TEOS OXIDE Today s Goal: Step 19: Backside Oxide Deposition for deep etch mask AMT P5000, Chamber A TEOS Backside of wafer had about 1.0 µm thermally grown SiO 2 Need additional oxide of about 2.0 µm deposited to ensure it would survive deep etch After 2 runs of (nominal) 1M TEOS LS, oxide thickness measured 2.6 µm (Spectramapper) Ran additional 0.75µm deposition; final thickness measured 3.3 µm (Spectramapper) Page 38

METAL LITHOGRAPHY Today s Goal: Step 18: Metal Lithography, Level 3 Authors: Jeff November 30, 2017 Page 39

METAL LITHOGRAPHY Today s Goal: Step 18: Metal Lithography The Authors: Jeff November 30, 2017 Page 40

METAL ETCH Today s Goal: Step 19: Aluminum Wet Etch 50 C ~1.5 min. Visual end point (wafer turns dark) Authors: Patsy November 30, 2017 Page 41

AFTER SOLVENT STRIP AND SRD Today s Goal: Step 20: Strip resist from front and back of wafer 90 C 5min, 5min, DI water 5 min, SRD Authors: Jeff November 30, 2017 Page 42

AFTER SOLVENT STRIP AND SRD Authors: Jeff November 30, 2017 Page 43

Today s Goal: Step 19: Sinter Wafers SINTER WAFERS Recipe #99 Sinter at 400 C for 20 min., N2/H2 Authors: Eddie, Matt November 30, 2017 Page 44

DECEMBER 4 TH : STEPS 22 & 23 Today s Goal: Steps 22 & 23; Coat, Lithography, Develop, Oven Bake, BOE Etch. Performed Step 22 (PH03): Level-4 lithography (back hole), hand coat PR on the front side, oven bake Performed Step 23: Etch Oxide in holes on back. Authors: Chimakurthi, Amendola, Rosenfeld, Zwick December 4, 2017 Page 45

TRIALS AND TRIBULATIONS First attempt: Hand coated the back of the wafer, covered the carrier with tinfoil(to avoid the white light) and pre-exposure baked for 10min at 90C. Then exposed using the ASML[MEMS4X, MCEE7701177, TEST4]. Hand developed in CD-26 for 45sec and water rinsed for 30sec. This dissolved all the photoresist. Restart: Solvent stripped(90c 5min, 5min, DI water 5min) and SRD Second Attempt: Wafers coated & developed using the SSI trac, as well as Exposed. Before sticking the device wafer with the other coated wafer, we hand coated PR on the front side of the device wafer and then tried to stick them together in the oven. For the wafers to be back etched using STS, we had to use a different wafer (coated with PR) and stick them both (front of our device wafer is stuck with the other wafer) in the oven (@90 C for 10 min). Finally, the wafers were stuck, and the holes were etched in the back in the BOE solution at the end. The wafer is now ready for the STS etch. Page 46

DEEP REACTIVE ION ETCH Today s Goal: Step 24: STS Etch Silicon from Back STS ASE Deep Silicon Etch 21 seconds/cycle Autotune match on coil generator Manually tune match on platen C 4 F 8, SF 6, O 2, and Ar process gases Handle thickness 525µm Cycle etch depth ~ 1µm 525 cycles Total time 3 hours, 10 minutes Author: Salzmann December 5, 2017 Page 47

DEEP REACTIVE ION ETCH Today s Goal: Step 24 (continued): Remove resist 1. PRS-2000 wet strip 20 minutes @ 90ºC 2. DI water rinse (10 min @ room temperature) 3. IPA dry 4. Ash using recipe FFF (total ash time 1600 seconds) Ash was ineffective; robot mashed wafer after last iteration of ashing. DRIE nearly finished After 900 seconds ashing Author: Salzmann December 5, 2017 Page 48

DEEP REACTIVE ION ETCH Pictures of etched holes in Microelectronic backside Engineering of wafer Author: Salzmann December 5, 2017 Page 49

Today s Goal: Test some devices TESTING The first test we did was to place the wafer on a microscope stage and apply vacuum to the back side. You can see the diaphragm bend down and evaluate the alignment of the hole on the back side of the wafer with the structures on the front of the wafer. Alignment seems to be perfect. Movie as vacuum is applied and released repeatedly Picture with vacuum applied Author: Matt December 5, 2017 Page 50

Today s Goal: Test some devices TESTING More movies showing diaphragm movement as vacuum is applied to back of wafer. Different structures stiffen the diaphragm so that the bending is concentrated at the edges. Author: Matt December 5, 2017 Page 51

TESTING Today s Goal: Test some devices Next we do electrical tests to measure resistance and determine sheet resistance (knowing the resistor L and W. We also apply a DC voltage to opposite corners of the wheatstone bridge and measure the voltage at the two output nodes. The voltages should be equal to each other and approximately ½ of the applied voltage. The difference is the offset voltage. Offset could be due to the layout design or residual stresses. Author: Matt December 5, 2017 Page 52

TESTING Today s Goal: Test some devices 5 Volts +5 Volts R1 R3 R2 R4 Vo2 R1=427 R3=427 Vo1=2.5v Vo2=2.5v R2=427 R4=427 Vo1 Gnd Gnd Author: Matt December 5, 2017 Page 53

Today s Goal: Test some devices TESTING To do testing at different pressures the devices need to be packaged. MEMS Pressure Sensor Output Output Voltage (mv) 100 90 80 70 60 50 40 30 20 10 0 y = 0.0002x 2 + 0.586x + 60.593 0 10 20 30 40 50 Pressure (psi) Author: Matt December 5, 2017 Page 54

TESTING Today s Goal: Process wafer number 2 which was delayed at ion implant do to an equipment problem. This wafer was at step 11 Ion implant. That was done once the implanter was back up. It progressed quickly to step 18 which is sputter aluminum. The aluminum sputter was done. We learned that we do not want to have photoresist on the wafer when it is in the STS etcher for three hours to etch the holes through the wafer. The wafer must get hot and the photoresist is difficult (impossible) to remove after the etch. Instead of photoresist mask we decided to PECVD 2um of oxide from TEOS on the back of the wafer to act as a hard mask (plus the 1um of thermal oxide that is already there) Author: Matt December 5, 2017 Page 55

METAL DEPOSITION Today s Goal: Step 17: Level 3- Metal CVC601, Al/Si Sputter Deposition Base Pressure 6.0 E-06 Torr 20 sccm Ar, 5 mtorr deposition pressure. 5 minute presputter, 30 minute deposition @ 2000W Result: 1.12 µm, measured on P-2 profilometer Author: Salzmann December 7, 2017 Page 57

BACKSIDE OXIDE DEPOSITION Today s Goal: Step 18: Backside Oxide Deposition for deep etch mask AMT P5000, Chamber A TEOS Backside of wafer had about 1.0 µm thermally grown SiO 2 Need additional oxide of about 2.0 µm deposited to ensure it would survive deep etch After 2 runs of (nominal) 1M TEOS LS, oxide thickness measured 2.6 µm (Spectramapper) Ran additional 0.75µm deposition; final thickness measured 3.3 µm (Spectramapper) Author: Salzmann December 7, 2017 Page 58

METAL LITHOGHRAPHY, ETCH, SOLVENT STRIP Today s Goal: Process wafer number 2 which was delayed at ion implant do to an equipment problem. Step 19, 20, 21 Coat.rcp Expose Level 3 Develop.rcp Aluminum etch 6min, 50C Solvent strip, 5min., 5min., Rinse 5min., SRD Author: Matt, Eddie, Patsy, Casey, Ryan December 8, 2017 Page 59

SINTER WAFER Today s Goal: Process wafer number 2 which was delayed at ion implant do to an equipment problem. Step 22 Sinter 400C, 20 min Sintering Recipe 99 Author: Matt, Eddie, Patsy, Casey, Ryan December 8, 2017 Page 60

LITHOGRAPHY FOR BACKSIDE HOLES, ETCH OXIDE Today s Goal: Process wafer number 2 which was delayed at ion implant do to an equipment problem. Step 23, 24 Step 23 - Level 4 Lithography for back side of wafer SSI Coat.rcp ASML Expose level 4 SSI Develop.rcp Coat front side by hand spinning Oven bake Step 24 Wet Etch in 5.2:1 BOE for 16 min. Author: Matt, Eddie, Patsy, Casey, Ryan December 8, 2017 Page 61

STS ETCH DONE STS ASE Deep Silicon Etch 21 seconds/cycle Autotune match on coil generator Manually tune match on platen C4F8, SF6, O2, and Ar process gases Handle thickness 525µm Cycle etch depth ~ 1µm 600 cycles Total time 3 hours And 20 minutes Authors: Amendola, Chimakurthi, Rosenfeld, Zwick 11 DEC 2017 Page 62

BACK SIDE OF COMPLETED WAFERS Page 63

COMPLETED WAFER MOVIE Page 64