Surface MEMS Fabrication Blog Dr. Lynn Fuller, Adam Wardas Webpage:

Similar documents
MEMS Surface Fabrication

Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

Surface MEMS Fabrication Details Dr. Lynn Fuller, Adam Wardas, Casey Gonta, Patsy Cadareanu

Bulk MEMS Fabrication Blog 2017 Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller

Summary of Selected EMCR650/731 Projects for Jeremiah Hebding Dr. Lynn Fuller

Summary of Selected EMCR732 Projects for Spring 2005 Mike Aquilino Dr. Lynn Fuller

Dr. Lynn Fuller, Motorola Professor Steven Sudirgo, Graduate Student

2015 EE410-LOCOS 0.5µm Poly CMOS Process Run Card Lot ID:

CMOS Factory Laboratory

Wafer Cleaning and Oxide Growth Laboratory Dr. Lynn Fuller Webpage:

Microelectronic Device Instructional Laboratory. Table of Contents

Dr. Lynn Fuller Webpage:

LAM 490 Etch Recipes. Dr. Lynn Fuller

Surface micromachining and Process flow part 1

RIT s Sub-CMOS Process (Leff < 1.0 µm) Dr. Lynn Fuller Suraj Bhaskaran and Ivan Puchades

Lab #2 Wafer Cleaning (RCA cleaning)

RIT s Sub-CMOS Process (Leff < 1.0 µm) Dr. Lynn Fuller Suraj Bhaskaran and Ivan Puchades

Process Improvement Projects May 2006 Dr. Lynn Fuller

Welcome MNT Conference 1 Albuquerque, NM - May 2010

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers

Isolation Technology. Dr. Lynn Fuller

Drytech Quad Etch Recipes Dr. Lynn Fuller Mike Aquilino Microelectronic Engineering

Process Development of Sidewall Spacer Features for Sub-300nm Dense Silicon FinFETs

Surface Micromachining

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

EE 143 MICROFABRICATION TECHNOLOGY FALL 2014 C. Nguyen PROBLEM SET #9

The Physical Structure (NMOS)

3.155J / 6.152J MICROELECTRONICS PROCESSING TECHNOLOGY TAKE-HOME QUIZ FALL TERM 2003

Fabrication and Layout

EE C245 / ME C Cory. symmetric in both. polysilicon.

EECS130 Integrated Circuit Devices

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis

Process Flow in Cross Sections

4/10/2012. Introduction to Microfabrication. Fabrication

Chapter 2 Manufacturing Process

Today s Class. Materials for MEMS

Design and Fabrication of a Micromechanical Pressure Sensor

INTEGRATED-CIRCUIT TECHNOLOGY

Physical Vapor Deposition (PVD) Zheng Yang

TANOS Charge-Trapping Flash Memory Structures

Mostafa Soliman, Ph.D. May 5 th 2014

Chemical Vapor Deposition

LAM4600 Plasma Etch Tool Recipes Dr. Lynn Fuller

How To Write A Flowchart

CyMOS process Spring 2016 Iowa State University

A Novel Low Temperature Self-Aligned Field Induced Drain Polycrystalline Silicon Thin Film Transistor by Using Selective Side-Etching Process

Chapter 3 Silicon Device Fabrication Technology

Microstructures using RF sputtered PSG film as a sacrificial layer in surface micromachining

LAM4600 Plasma Etch Tool Recipes Dr. Lynn Fuller Webpage:

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam

Lecture #18 Fabrication OUTLINE

VLSI INTRODUCTION P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT

EE 330 Lecture 9. IC Fabrication Technology Part 2

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to

Development of Silicon Pad and Strip Detector in High Energy Physics

Chapter 4 Fabrication Process of Silicon Carrier and. Gold-Gold Thermocompression Bonding

Lecture 1A: Manufacturing& Layout

6.777J/2.732J Design and Fabrication of Microelectromechanical Devices Spring Term Solution to Problem Set 2 (16 pts)

NMOS Transistor Design and Fabrication for S-Parameter Extraction

Semiconductor Device Fabrication

Via Fill in Small Trenches using Hot Aluminum Process. By Alice Wong

EE C245 ME C218 Introduction to MEMS Design Fall 2011

Microfabrication of Integrated Circuits

Complexity of IC Metallization. Early 21 st Century IC Technology

Microelectromechanical Systems (MEMs) Unit Processes for MEMs Measurement

Etching Gold using Oxford Ion Mill Tool

EE 330 Lecture 9. IC Fabrication Technology Part II. -Oxidation -Epitaxy -Polysilicon -Planarization -Resistance and Capacitance in Interconnects

PRELIMINARY FORMATION OF DEEP TRENCH C~P~CITORS

Chapter 2 MOS Fabrication Technology

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Single-digit-resolution nanopatterning with. extreme ultraviolet light for the 2.5 nm. technology node and beyond

IC/MEMS Fabrication - Outline. Fabrication

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

MEMS II: January 23. Lab 1: Pop-up mirror - PolyMUMPS - Thermal actuators - Mirror CoventorWare

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

Total Points = 110 possible (graded out of 100)

EE 330 Lecture 8. IC Fabrication Technology Part II. - Oxidation - Epitaxy - Polysilicon - Interconnects

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

Bruce Furnace Recipes Dr. Lynn Fuller Webpage: Electrical and Microelectronic Engineering

Fabrication Technology, Part I

Selective-Area Atomic Layer Deposition (SA-ALD) of Titanium Dioxide (TiO 2) using Poly(methyl methacrylate) (PMMA) Michael Tu 5/12/2016

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

Photolithography I ( Part 2 )

Brian Izzio 5th Year Microelectronic Engineering Student. Rochester Institute of Technology

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

RIT s Advanced CMOS Process l=0.25 µm, L poly = 0.5 µm, L eff = 100nm

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

Czochralski Crystal Growth

DEPARTMENT OF MECHANICAL SCIENCE AND ENGINEERING UNIVERSITY OF ILLINOIS. ME498 PV Class. Laboratory Manual on Fundamentals of Solar Cell Manufacturing

EE 330 Lecture 8. IC Fabrication Technology Part II. - Masking - Photolithography - Deposition - Etching - Diffusion

Review of CMOS Processing Technology

Thermal Oxidation and Growth of Insulators (Chapter 3 - Jaeger 3) Key advantage of Si: Oxidation of Si into SiO 2 (glass) Major factor in making

Because of equipment availability, cost, and time, we will use aluminum as the top side conductor

Micro-Scale Engineering I Microelectromechanical Systems (MEMS) Y. C. Lee

ECE 440 Lecture 27 : Equilibrium P-N Junctions I Class Outline:

Lecture 22: Integrated circuit fabrication

Process Integration. MEMS Release Techniques Sacrificial Layer Removal Substrate Undercut

Transcription:

ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Surface MEMS Fabrication Blog Dr. Lynn Fuller, Adam Wardas Webpage: http://people.rit.edu/lffeee 82 Lomb Memorial Drive Rochester, NY 14623-5604 Tel (585) 475-2035 Email: Lynn.Fuller@rit.edu Department webpage: http://www.microe.rit.edu MEMS_Fabrication_Blog_2015.ppt Page 1

INTRODUCTION This document is a blog addressing the fabrication and testing of the MEMS wafers that were made as part of the MCEE770 MEMS Fabrication class. The students in the class provided individual design layouts that were merged into a single project chip design used to create the reticles for this project. Other documents provide details addressing the design, layout and fabrication for this project. Page 2

PROCESS DESCRIPTION Mechanical Poly2 Layer Bottom Poly1 Sacrificial Oxide Starting Wafer Metal Field Oxide This is a surface micromachine process with two layers of polysilicon and one layer of metal. Poly2 can be suspended above the wafer allowing for structures that can move. The two poly layers can cross without connection or can be connected through anchor holes. The metal layer can connect to Poly2 through a via or to Poly1 through via and anchor holes. The yellow layers are silicon nitride. Page 3

LAYOUTS USING MENTOR GRAPHICS SOFTWARE Students did their design and layout using the computers in our VLSI Lab Page 4

MENTOR GRAPHICS LAYOUT OF CANTILEVER The cantilever shown is anchored on the left and free to move on the right. The design includes resistive and capacitive position sensors and electrostatic actuation. The device can be used as an accelerometer. Page 5

2015 MEMS MULTICHIP PROJECT DESIGN Page 6

MASK ORDER FORM Dr Fuller RIT mems-2015-final.gds 8 16.5mm x 16.5mm mems-2015-final x Page 7

MASK ORDER FORM DETAILS Reticle Number Reticle Name Design Layer # s Boolean Function Dark/ Clear 1 Poly1 1 None Clear 2 SacOx 2 None Clear 3 Anchor 3 3 Inverted Dark 4 No Implant 15 None Clear 5 Poly2 4,16 4 AND (16 Inverted) Clear 6 Cut 6 6 Inverted Dark 7 Metal 7 None Clear 8 Release 5 Inverted Dark Comment Design Layer 9 Out (outline) is not used. It is only for placement of projects on the multi-project reticle template. cp <filename>.gds /dropbox/masks Page 8

MASK PROCESS FLOW Data Prep CAD IC Graph by Mentor Graphics GDSII CATS Computer Aided Transcription Software MEBES File MEBES Job Etch Cr Inspect Develop Expose Coat Plate Maskmaking Inspect Clean Ship out This process can take weeks and cost between $1000 and $20,000 for each mask depending on the design complexity. Page 9

MEBES - Manufacturing Electron Beam Exposure System The masks were made using the MEBES electron beam writer at RIT. This tools is capable of writing on glass or quartz plates or wafers with spot size down to 0.1um. Page 10

CLEAR FIELD RETICLE FOR ASML Poly One Non-Chrome Side Metal Chrome Side Page 11

SURFACE MEMS 2015 PROCESS 1. Starting wafer 2. PH03 level 0, Marks 3. ET29 Zero Etch 4. ID01-Scribe Wafer ID, D1 5. ET07 Resist Strip, Recipe FF 6. CL01 RCA clean 7. OX04 6500Å Oxide Tube 1 8. CV01 LPCVD Poly 5000Å 9. IM01 Implant P31, 2E16, 60KeV 10. PH03 level 1 Poly-1 11. ET08 Poly Etch 12. ET07 Resist Strip, Recipe FF 13. CL01- RCA Clean 14. OX05 700Å Dry Oxide 15. CV02- LPCVD Nitride 4000Å 16. PH03 level 2 Anchor 17. ET29 Etch Nitride 18. ET07 - Resist Strip, Recipe FF 19. CL01 RCA Clean 20. CV03-TEOS SacOx Dep 1.75um 21. PH03 level 3 SacOx Define 22. ET06 - wet etch SacOx Define Etch 23. ET07- Resist Strip, Recipe FF 24. CL01 RCA Clean 25. CV01-LPCVD Poly 2um, 140 min 26. PH03 - level 4 No Implant 27. IM01-P31 2E16 100KeV 28. ET07 Resist Strip, Recipe FF 29. CL01 RCA Clean 30. OX05-500Å pad oxide 31. CV02 2000Å nitride 32. PH03 - level 5 Poly2 33. ET29 Plasma Etch Nitride 34. ET06 Wet Etch pad oxide 35. ET68 - STS Etch Poly2 36. ET07 - Resist Strip, Recipe FF 37. PH03 level 6 Contact Cut 38. ET29 Etch Nitride Contact Cut 39. ET06 Etch Oxide Contact Cut 40. ET07 Resist Strip, Recipe FF 41. 39. CL01 RCA Clean two HF 42. ME01 Metal Deposition - Al 43. PH03 level 7 Metal 44. ET55 Metal Etch - wet 45. ET07 Resist Strip 46. PH03 level 8 Release 47. ET66 Final SacOx Etch 48. ET07 - Resist Strip, Recipe FF 49. SEM1 Pictures 50. TE01 - Testing 9-13-15 Page 12

ZERO ETCH AND PHOTORESIST STRIP Today s Goal: Coat the wafers with photoresist, expose with ASML stepper, develop and plasma etch ASML alignment marks on six wafers. Etch Silicon using Drytek Quad 482 Etcher Cleaning of chamber for 5 min. in 02 plasma Etching the device wafer for 2 min. in CF4, CHF3 and O2 plasma Inspection of alignment marks on wafer Removal of Photoresist using GaSonics - (recipe FF) Microscope images of alignment marks before and after P.R. removal Before P.R. removal After P.R. removal Drytek Quad GaSonics PR Asher Authors: Abhinav, Nikhil, Ranjana, Shruthi, Yamini October 19, 2015 Page 13

RCA CLEAN AND OXIDE GROWTH Today s Goal: Remove organic and metallic contaminants from wafers with RCA clean, steam oxide growth of 6500Å of oxide in Bruce Tube 1. Performed step 6: CL01 (RCA clean) Cleaned four wafers from lot Processed through SRD afterwards Adam developed and etched the other two wafers in the lot Performed step 7: OX04 (oxide growth) Procedure used to grow 6500A of oxide Measured Oxide Thickness: Mean : 6597.7 Å Std Dev. = 0.38% CL01 RCA Clean Authors: Mattias Herrfurth, Corey Shay OX04 oxide growth October 20, 2015 Page 14

LPCVD POLY DEPOSITION Today s Goal: Deposit polysilicon using the ASM LPCVD Tube 2 for a target thickness of 5000 Å. Step 8: CV01 LPCVD Poly 5000A - 3 wafers were done during this time - Other 3 wafers were processed Friday morning Parameters - 100 sccm of SiH 4 - Time: 36 mins - Temp: 650 C Wafer ID Mean Thickness (A) Standard Deviation (%) D4 5572 6.104 D5 5633.9 7.627 D6 4691.5 26.178 Results of Poly Deposition Loading Wafer into the ASM LPCVD Tube 2 Authors: Adam Banees, Dustin Schroeder October 22, 2015 Page 15

POLY THICKNESS MEASUREMENT Today s Goal: Measure the mean and the standard deviation of the poly thickness of 3 of the wafers using the SpectraMap Auto SM300. Target thickness was 5000Å. Wafer ID Mean Thickness (Å) Standard Deviation (%) D1 5108.4 27.2 D2 4950.6 22.6 D3 4192.8 28.3 Wafer Topology Output of SpectraMap Loading Wafer into the SpectraMap Authors: Megan Ehrhart, Miaotian Wang October 23, 2015 Page 16

ION IMPLANTATION Today s Goal: Ion Implant of P31 ions using the Varian 350D ion implanter. Setting up the Varian 350D Ion Implanter Author: Aslesh Shetty October 23, 2015 Page 17

ION IMPLANT POLY 1 Today s Goal: Implant Poly1 with Phosphorus at 2e16 Dose. Time spent to achieved this dose was calculated. Dose Area q time = I Dose: 2e16 ions/cm 2 Area: 196 cm 2 q: 1.6e-19 C I: 1mA time = 627.2 sec ~ 10.5 minutes Before and After Implant Wafer going into Ion Implanter Authors: Megan Ehrhart, Miaotian Wang October 23, 2015 Page 18

PHOTORESIST COATING FOR POLY1 PATTERNING Today s Goal: Coat the wafers with photoresist, P.R., measure thickness of the coating, expose with ASML stepper, post exposure bake and post development hard bake. Coated device and dummy wafers with P.R. Recipe Standard coat, 3250 RPM, 30 sec. Photoresist OIR 620 Measured thickness of P.R., SpectraMap Expose P.R. with ASML stepper Dose 250mJ/cm 2, Focus Offset 0.5 μm, NA 0.48 Post Exposure bake - 110 C, 60 sec. Post development hard bake - 140 C P.R. Thickness Data from SpectraMap Gives Mean = 10200Å P.R. Overlay and Resolution Pattern for Poly 1 Authors: Abhinav, Nikhil, Ranjana, Shruthi, Yamini October 26, 2015 Page 19

Wafers 5 and 6 poly etched on Drytek Quad. Recipe: FACCPOLY SF6: 30 sccm CHF3: 30 sccm O2: 5 sccm Ar: 0 sccm Pressure: 40mT RF Power: 160w Etch Rate: 1250 A/min POLY 1 ETCH AND RESIST STRIP Today s Goal: Etch Poly 1 with the Drytek Quad and strip the resist with an oxygen plasma produced in a GasSonics Aura 1000 Asher. Wafer 6 over etched, field oxide reduced to 5500Å, green. Wafer 5 etched for 4 min 30 sec with field oxide of 6100Å. Carnation pink. Chamber Plasma During Poly Etch Authors: Corey Shay, Mattias Herrfurth Chamber 2, O2 clean done before processing wafers. October 27, 2015 Page 20

AFTER POLY 1 ETCH AND RESIST STRIP Pictures of some of the devices on wafer 5 after etch and resist strip Authors: Corey Shay, Mattias Herrfurth October 27, 2015 Page 21

RCA CLEAN AND 700Å OXIDE GROWTH Today s Goal: Remove organic and metallic contaminants from wafers with RCA clean, Dry oxide growth of 700Å in Bruce Tube 4. Performed Step 13: CL01- RCA Clean SC1 <10min> Remove Organic components. HF <30s> Remove Oxide (5nm) from SC1. SC2 <10min> Remove metallic components. Spin/Rinse Dry Performed Step 14: CV03 OX05 700Å Dry Oxide An etch stop and pad oxide for subsequent silicon nitride deposition. Recipe 270; 1h 33min, Soak. Dry O2 CL01- RCA Clean Microelectronic Wafer Before Engineering Oxide Growth Loading Wafer into the Bruce Tube4 October 28, 2015 Authors: Miaotian Wang Page 22

4000 Å LPCVD NITRIDE DEPOSITION Today s Goal: Deposit nitride using the ASM LPCVD Tube 2 for a target thickness of 4000 Å. Step 15: CV02 4000Å LPCVD Nitride - 8 wafers total, 6 device wafers, 2 control wafers - C1: Si wafer with 780A of dry oxide - C2: Bare Si wafer Parameters - Dichlorosilane (H 2 SiCl 2 ) and ammonia (NH 3 ) - Time: 67 mins - Temp: 810 C Wafer ID Mean Thickness (A) Standard Deviation (%) C1 3696.9 6.481 C2 3962 3.956 Results of Nitride Deposition Authors: Adam Banees, Dustin Schroeder, Chris O Connell, Miotian Wang Loading Wafer into the ASM LPCVD Tube 2 October 29, 2015 Page 23

MEASURING REMAINING OXIDE THICKNESS Today s Goal: To find the thickness of the remaining oxide under the Nitride after etching the Nitride. Starting oxide was 700Å Procedure Coating photoresist Exposure in Lithography Post exposure bake Exposing to developing material Dry etching for? min. Measuring oxide thickness Measuring oxide thickness Oxide thickness measured with Nanometrics 210 Point Number 1 2 3 4 5 Thickness (Å) 355 257 265 433 466 Authors: Farzad Forouzandeh, Adam Wardas October 30, 2015 Page 24

DETERMINE NITRIDE ETCH RATE Today s Goal: Coat dummy wafer with negative photo resist and etch the nitride a little at a time to determine nitride etch rate. 1. Measure nitride thickness prior to etch using NanoSpec Optical Reflectance Spectrometer 2. Coat wafers with n-lof-2020 Image Reversal Resist, Use COATNLOF recipe on the SSI track 3. Expose on the ASML Stepper 4. Develop on SSI Track using recipe DEVNLOF 5. Etch in LAM490 plasma etcher using SF6 gas 6. Remove Photoresist NIT PreEtch (Å) 2min Etch (Å) 4min Etch (Å) After 6min Etch(Å) Center 3723 2373 1116 0 Top 3951 2426 936 0 Left 3922 2652 1305 0 Bottom 4073 2789 1557 0 Right 3926 2463 1211 0 Average (Å) 3919 2540.6 1225 0 Average Etch Rate (Å/min) - 689.2 Å/min 657.8 Å/min - Authors: Megan Ehrhart October 30, 2015 Page 25

ANCHOR PHOTO AND NITRIDE ETCH Today s Goal: Coat and expose photoresist for Anchor level, then etch nitride back using SF6 plasma Performed step 16: PH03 (photolithography coat, expose, and develop) Coated all wafers in lot with OiR-620 resist on SSI track Exposed on ASML stepper Stepper did not start up properly; had to reset several times Develop track was not operating; had to use CEE-100 spinner w/ CD-26 developer Note: Had to process through one wafer to test processes and work out kinks; by end of session only one wafer went through nitride etch Performed step 17: ET29 (nitride etch) Used LAM-490 w/ SF6 plasma to etch nitride First run didn t etch, needed to rerun After nitride etch, tried to measure oxide on poly w/ Nanospec, but material stack was too complex for measurement Performed step 18: ET07 (resist strip) Only performed on one wafer to check anchor etch Authors: Mattias Herrfurth, Corey Shay, Yamini Sodagum, Shruthi Venkateshan, Abhinav Mamidala November 3, 2015 Page 26

ANCHOR PHOTO AND NITRIDE ETCH PH03 SSI track coat resist PH03 Expose resist on ASML PH03 Develop on CEE-100 ET29 etch with LAM 490 Authors: Mattias Herrfurth, Corey Shay, Yamini Sodagum, Shruthi Venkateshan, Abhinav Mamidala November 3, 2015 Page 27

RECIPES FOR ASML STEPPER AND LAM 490 Recipe for nitride etch as displayed on LAM 490 Recipe for ASML Stepper: Dose = 250 mj/cm 2 Focus Offset = 1µm NA = 0.48 σ = 0.625 Recipe for nitride etch in LAM 490: Pressure = 260 mtorr RF Top = 125 Watts Gap = 1.65 cm SF6 flow = 200 sccm Time = 7 min / wafer Plasma generated in LAM490 chamber Authors: Mattias Herrfurth, Corey Shay, Yamini Sodagum, Shruthi Venkateshan, Abhinav Mamidala November 3, 2015 Page 28

DEVICE IMAGES AFTER RESIST STRIP Images of devices after anchor photo, etch, and resist strip Authors: Mattias Herrfurth, Corey Shay, Yamini Sodagum, Shruthi Venkateshan, Abhinav Mamidala November 3, 2015 Page 29

AFTER NITRIDE ETCH AND RESIST STRIP Green Anchor ~500Å Oxide on Poly1 on 6500Å Oxide on Silicon Pink Nitride on 7200Å Oxide on Silicon Alignment Mark - Anchor White Nitride on 700Å Oxide on Poly1 on 6500Å Oxide on Silicon Authors: Miaotian Wang, Nikhil Ratakonda November 4, 2015 Page 30

RCA CLEAN AND PEVCD OXIDE FROM TEOS Today s Goal: Remove organic and metallic contaminants from wafers with RCA clean, PECVD of TEOS Silicon Dioxide of 1.75um in AME P5000 Chamber A. Performed Step 19: CL01 - RCA Clean SC1 <10min> Remove Organic components. HF <30s> Remove Oxide (25nm) from SC1. SC2 <10min> Remove metallic components. Spin/Rinse Dry Same as Page 22 Performed Step 20: CV03 - TEOS SacOx 1.75um Heated chamber at 390 C RF Plasma + TEOS Deposition rate calc. by setting 120s for 1um on Blank Wafer Result: Mean = 9428.0Å; Std Dev. = 2.209% Recipe - 120s for 1um, then 90s for 0.75um Total 1.75um CL01- RCA Clean Spin Rinse Dry (SRD) CV03 AME P5000 After PECVD 1.75um Oxide Authors: Miaotian Wang, Nikhil Ratakonda November 4, 2015 Page 31

SACOX PHOTO Today s Goal: Coat and expose photoresist for SacOx. Performed step 21: level 3 SacOx Define Applied MICROPOSIT S1827 Photoresist - Thicker resist than OIR-620 - Necessary due to increasingly complex topography ASML Stepper SacOx Step - E = 525 mj/cm2 - Focus Offset = 2.0 - Numerical Aperture = 0.48 - Sigma Outer = 0.450 ASML Stepper Control Terminal Manually applying S1827 resist Authors: Dustin Schroeder, Christopher O Connell, Adam Banees November 5, 2015 Page 32

RESIST STRIP, TESTING TO VERIFY ETCH WORKED Today s Goal: Removed photo resist and tried to measure Poly1 resistor without success. Will have to investigate more. 1. Etch with Using 5.2:1BOE for 10 minutes. 2. Rise for 5 minutes in DI water 3. Spin dry for 5 minutes. When measuring a number of the Poly1 resistors, we got an open. However, when we connected both probes to a large pad, we got a low resistance. Putting Wafer in 5.2:1BOE Spin, Rinse, Dry (SRD) Tool Used to Dry a Boatload of Wafers Authors: Megan Ehrhart November 6, 2015 Page 33

TESTING TO MEASURE POLY1 RESISTANCE Today s Goal: To find out if the anchor etch was done properly. Probe poly1 at the anchor holes at the ends of resistor structures and measure resistance. If infinite then etch was not complete down to the surface of Poly1. Finite resistance is good. Testing gave result: infinite resistance (oxide and nitride is not etched properly) We reworked the wafer, etch more. Coat with photoresist Do Photolithography(Anchor Mask) Manual Developing Dry etching of nitride (1 min) Checked color under microscope Oxide etch using the BOE (10 min) Testing again. Still infinite resistance Probe Station and Microscope Display Showing Resistor being Tested Authors: Ankur November 9, 2015 Page 34

STRIP PHOTORESISTAND THICKNESS MEASUREMENT Today s Goal: Removal of Photoresist using GaSonics, measuring thickness of the coatings to determine if the etch depths seem correct. Removal of Photoresist using GaSonics - (recipe FF) Thickness of different layers is measured at different locations using Tencor P2 Profilometer. Wafers were also tested for electrical conductivity None of the resistor structures showed conductivity Profile measurements indicate presence of Poly1at all locations. (does not seem to be over etched) Still the resistors read infinite resistance In large pads two probes 100um apart read a resistance of 30 ohms. Still the resistors read infinite resistance Decided to move forward with the remaining wafers 7597A Thickness measurement by Profilometer 6795A Thickness measurement by Profilometer Authors: Abhinav, Nikhil, Ranjana, Shruthi, Yamini November 09, 2015 Page 35

SACOX ETCH AND RESISTOR TESTING Today s Goal: Etch the SacOx on the remaining 5 wafers. Test to make sure the etch goes down to Poly1 in the Anchor Holes. Test resistors to see if they were working correctly. If they are working correctly then next step is strip photoresist. If not etch longer in Buffered Oxide Etch and test resistors again. SacOx Etch ET06 Step 22 Etch wafer in BOE 5.2:1 solution for 10 min. Test Resistors (see next page) Results show no electrical conduction thus oxide still remains in the anchor holes Etch wafers in BOE 5.2:1 for another 5 min. Test Resistors (see next page) Results show ~ correct resistance values. Etch remaining wafers for total of 15 min. SRD Spin, Rinse, Dry. Authors: Abhinav, Nikhil, Ranjana, Shruthi, Yamini 1.75um SacOx etch in 5.2:1 BOE November 10, 2015 Page 36

TESTING REMOVAL OF NITRIDE AND OXIDE IN ANCHOR HOLES OVER POLY1 Electrical Test involves placing two probes on the wafer and connecting to the HP 4145 Semiconductor Parameter Analyzer set up to sweep the voltage from -20 to +20 volts and measuring the current. The slope is 1/R. Any reasonable value is good. Probes at both ends of Resistor Structure Two Probes on Same Anchor hole to Poly1 Slope = 0.0156 R = 1/Slope = 64 Ω I I -20V 0 +20V I vs V I vs V Slope = 0.00334 R = 1/Slope = 300 Ω -20 0 +20V Authors: Corey Shay Mattias Herfurth November 10, 2015 Page 37

RESIST STRIP AND TAKE PICTURES Today s Goal: Resist strip with GasSonics Asher. Get all wafers ready for RCA Clean and Poly2 Resist Strip ET07 Step 23 Recipe FF runs recipe F twice for resist strip. Recipe F Pressure 2.0 Torr O2 4.5 LPM N 0.5 LPM Time 99 sec MEMS Switch 1 2 d 4 r Mirror 3 SacOx remains in center rectangle SacOx remains in circle of radius r with hole in center of diameter d to anchor a mirror of Poly2, electrostatic actuation with the 4 poly1 plates 1,2,3,4 Authors: Corey Shay, Mattias Herfurth, Adam Wardas November 10, 2015 Page 38

TESTING TO MEASURE POLY 1 RESISTANCE Today s Goal: Probe Poly 1 at the anchor holes at the ends of resistor structures and measure resistance. Electrical Test involves placing two probes on the wafer and connecting to the HP 4145 Semiconductor Parameter Analyzer set up to sweep the voltage from -20 to +20 volts and measuring the current. The slope is 1/R. Same as Page 37. I vs V (Wafer D3) -20V 0 +20V I vs V (Wafer D2) Probes at both ends of Resistor Structure Slope = 3.3753m R D2 = 1/Slope = 296 Ω L/W ~10 Rhos ~30 ohms/sq -20V 0 +20V Slope = 3.5061m R D3 = 1/Slope = 285 Ω Authors: Miaotian Wang EHRHART THERMOPILE November 11, 2015 Page 39

TESTING TO MEASURE POLY 1 RESISTANCE I vs V (Wafer D4) I vs V (Wafer D6) Slope = 2.8853m R D4 = 1/Slope = 346 Ω -20V 0 +20V Slope = 2.8526m R D6 = 1/Slope = 350 Ω -20V 0 +20V The cause of the difference might be that wafer D4, D6 deposited polysilicon (36min, 650 C) 1min longer than D2, D3 (35min, 650 C). (Refer to Page 15) Wafer ID Slope Resistance(Ω) D2 3.3753m 296 D3 3.5061m 285 D4 2.8853m 346 D6 2.8526m 350 Result of Electrical Test Authors: Miaotian Wang November 11, 2015 Page 40

LPCVD POLY 2 DEPOSITION Today s Goal: Deposit polysilicon using the ASM LPCVD Tube 2 for a target thickness of 1.75µm. Step: CL01 RCA Clean -Standard RCA clean was preformed, with addition of a 30s HF dip after SC1 and SC2 Step: CV01- LPCVD Poly 2µm - 4 wafers were processed with one TEOS control wafer - The fifth wafer is in rework Parameters -100 sccm of SiH 4 -Time: 130 mins -Temp: 650 C Wafer ID Mean Thickness (A) Standard Deviation (%) C3 7703 1.62 TEOS Thickness on control before poly 2 deposition Loading Wafers into the ASM LPCVD Tube 2 Authors: Chris O Connell, Adam Banees, Dustin Schroeder, Adam Wardas November 12, 2015 Page 41

RCA CLEAN AND DEPOSITION OF POLY2 Today s Goal: Clean the wafers using RCA clean (with two HF dips) prior to deposition of Poly2 followed by LPCVD of 1.75um thick layer of polysilicon (Poly2). The second HF dip prior to the final DI rinse is to remove any chemically grown oxide from the SC2 (contains H2O2) on Poly1. We want Poly2 and Poly1 to be electrically connected at the anchor locations. Poly2 is deposited by LPCVD at 850 C with Silane (SiH4) at 300 mtorr for 140 min. Measure Poly2 thickness using the Spectromap on a test wafer that had only oxide on it. Results gave average Poly 2 thickness of 1.70um. Authors: Dr. Fuller, Adam Wardas November 12, 2015 Page 42

RESIST COATING FOR NO-IMPLANT LAYER Today s Goal: Using the SSI Tack, apply the resist coating for the no implant layer. Photoresist 1827 (a thicker resist) was used so as to not effect the current structure with large step heights to coat. 1. HMDS vapor prime and bake at 140 C for 60 seconds 2. Coat wafers with 1827 Resist 3. Spin at 2500 RPM 4. Bake at 90 C for 60 seconds SSI Track Authors: Megan Ehrhart November 14, 2015 Page 43

RESIST EXPOSE AND DEVELOP NO-IMPLANT LAYER Today s Goal: Expose and Develop No-Implant Layer.Take Pictures Pink pattern is photoresist regions not to be implanted. Authors: Abhinav, Nikhil, Ranjana, Shruthi, Yamini November 14, 2015 Page 44

ION IMPLANTATION P31, 100KEV Today s Goal: Ion implantation of Phosphorous at 100 KeV with Dose of 2E15 Ion implant with Dose of 2E15 was carried out with beam current of 300 Μa. Dose Area Charge Beam Current Area of 6 wafer = 196 cm 2 Time of Implant = Time = 2E15 196 1.6E 19 300E 6 ~ 35 Minutes/wafer Detector ~175mm diameter with 10mm hole in center is used to set up the beam scan. Horizontal scan current and vertical scan current is displayed with an oscilloscope. The M shape shows the scan will pass across the center of the detector and thus the scan will be centered on the wafer. Authors: Abhinav, Nikhil, Ranjana, Shruthi, Yamini Ion Beam Set Up November 16, 2015 Page 45

RESIST STRIP, RCA CLEAN AND THIN OXIDE GROWTH Today s Goal: Clean wafers of metallic and organic contaminants for the purpose of preparing them for a dry O 2 oxide growth of 500Å Performed step 29 RCA Clean SC1 5000mL DI Water, 300mL NH 4 OH, 300mL H 2 O 2 SC2 5000mL DI Water, 300mL HCl, 300mL H 2 O 2 HF Bath 50:1 (H 2 O:HF) SRD last step Performed step 30 Thin oxide growth (Dry O 2 ) Recipe #250 RCA clean process flow Authors: Mattias Herrfurth, Corey Shay November 17, 2015 Page 46

PROCESS FLOW FOR RCA CLEAN OXIDE GROWTH SC1 Bath SC2 Bath Spin Rinse Dryer Dry Oxide Growth Authors: Mattias Herrfurth, Corey Shay November 17, 2015 Page 47

2000 A LPCVD NITRIDE DEPOSITION Today s Goal: Deposit nitride using the ASM LPCVD Tube 2 for a target thickness of 2000 A. Measured Oxide Thickness: (Step 30) Mean : 512.09 A Std Dev. = 4.945% Step 31: CV02 LPCVD Nitride 2000A 11 wafers total, 4 device wafers, 6 control wafers and 1 blank wafer Parameters TubeMKS: 300 mtor (Deposition pressure) 60 sccm of DCS (SiH 2 Cl 2 ); 148 sccm of NH 3 Time: 35 mins Temp: 810 ºC Measured Nitride Thickness: Mean : 1978.8 A Std Dev. = 3.971% Device Wafer after LPCVD 2000 A Nitride Blank Wafer after LPCVD 2000 A Nitride Authors: Miaotian Wang November 18, 2015 Page 48

POLY 2 LAYER LITHOGRAPHY WITH ASML Today s Goal: Due to issues with some equipment, only one wafer (D3) was able to be exposed during this lab. The recipe was modified slightly, see below, to increase the focus because there are more layers on the wafer now. ASML Setup Parameters: Energy: 525 mj/cm 2 Focus: +4.0 NA: 0.48 Sigma: 045 Note: these settings did not turn out good ASML Authors: Megan Ehrhart October 30, 2015 Page 49

ETCHING OF NITRIDE, PAD OXIDE, & POLYSILICON Today s Goal: Etching of Silicon Nitride, Pad Oxide and Polysilicon Nitride etching of all the wafers using LAM 490 Recipe used FNIT 1500 260 m T, 4.54 Seconds for nitride etch, SF6 200SCCM Oxide etching of D3 wafer BOE 5.2:1 - for 2 minutes Deionized water - for 5 minutes Poly-silicon etching Drytek Quad Chamber 2 Recipe FACPOLY step 2 Etch rate was found to be slow, didn t etch polysilicon completely in 10 minutes. Etched another 10 minutes Results were not good. Think the lithography was not good. So we plan to do a focus-exposure matrix to determine best focus and exposure. Then redo the lithography Microelectronic prior Engineering to Poly2 etch on Lam 490 Plasma Intensity Vs. Time for Nitride etching Polysilicon etching starts to clear at the edge of the wafer after 10 mins remaining wafers November 23, 2015 Authors: Abhinav, Nikhil, Ranjana, Shruthi, Yamini Nitride etch Pad Oxide etch Poly removed from periphery of wafer Page 50

Today s Goal: Plasma etch poly 2 prior. PLASMA ETCH POLY 2 Wafer D4 processed etched 1. Post development bake @ 140C for 60s. 2. Plasma etch Poly 2 hole with Drytek Quad Recipe: FACCPOLY Chamber 2 for 18 min 3. Strip resist with GaSonics Asher Recipe: FF Poly 2 for a MEMS Speaker Authors: Corey Shay, Mattias Herrfurth, Adam Wardas Poly 2 over SacOx for A MEMS Switch. December 1, 2015 Page 51

PHOTORESIST COATING FOR POLY2 PATTERNING Today s Goal: Coat the wafers with photoresist, expose with ASML stepper and develop two wafers. Step 32: PH03 - level 5 Poly2 Coated all wafers with S1827 resist on SSI track ~ 3um thick Expose P.R. with ASML stepper Exposure Dose = 475 mj/cm 2, Focus Offset = -2μm ~ for D6 Exposure Dose = 350 mj/cm 2, Focus Offset = -2μm ~ for D3 Post Exposure bake - 110 C, 200 sec. GaSonics PR Asher Manually applying S1827 resist Authors: Miaotian Wang December 2, 2015 Page 52

REDUCING EXPOSURE IMPROVES RESIST IMAGE D6 Exposure Dose (mj/cm 2 ) D6 D3 475 350 D3 D6 focused on Substrate bottom of Resist D6 focused on Poly 2 Top of Resist D6 D3 focused on Substrate bottom of Resist D3 focused on Poly 2 Top of Resist D3 Authors: Miaotian Wang December 2, 2015 Page 53

ASML 5500/200 NA = 0.48 to 0.60 variable = 0.35 to 0.85 variable With Variable Kohler, or Variable Annular illumination Resolution = K1 l/na = ~ 0.35µm for NA=0.6, =0.85 Depth of Focus = k 2 l/(na) 2 = > 1.0 µm for NA = 0.6 i-line Stepper l = 365 nm 22 x 27 mm Field Size Page 54

DOING A FOCUS EXPOSURE TEST Today s Goal: We need to determine the best focus and exposure for the thick resist (S1827 ~3um) used on poly2. F = -3.0 Example: Depth of Focus = k 2 l/(na) 2 l = 365nm. Let k 2 = 0.63 and NA = 0.48 Gives Depth of Focus = 1.0um (so pick step size of 1.0um) F = 0.0 Best Best found today with S1827 resist F= - 0.5 E= 400 mj/cm2 F = +3.0 280 400 520 mj/cm2 Authors: Stephanie Bolster December 3, 2015 Page 55

PICTURES FROM FOCUS EXPOSURE TEST F=0.0 F=+2 F=+1 F=-1 F=-2 F=-3 Top Row: Microscope Focused at Top of Photoresist Bottom Row: Microscope Focused at Bottom of Photoresist S1827 ~3um Photoresist, All Exposure Dose at 400 mj/cm2 Authors: Stephanie Bolster December 8, 2015 Page 56

SETTING FOCUS FOR ASML STEPPER / THICK RESIST Focus of 0.0 is the best focus setting experimentally determined using a ~1um thick resist on a blank wafer. A stage gap sensor is used to position the surface of the wafer at a repeatable starting distance from the bottom of the lens. The gap for best focus is called zero. If the stepper job calls for a focus offset the stage height is moved an additional amount from best focus equal to the offset in µm, a positive offset makes the gap bigger, a negative offset makes the gap smaller. For positive resist the profiles might look like this for thick resist. F = +2.0 F = 0.0 Lens Focus offset = +2.0 PR Thickness = 4µm Lens Focus offset = 0.0 PR Thickness = 4µm Lens Focus offset = -2.0 Top of PR Top of PR Top of PR F = -2.0 PR Thickness = 4µm Authors: Stephanie Bolster December 3, 2015 Page 57

POLYSILICON2 ETCHING Today s Goal: To etch Polysilicon2 on remaining wafers Using the dry tech quad tool, Recipe FACPOLY Chamber 2, Time= 18 minutes Adam at Dry Tech Quad Wafer Bfore Poly Etch Wafer After Poly Etch Authors: Ankur December 5, 2015 Page 58

REMOVE PHOTORESIST Today s Goal: On wafer D3, the photoresist for Poly2 was removed, after the wafer was etched correctly. Remove Photoresist (Recipe FF): Presure: 2 Torr Oxygen: 4.5 LPM Nitrogen: 0.5 LPM Time: 99 seconds two times GaSonics Oxygen Plasma Asher Authors: Megan Ehrhart December 4, 2015 Page 59

COAT AND EXPOSE CONTACT PHOTORESIST Today s Goal: On wafer D3, the Photoresist for the Contact Cut layer was coated and exposed. Coat with Photoresist (recipe MEMs Coat) 1. Coat with HMDS and bake at 140 C for 60 seconds 2. Coat wafers with 1827 Resist 3. Spin at 2500 RPM 4. Bake at 90 C for 60 seconds SSI Track ASML Setup Parameters: Energy: 400 mj/cm 2 Focus: -0.5 NA: 0.6 Sigma: 0.7 ASML Authors: Megan Ehrhart December 4, 2015 Page 60

CONTACT CUT LITHO, NITRIDE AND OXIDE ETCH Today s Goal: To perform Level 6, Contact cut lithography and Nitride and Oxide etch on wafers D2, D4, D6. Manual coating of PR S1827 Contact cut lithography with- Dose- 400 mj/cm2 Focus offset 0.5 micro σ = 0.7 Post bake at 140 C Nitride Etch Recipe Factory Nitride Etch, Lam 490 Gas used SF6 Time (3 minutes for etch + 1 minute over etch)/wafer Buffered Oxide Etch BOE 5.2:1 - for 2 minutes Deionized water - for 5 minutes, SRD Wafer after Oxide etch Authors: Abhinav, Nikhil, Ranjana, Shruthi, Yamini December 07, 2015 Page 61

TESTING TO MEASURE POLY 2 RESISTANCE Today s Goal: Probe Poly 2 at the anchor holes at the ends of resistor structures and measure resistance. Test involves placing two probes on the wafer and connecting to the HP 4145 Semiconductor Parameter Analyzer set up to sweep the voltage from -10 to +10 volts and measuring the current. The slope is 1/R. I vs V Probes at both ends of Slope=0.6277m Resistor Structure R=1/Slope=1.59K If L/W=3, Rhos = 530 ohms/sq Note: no implant makes W smaller than it looks Authors: Aslesh Shetty, Naresh Bakhtiani,Nikhil, Adam Wardas December 4, 2015 Page 62

TESTING TO MEASURE POLY 2 RESISTANCE D4 Today s Goal: Probe Poly 2 at the anchor holes at the ends of resistor structures and measure resistance. Test involves placing two probes on the wafer and connecting to the HP 4145 Semiconductor Parameter Analyzer set up to sweep the voltage from -10 to +10 volts and measuring the current. The slope is 1/R. Gas Flow Sensor Slope=0.0170m R=1/Slope=58.8K Wafer D4 Slope=0.0103m R=1/Slope=97K Wafer D4 Why are these R s so high? Authors: Aslesh Shetty, Naresh Bakhtiani,Nikhil, Adam Wardas Slope=0.2603m R=1/Slope=3.84K Wafer D4 Note: this resistor is poly1 to poly2 to poly1 December 4, 2015 Page 63

MORE TEST RESULTS WAFER D6 Test involves placing two probes on the wafer and connecting to the HP 4145 Semiconductor Parameter Analyzer set up to sweep the voltage from -10 to +10 volts and measuring the current. The slope is 1/R. Why are these so much lower than D4? Chevron Thermal Actuator with resistance 500ohms (Yamini s device) Peltier resistor R1 = 202 Ohm, R2 = 215 Ohm December 7, 2015 Page 64

ALUMINUM METAL DEPOSITION Today s Goal: Deposit Al using CVC601 Sputter tool for a target thickness of 10,000Å. Step 42: ME01 Metal Deposition Al 4 device wafers (D2, D3, D4, D6 ) + 1 control wafer with tape for measurement Time ~ 34 min 2000 Watts for ~300 Å/min ( Sputtering power ) Pressure 5 mt ( Sputtering Pressure ) Argon Flow 28 sccm ( to set the Sputtering Pressure ) Arc detect count -> 40 Pre-sputtering: 5 min same power - Arc detect count -> 3 Remove contaminants from target expose to atmosphere (Al 2 O 3, AlN, etc.). Target Wafer after Sputtering Inside the Vacuum Chamber with the Platen Inside the Vacuum Chamber without the Platen Authors: Miaotian Wang December 9, 2015 Page 65

CURRENT WAFER STATUS December 9, 2015 D1 D2 D3 D4 D5 D6 Next Step Dead (Over etched the nitride. There is no contact to Poly1.) Step 43 PH03 Aluminum Photolithography Step 43 PH03 Aluminum Photolithography Step 43 PH03 Aluminum Photolithography Measure P1 Resistor then Step 24. CL01 Step 43 PH03 Aluminum Photolithography Authors: Megan Ehrhart December 8, 2015 Page 66

SURFACE MEMS 2015 PROCESS 1. Starting wafer 2. PH03 level 0, Marks 3. ET29 Zero Etch 4. ID01-Scribe Wafer ID, D1 5. ET07 Resist Strip, Recipe FF 6. CL01 RCA clean 7. OX04 6500Å Oxide Tube 1 8. CV01 LPCVD Poly 5000Å 9. IM01 Implant P31, 2E16, 60KeV 10. PH03 level 1 Poly-1 11. ET08 Poly Etch 12. ET07 Resist Strip, Recipe FF 13. CL01- RCA Clean 14. OX05 700Å Dry Oxide 15. CV02- LPCVD Nitride 4000Å 16. PH03 level 2 Anchor 17. ET29 Etch Nitride 18. ET07 - Resist Strip, Recipe FF 19. CL01 RCA Clean 20. CV03-TEOS SacOx Dep 1.75um 21. PH03 level 3 SacOx Define 22. ET06 - wet etch SacOx Define Etch 23. ET07- Resist Strip, Recipe FF 24. CL01 RCA Clean 25. CV01-LPCVD Poly 2um, 140 min 26. PH03 - level 4 No Implant 27. IM01-P31 2E16 100KeV 28. ET07 Resist Strip, Recipe FF 29. CL01 RCA Clean 30. OX05-500Å pad oxide 31. CV02 2000Å nitride 32. PH03 - level 5 Poly2 33. ET29 Plasma Etch Nitride 34. ET06 Wet Etch pad oxide 35. ET68 - STS Etch Poly2 36. ET07 - Resist Strip, Recipe FF 37. PH03 level 6 Contact Cut 38. ET29 Etch Nitride Contact Cut 39. ET06 Etch Oxide Contact Cut 40. ET07 Resist Strip, Recipe FF 41. 39. CL01 RCA Clean two HF 42. ME01 Metal Deposition - Al 43. PH03 level 7 Metal 44. ET55 Metal Etch - wet 45. ET07 Resist Strip 46. PH03 level 8 Release 47. SA01 Saw Wafer ½ Way 48. Special Soap Clean 49. ET66 Final SacOx Etch 50. ET07 - Resist Strip with Acetone 51. Rinse and Dry w Isopropyl Pull 52. TE01 wafer level testing 53. SEM1 Pictures 54. Packaging and Testing 12-8-15 Page 67