Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications

Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications M. Gonzalez 1, B. Vandevelde 1, Jan Vanfleteren 2 and D. Manessis 3 1 IMEC, Kapeldreef 75, 3001, Leuven, Belgium 2 IMEC/INTEC/TFCG, Sint-Pietersnieuwstraat 41 9000 Gent, Belgium 3 TU Berlin, Microperipheric Research Center, TIB 4/2-1, Gustav-Meyer-Allee 25, D-13355 Berlin, Germany Tel. +32.16.28.86.02; E-mail: mario.gonzalez@imec.be Abstract A variety of lead free alloys have been developed to replace the commonly used tin lead solder. At present, the leading candidates are, SnAg and SnCu(Ni) solder alloys. Nevertheless, a major concern regarding the rather new alloys is the fatigue reliability. The lack of reliability data of these solder materials makes every step towards the replacement of lead containing solder uncertain. A 3D Finite Element Model (FEM) was used to simulate the visco-plastic constitutive behavior of the solder in a f lip chip package when submitted to a thermal cycle test. When the solder is subjected to cyclic stresses generated during the thermal cycling, the reliability of the solder joint depends on its resistance to fatigue. The goal of the thermo-mechanical analysis in the electronic industry is to be able to predict, before extensive testing, the reliability of the solder joints. This paper focuses on predicting the thermomechanical behavior of fine pitch flip-chip packages using and solder alloys. Three different sizes and 2 different pitches were analyzed. The number of cycles to failure was correlated to the accumulated creep strain using an empirical relationship found in literature. Moreover, the results also indicate that this lead free alloys may be used as alternative solder to improve the resistance to fatigue when compared with standard lead containing solder. Key words: Flip Chip, creep, Finite Element Modeling, FEM, voids,, Lead Free. Introduction The shift from lead based solders to Pb-free in the electronic industry becomes imminent due to environmental, business and legislatives concerns. Although many lead free alloys are being investigated, the choice of the industry and research institutes converge to the use of, SnAg and SnCu(Ni) alloys as the promising replacements [1-3]. A large number of research studies have been performed and are currently ongoing in the lead-free solder area, however, the conclusions are not universal and sometimes are even contradictory. The degree of reliability improvement or deterioration depends on many factors such as package design, temperature cycle conditions, surface finishing and/or variations in the alloy composition. Tin-lead and lead-free solders present a complex nonlinear deformation when submitted to a thermal cycle. Finite Element Modeling (FEM) has been broadly used for analyzing these time and temperature dependent behavior of various solder joints in electronic packages. A severe obstacle for modeling electronic packages and its components is the lack of adequate material properties and model parameters for many of the materials being applied. These parameters should describe the time and temperature dependent properties like stress-strain relations, damages evolution and failure criteria. Therefore thermal and mechanical characterization of microelectronic materials is a critical factor for modeling. Beside the solder joint technology, the packaging technology must be also developed to meet the industrial demands for higher package density combined with an increasing number of I/O's. Flip Chip interconnection shows interesting advantages over other IC's packages including a high electrical performance and high package density [9]. The objective of this paper is to evaluate the thermomechanical behavior of a lead free solder alloy and compare the results with the eutectic tin lead solder (Sn37Pb). The demonstrator used in this analysis is a Flip Chip package with three different sizes, namely 2.5x2.5; 5x5 and 10x10 mm². The pads are in a peripheral array design with two different pitches for each die size, i.e. 200 and 300 µm. A study of the influence of voids on the reliability of the Flip Chip package is also presented. 440

Flip Chip Package Design In the framework of IMECAT project, three different Flip Chip packages were designed in order to fulfill the needs of lead free soldering tests of the different partners. However, only two types of packages were modeled. The third type (IMECAT D) was mainly used for processing challenges in order to explore the possibility of printing very fine pitches and will not be tested in the accelerated thermomechanical fatigue test. Therefore, IMECAT D package will not be modeled to predict the reliability life. For each type of package, there were specimens with 3 different chip sizes and two different kinds of solder materials for each size, namely, and. The detailed specifications of the Flip Chip specimens are summarized in Table 1. Table 1. Geometric specification of the different Flip Chip packages Wafer Description Chip size (mm 2 ) Pitch (µm) Pad size (µm) IMECAT B 10 x 10 5 x 5 300 IMECAT C 2.5 x 2.5 10 x 10 5 x 5 200 80 2.5 x 2.5 The solder bump height was measured by TU Berlin [5] using optical microscopy and laser profilometry. This information was used to calculate analytically the volume and the standoff of the solder joints after assembly. The results of volume and standoff resulted from this analytical model are summarized in Table 2. Table 2. Geometric specifications of the solder joint interconnections Measured Simulated Simulated Wafer ball height Volume stand-off Description (µm) (mm 3 ) (µm) IMECAT B 130 1.4771x10-3 119 IMECAT C 110 9.7337x10-4 97 Finite Element Simulations Due to the symmetry of the package, only one eight of the flip chip needs to be modeled in the FE analysis. The global mesh and the details in the solder joint are shown in Figure 1 for an IMECAT B chip of 10x10 mm 2 mounted on a PCB. The volume averaging technique is employed to calculate the accumulated inelastic strain of the solder joint at package and board interface. This technique is used not only to avoid singularity problems during calculation, but also to eliminate a meshing dependent results. These volume regions were located in both sides of the solder joint. In this way, it is easy to identify whether the failure will occur in the chip or in the substrate side. Figure 1 FEM mesh for the underfilled 10x10 mm 2 flip chip assembly mounted on a 1 mm thick FR4 board Besides the possible discrepancy in the results due to the material properties used in the model, the actual simulation methodology used to represent electronic assemblies and solder joints is a source of variation for life prediction models. All simulation approaches use some assumptions, which can impact the accuracy of life prediction model. In order to compare both solder materials without influence of the package design, the same model has been simulated for each solder alloy. In other words, the same geometric model has been analyzed twice, one for each solder material. The dominant failure mechanism expected for the solder joints is the thermal fatigue. Other failure modes like delamination, brittle fracture at the interface between solder and UBM or chip crack were not considered in this analysis. Another methodology used in our models to reduce the simulation time was to simplify the model. In the case of underfilled flip chip package, the main deformation in the solder comes from the deformation of the underfill and not from the shear displacement between chip and substrate like the case of CSP packages. As the volume of underfill material is much bigger than the volume of the solder (in the case of peripheral array), it is possible to simplify the model by including only the critical bump (corner bump). This approach has been verified by comparing the accumulated creep strain after 3 thermal cycles for the two package types (IMECAT B and C) with a chip size of 10x10 mm 2. The methodology was verified for both solder alloys. The accumulated creep strain for two different packages and two different solder alloys is depicted in Figure 2. The difference in the accumulated creep strain using the full model or the simplified (only the critical bump) is limited and calculation time was 441

reduced more than 5 times without loosing accuracy. Therefore, the results presented in this report will be based on simplified models. Eq. creep strain / cycle 4,0 3,5 3,0 2,5 2,0 1,5 1,0 0,5 0,0 imecat B imecat C imecat B imecat C simplified model full model Figure 2. Comparison of the accumulated equivalent creep strain, including all the solder bumps or just the critical solder (corner joint). Temperature cycle profile In the calculations, the materials of the structure were assumed to be stress free at 150ºC. The assembly was then uniformly cooled down to room temperature (no thermal gradients) to be closer to a real thermal condition. Then, a temperature cycle between 125ºC and 55 ºC is applied as load condition. Perfect bonding is assumed at all interfaces between the heterogeneous materials. As a result, delamination failure was not possible. The time-temperature loading profile used for modeling is depicted in Figure 3. Temperature (ºC) 160 140 120 100 80 60 40 20 0-20 -40-60 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 Time (s) Figure 3. Time-temperature load condition Materials Properties The thermo-mechanical behavior of the silicon die, FR4 board, copper and nickel metallizations and underfill resin were modeled as isotropic, linear elastic and temperature independent. To limit the simulation time and retain sufficient accuracy, only the solder interconnections were modeled with non-linear behavior. The time independent plasticity was not considered in this analysis because is not expected to play a significant role during thermal fatigue simulation. The published constitutive properties of lead free solder alloys are very scarce and validation of the existing models is still ongoing. For this study, the creep behavior of is assumed to obey the Garofalo-Arrhenius creep constitutive law [6]. This alloy present a different increase of creep rate at different applied stresses. At intermediate stresses, the strain rate is dominated by the stress to the power n (: n=3.3). At higher stresses, the strain rate is an exponential function of stress. The creep rate of solder alloy is defined by the following equation: 6.14 76589 151T 2027 6352 sinh exp T 76589 151T T The experimental steady state creep behavior of solder joints is given by Wiese [7]. The creep deformation of this alloy does not follow the same behavior as the eutectic alloy. In this case, there is not a break down slope as observed with the other alloy. The creep strain for the alloys is defined by a power law function as shown below: 21 18 9994.59 2x10 exp T with T in ºK and in MPa. The steady-state creep of the two investigated solder alloys is plotted versus stress (tension) in Figures 4 and 5. Comparing these data it is observed that at high temperatures and low stresses, lead free solders are more creep resistant than the standard solder alloy. However, at low temperature and high stresses, the gap between the two plots is reduced. Creep rate (s -1 ) 1,E-01 1,E-02 1,E-03 1,E-04 1,E-05 1,E-06 1,E-07 1,E-08 1,E-09 1,E-10 1,E-11-50 ºC 1,E-12 1 10 100 (MPa) Figure 4. Comparison of creep strain rate for and at 50ºC 3.3 442

Creep rate (s -1 ) 1,E-01 1,E-02 1,E-03 1,E-04 1,E-05 1,E-06 1,E-07 1,E-08 1,E-09 1,E-10 1,E-11 150 ºC 1,E-12 1 10 100 (MPa) Figure 5. Comparison of creep strain rate for and at 150ºC The relevant elastic properties of the package components are listed in Table 3 and they include the elastic properties of the solder alloys as a function of temperature. Table 3. Material Properties Young s CTE Material Modulus (10-6 /ºC) (MPa) Poisson s Ratio, FR4 25000 16 0.3 Silicon 169000 2.3 0.26 Cu 117000 16.7 0.3 Ni 200000 13.3 0.31 Underfill 5600 45 0.3 (Hysol FP4549) 35366-151. 25.5 0.34 T 52708.67-67.14. T- 17.6 0.4 0.0587. T 2 NB: T is the temperature in ºC Simulations Results The accumulated creep strain was calculated for each flip chip assembly and for each solder material. The maximum creep strain was always observed in the chip side; therefore, the failure mode is expected to occur in this region. The summary of the modeling results is presented in Table 4. From these results it is clear that the accumulated creep strain increase for larger chip sizes and smaller pitches. Therefore, the highest reliability is expected for the 2.5x2.5 mm 2 chip with 300 µm pitch. A taller solder joint is able to better address the CTE mismatch than a shorter one by relieving the shear strain stresses through the length of the joint. As a result the volume of the solder paste deposited affects the reliability of the joint. With greater paste deposited, the solder joint formed should be larger and taller producing a more reliable joint. Table 4. Accumulated creep strain (%) for the different demonstrators after 3 thermal cycles. B=300 µm pitch. C=200 µm pitch. Chip size (mm 2 ) B C B C 2,5x 2,5 1.84 2.56 2.28 3.09 5x 5 1.95 2.70 2.39 3.24 10 x 10 2.18 3.04 2.65 3.59 From these results it is also observed that the accumulated creep strain is lower in the SAC alloy; therefore, it is concluded that qualitatively, the solder should be more reliable than the under normal operating conditions. However, it has to be noted that in this FEA analysis, the package was modeled based on continuum models without any imperfections. Failure mechanisms due to processing were not taken into account. In addition, the manufactory assembly process would contribute to the reliability of the solder joint. For instance, the reflow profile can influence the wetting and the microstructure of the solder joint increasing or reducing the reliability of the solder joint and changing in consequence the trends calculated by FEM. Reliability estimation The reliability estimation of the flip chip demonstrators was done based on the empirical equations presented by R. Dudek [8]. The empirical equations are presented graphically in Figure 6. Figure 6. Relationship between accumulated creep strain and the characteristic life The reliability estimation for the different chip sizes is presented in Table 5. In all cases, the predicted lifetime of the SAC alloy is higher than the one of the eutectic solder alloy. Furthermore, the lifetime improvement is more pronounced in the case of packages with a small pitch (IMECAT C) where the reliability is about 50% higher for the SAC alloy. 443

Table 5. Reliability estimation of the different IMECAT demonstrators (N50 cycles) IMECAT B IMECAT C 793 517 2,5 x 2,5 622 360 SAC / 1,27 1,44 736 483 5 x 5 572 331 SAC / 1,29 1,46 636 414 10 x 10 475 275 SAC / 1,34 1,51 max = 4.44 % Figure 8. Equivalent creep strain in a solder joint without voids Effects of voids on the thermal fatigue reliability A typical problem encountered in the lead free solder alloys is the presence of voids after the reflow (Figure 7) because the more aggressive fluxes that must be used and the subsequent outgassing. In some cases, excessive solder voids can cause some reliability problems because they act as stress concentrators and therefore may allow the crack to initiate and propagate. max = 4.55 % max = 4.43% Figure 9. Equivalent creep strain in a solder joint with a void in different locations max = 10.64% max = 11.58% Figure 10. Equivalent creep strain in a solder joint with several voids. Figure 7. Cross section of a solder joint showing a void. A 2D FEM has been built in order to study the presence of voids in the solder joints. Several configurations were analyzed including different size and position of the voids inside the solder joint and the existence of several voids. A solder joint without voids was also model and considered as reference. From the FEM results, it was found that the maximum inelastic strain of solder joints with voids is not always larger than those without them. This is only true in the case of a single void located randomly in the solder as can be observed in Figure 9. However, if several voids are located one aside the other, the accumulated strain in the region between the two voids is much higher than the reference joint because the effective cross section is reduced (Figure 10). Summary and Conclusions In this report, we summarized the reliability studies of different IMECAT demonstrators using lead free and tin-lead solder joints. The main conclusion is that the chips assembled with lead free solder have an improvement between 27 and 51% with respect to the lifetime of the packages assembled with solder alloy. The FEM results presented in this work have not been verified experimentally yet. However, the assembly and reliability studies of bumped chips are planned and the results will be reported in a near future communication. The fatigue strength of lead-free solder joints containing voids was analyzed using 2D FEM. From these results it has been observed that the accumulated inelastic strain of a solder joint with a single void is not larger than that of a solder joint without voids. In the case of several voids in the same solder joint can cause an early fatigue failure. Acknowledgments The authors would like to thank the European Commission for financial support of this work in the framework of the IMECAT Project (EC-Growth GRD1-2001-40712) (www.imec.be/imecat). 444

References [1] IPC Leadfree Home Page: http://www.leadfree.org/lf_4-1.htm [2] J. E. Sohn. Are Lead-Free Solder Joints Reliable?, Circuits Assembly. June 2002. pp. 32-35. [3] Carol Handwerker et al., "NEMI report: a single lead-free alloy is recommended ". Surface Mount Technology vol.17, no.1 : 24-25, Jan. 2003. [4] Report on the Workshop on Modeling and Data Needs for Lead-Free Solders. Sponsored by NEMI, NIST, NFS and TMS. New Orleans, LA, USA. Feb. 2001. [5] D. Manessis et al., "Accomplishments in Lead- Free Flip Chip Wafer Bumping using Stencil Printing Technology". IMAPS 2004, Long Beach, USA. [6] R. Darveaux, et al., Constitutive Relations for Tin-Based Solder Joints. IEEE Transactions on Components, Hybrids and Manufacturing Technology, 1992, Vol 15, No. 6, Page(s): 1013 1024. [7] S. Wiese, et al., Microstructural Dependence of Constitutive Properties of Eutectic SnAg and Solders. Proceedings of the 53rd Electronic Components and Technology Conference, 2003, Page(s): 197-206. [8] Dudek, et al., "Thermal fatigue modelling for and solder joints", EuroSimE 2004, pp. 557 564 [9] B. Vandevelde, D. Degryse, E. Beyne, Parameter study for Solder Joint Reliability of Underfilled Flip Chip Assemblies, Proceedings of the 4th Area Array Packaging Technologies Workshop, Berlin, Germany, April 22-23, 2002. 445