Package Design Optimization and Materials Selection for Stack Die BGA Package

Similar documents
The Development of a Novel Stacked Package: Package in Package

Design for Plastic Ball Grid Array Solder Joint Reliability. S.-W. R. Lee, J. H. Lau*

23 rd ASEMEP National Technical Symposium

Effect of Chip Dimension and Substrate Thickness on the Solder Joint Reliability of Plastic Ball Grid Array Packages* S.-W. Lee, J.H.

Solder joint reliability of cavity-down plastic ball grid array assemblies

Journal of Science and Technology The Investigation of Die Back Edge Cracking in Flip Chip Ceramic Ball Grid Array Package (FC-CBGA)

22 nd ASEMEP National Technical Symposium

Solder joint reliability of plastic ball grid array with solder bumped flip chip

Recent Advances in Die Attach Film

Accurate Predictions of Flip Chip BGA Warpage

REDUCTION OF WARPAGE OCCURRENCE STACK-DIE QFN THROUGH FEA AND STATISTICAL METHOD

An Advanced Reliability Improvement and Failure Analysis Approach to Thermal Stress Issues in IC Packages

3D Package Technologies Review with Gap Analysis for Mobile Application Requirements. Apr 22, 2014 STATS ChipPAC Japan

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking

Statement of Work (SOW) inemi Packaging TIG SiP Module Moldability Project

System Level Effects on Solder Joint Reliability

Material based challenge and study of 2.1, 2.5 and 3D integration

Packaging Effect on Reliability for Cu/Low k Damascene Structures*

Panel Discussion: Advanced Packaging

White Paper Quality and Reliability Challenges for Package on Package. By Craig Hillman and Randy Kong

Thermal Management of Die Stacking Architecture That Includes Memory and Logic Processor

Development of System in Package

"ewlb Technology: Advanced Semiconductor Packaging Solutions"

Molding materials performances experimental study for the 3D interposer scheme

SLIM TM, High Density Wafer Level Fan-out Package Development with Submicron RDL

Simulations and Characterizations for Stress Reduction Designs in Wafer Level Chip Scale Packages

Encapsulation Selection, Characterization and Reliability for Fine Pitch BGA (fpbga )

inemi Statement of Work (SOW) inemi Packaging TIG Impact of Low CTE Mold Compound on 2nd Level Solder Joint Reliability Phase 1 & Phase 2

Effect of Die Bonding Condition for Die Attach Film Performance in 3D QFN Stacked Die.

II. A. Basic Concept of Package.

Hannah Erika R. Ducusin, Jennifer.J. Fabular, Richard Raymond N. Dimagiba, Manolo G. Mena. A. Model Description

3D FRACTURE MECHANICS ANALYSIS OF UNDERFILL DELAMINATION FOR FLIP CHIP PACKAGES

PoP/CSP Warpage Evaluation and Viscoelastic Modeling

White Paper. Discussion on Cracking/Separation in Filled Vias. By: Nathan Blattau, PhD

Thermo-Mechanical FEM Analysis of Lead Free and Lead Containing Solder for Flip Chip Applications

Basic Project Information. Background. Version: 2.0 Date: June 29, Project Leader: Bart Vandevelde (imec) inemi Staff: Grace O Malley

Avatrel Stress Buffer Coatings: Low Stress Passivation and Redistribution Applications

Basic PCB Level Assembly Process Methodology for 3D Package-on-Package

Copyright 2009 Year IEEE. Reprinted from 2009 Electronic Components and Technology Conference. Such permission of the IEEE does not in any way imply

Development and Characterization of 300mm Large Panel ewlb (embedded Wafer Level BGA)

IMPLEMENTATION OF A FULLY MOLDED FAN-OUT PACKAGING TECHNOLOGY

Recent Trends of Package Warpage and Measurement Metrologies (inemi Warpage Characterization Project Phase 3)

CHARACTERISATION OF INTERFACIAL CRACKING IN MICROELECTRONIC PACKAGING

Effects of Design, Structure and Material on Thermal-Mechanical Reliability of Large Array Wafer Level Packages

Mechanical Behavior of Flip Chip Packages under Thermal Loading

High Reliable Non-Conductive Adhesives for Flip Chip CSP Applications

Challenges and Solutions for Cost Effective Next Generation Advanced Packaging. H.P. Wirtz, Ph.D. MiNaPAD Conference, Grenoble April 2012

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

System in Package: Identified Technology Needs from the 2004 inemi Roadmap

Effect of local grain distribution and Enhancement on edgebond applied wafer-level chip-scale package (WLCSP) thermal cycling performance

Material Selection and Parameter Optimization for Reliable TMV Pop Assembly

Fundamentals of Sealing and Encapsulation

S/C Packaging Assembly Challenges Using Organic Substrate Technology

Simulation Study on the Warpage Behavior and Board-level Temperature Cycling Reliability of PoP Potentially for High-speed Memory Packaging

High Density PoP (Package-on-Package) and Package Stacking Development

TRANSFER MOULDING & EPOXY MOULD COMPOUND TECHNOLOGY WORKSHOP

EVALUATION OF HIGH RELIABILITY REWORKABLE EDGE BOND ADHESIVES FOR BGA APPLICATIONS

Solder Joint Reliability Study for Plastic Ball Grid Array Packages

Cost effective 300mm Large Scale ewlb (embedded Wafer Level BGA) Technology

Effect of Bond Layer Properties to Thermo-Mechanical Stresses in Flip Chip Packaging

ENHANCING WLCSP RELIABILITY THROUGH BUILD-UP STRUCTURE IMPROVEMENTS AND NEW SOLDER ALLOYS

The Effect of Fillers in Nonconductive Adhesive on the Reliability of Chip-on-Glass Bonding with Sn/Cu Bumps

Residual Stress Distribution and Adhesive Interface Strength Analysis of Thermosetting Resin Molding

Parametric Design and Reliability Analysis of Wire Interconnect Technology Wafer Level Packaging

Thermal stress analysis of leads in Quad Flat Package: a parametric study

Recent Trends of Package Warpage and Measurement Metrologies

Achieving Warpage-Free Packaging: A Capped-Die Flip Chip Package Design

Pressure-Assisted Low-Temperature Sintering of Silver Paste as an Alternative Die-Attach Solution to Solder Reflow

Wire-Bond CABGA A New Near Die Size Packaging Innovation Yeonho Choi February 1, 2017

HOW THE MOLD COMPOUND THERMAL EXPANSION OVERRULES THE SOLDER COMPOSITION CHOICE IN BOARD LEVEL RELIABILITY PERFORMANCE

Qualification of Thin Form Factor PWBs for Handset Assembly

Thermo-Mechanical Reliability Assessment of TSV Die Stacks by Finite Element Analysis

Power Electronics Packaging Solutions for Device Junction Temperature over 220 o C

Design and Characterization of Thermal Conductive Wafer Coating in Thin Small Outline Package for Automotive Product Application

Keywords:- Sintered Silver, Die Attach, Tin Lead Solders, Thermal Analysis, Digital Scanning Calorimetry

IN ELECTRONIC packaging, materials with different coefficients

ENHANCING MECHANICAL SHOCK PERFORMANCE USING EDGEBOND TECHNOLOGY

The Packaging and Reliability Qualification of MEMS Resonator Devices

Mold Compound and Copper Wire Selection for Quad-Flat Packages with High Density Leadframe in Automotive Applications

Topography and Deformation Measurement and FE Modeling Applied to substrate-mounted large area wafer-level packages (including stacked dice and TSVs)

JOINT INDUSTRY STANDARD

Freescale Semiconductor Tape Ball Grid Array (TBGA) Overview

Originally presented at NEPCON Southeast, Copyright 1999 AcousTech, Inc. INTRODUCTION

Chips Face-up Panelization Approach For Fan-out Packaging

PLASMA TREATMENT OF X-Wire. Insulated Bonding Wire

Experience in Applying Finite Element Analysis for Advanced Probe Card Design and Study. Krzysztof Dabrowiecki Jörg Behr

Processor Performance, Packaging and Reliability Utilizing a Phase Change Metallic Alloy Thermal Interface System

Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes

Electrical and Fluidic Microbumps and Interconnects for 3D-IC and Silicon Interposer

RF System in Packages using Integrated Passive Devices

Cypress Semiconductor 2-Die Stacked & Molding Compound Package Qualification Report

Cu Bond Wire Reliability and Decapsulation Process

REWORKABLE EDGEBOND APPLIED WAFER-LEVEL CHIP-SCALE PACKAGE (WLCSP) THERMAL CYCLING PERFORMANCE ENHANCEMENT AT ELEVATED TEMPERATURE

EXTRA FINE PITCH FLIP CHIP ASSEMBLY PROCESS, UNDERFILL EVALUATION AND RELIABILITY

Future Electronic Devices Technology in Cosmic Space and Lead-free Solder Joint Reliability

Worldwide IC Package Forecast (Executive Summary) Executive Summary

THROUGH-SILICON interposer (TSI) is a

Warpage Mechanism of Thin Embedded LSI Packages

Selection and Application of Board Level Underfill Materials

Transcription:

Package Design Optimization and Materials Selection for Stack Die BGA Package Rahul Kapoor, Lim Beng Kuan, Liu Hao United Test & Assembly Center Ltd (UTAC) 5 Serangoon North Ave 5, Singapore 554916 Email: rahul_kapoor@utac.com.sg, bk_lim@utac.com.sg, liu_hao@utac.com.sg Abstract Due to an expanding consumer electronics market and the need for form factor reduction, stack packages have been gaining popularity in the last 3 years. With the incorporation of silicon die stacking, there is a corresponding increase in bimaterial coupling and interfacial adhesion becomes a prime reliability concern. Interfacial delamination between the diemold compound is an existing issue that limits the package reliability under the exposure of both moisture and thermal excursion. With the requirement for higher solder reflow temperatures for lead-free applications, the problem becomes even more severe. It becomes increasingly important to understand the combined effects of material selection and package structure on the interfacial delamination under temperature excursion in the presence of moisture. This paper presents a detailed analysis into the effects of packaging materials and structure on interfacial delamination under temperature excursion in the presence of moisture for two die stack fine pitch BGA (D2-FBGA). Upfront analysis based on thermo-mechanical modeling is performed prior to a full design of experiments (DOE) investigation. The current DOE matrix includes variation in mold compound and geometrical construction in terms of die size and substrate thickness. Test results show that the silicon to package ratio has a strong correlation to die-mold compound delamination and other test factors such as geometrical variations in diestacking and the selection of mold compound influence the intensity of delamination Introduction Semiconductor industry s demand for higher levels of integration, lower costs, and a growing awareness of complete system configuration through SiP solutions [1-3] is enabling wide acceptance of multi-chip packaging. With an increasing importance on form factor reduction, especially in mobile and wireless consumer products, stacked die packages are becoming more common in cell phones, digital cameras and hand-held devices. Electronic packaging techniques that use only planar dimensions are no longer effective enough to answer the requirements of continually shrinking personal electronic products. Using 3-D packaging, devices can be made much smaller and lighter than with planar 2-D packaging [4]. Remarkable size and weight reductions have been reported using 3-D packaging instead of packaging in planar dimensions. In addition, 3-D interconnection delivers other significant advantages. The interconnection lengths can be kept shorter and the connectivity between active parts in a 3-D package is better than in planar packages. The noise and delay reductions due to shorter interconnection lengths are advantageous for high-speed operation [5]. Figure 1 shows the actual structure of the D2-FBGA package with two dies in a stack configuration and wirebonded on to the substrate. Figure1: Structure of D2-FBGA package showing the two die stack and the wirebond By packaging large amount of silicon in a small footprint provides various stress-related challenges to product reliability. Our work addresses some of these challenges by examining the effect of design and materials on the package reliability. Background Prior to the building of a full matrix for engineering evaluation, some prototypes were assembled for moisture sensitivity evaluation under JEDEC MSL2a (60 o C/60%RH, 120hrs) pre-conditioning followed by reflow (3 cycles) at 260 o C. As a check, Scanning Acoustic Microscopy was performed and the interfacial integrity of the prototypes was assured. Three epoxy mold compounds (EMC) were included in the prototype run (termed as EMC-A, EMC-B and EMC- C). After the preconditioning-reflow evaluation, C-SAM observation revealed that there were interfacial delaminations within the prototypes (refer to Figure 2), especially the packages encapsulated with EMC-A and EMC-C. As shown in Figure 3 below, there is notable delamination along the mold compound-bottom die interface, which develops into mold compound cracking in some cases. Thus, interfacial delamination along the mold compound-bottom die interface has been identified as a key reliability determinant for the current reliability evaluation of D2-FBGA. 0-7803-8582-9/04/$20.00 c2004 IEEE 2004 IEEE/SEMI Int'l Electronics Manufacturing Technology Symposium

Delamination initiates from bottom die edge Figure 2: C-SAM image with delamination within bottom die region Mold compound Delamination Substrate Epoxy Die adhesive Top Die Bottom Die clearly agrees with the C-SAM observation shown in Figure 2, which indicates possible delamination initiating from the bottom die edge. Both stress and strain can be viewed as potential drivers to the failure occurrence in this context. However, there is a greater fluctuation of stresses along the interface and it would be less conclusive if stresses were correlated to actual reliability keeping in mind the factors from mesh dependency and singularity. Strains are more consistent across the interface and will be proposed as a damage index for the current analysis. Since mold compound is expected to be more susceptible to straining (ductile characteristic) at high temperature, it is expected that strain is an appropriate indicator for assessing interfacial delamination. Mold Compound Figure 3: SEM cross-section view with delamination along mold compound-bottom die Based on Failure Analysis conducted on prototype units, the EMC-Bottom Die interface was found to be a potential trigger of package reliability failure. These prototype units provided a first-cut assessment of potential package reliability issues within the two die stack fine pitch BGA (D2-FBGA) study prior to a full engineering evaluation. In addition, upfront analysis based on thermo-mechanical simulation was conducted to better define the process evaluation matrix as well as provide physical insights to the causes of package reliability failures, prior to actual testing. Methodology for computational analysis In this paper, Finite Element Analysis was engaged to understand the mechanics of stress distribution along the EMC-bottom die interface within the context of thermomechanical analysis. Key interests would include the effects of mold-compound properties as well as the impact of variations in package structure (such as die size/thickness and substrate thickness) on package stress especially along the EMC-bottom die interface. A parametric 3D quarter (based on package symmetry) Linear model was constructed to account for all geometrical factors (refer to Figure 4). A temperature loading from 25 o C to 260 o C (resembling a lead free surface mount temperature excursion) was applied for all thermo-mechanical analysis with the assumption of a stressfree condition at room temperature (25 o C). Also, the mechanical properties of major package constituents were as highlighted in Table 1. The concept of CTE eff has been introduced to interpolate CTE s (alpha 1 and apla 2 ) based on the glass transition (T g ) temperature of the mold compound and has been commonly adopted in package mechanical analysis [6]. Interfacial stresses and strains along the mold compound-bottom die interface as denoted by (i)-(ii) were extracted based on the material and structural setup used in the prototype. As shown in Figure 5, typically both interfacial stresses and strains are highest at the edge of the bottom die-mold compound interface. This EM Die2 Die1 BT BT substrate Top Die Die-adhesive Top Die adhesive i DA1 Package center ii Bottom die Figure 4: Illustration of quarter model amd path of stress mapping Table 1: Mechanical properties of package materials Mat E(MPa) v Tg( o C) ppm/ o C (x/y/z) alpha 1 alpha 2 CTE (eff) BT substrate 33,947 0.37-15/60/16 15/60/16 15/60/16 Die 128,000 0.28-2.3 2.3 2.3 Die Adhesive 640 0.37 42 48.0 140.0 133.0 EMC-A 19,000 0.37 183 13.0 40.0 26.1 EMC-B 26,000 0.37 130 9.0 40.0 26.1 EMC-C 24,000 0.37 125 8.0 34.0 22.9 Effective CTE from 25 0 C to 260 0 C is based on: CTE(eff)=[alpah1*(Tg-25)+alpha2*(260-Tg)]/(260-25) Shear stress Peel stress Shear strain Peel strain Diagonal distance from package center to edge along EMC Figure 5: Compare interfacial stresses and strain along (i)-(ii)

Effect of mold compound properties on MSL reliability It is widely accepted that the properties of packaging materials have a strong influence on the reliability performance of IC packages under JEDEC MSL-reflow reliability. Packages are constructed based on the integration of materials with different thermal expansion properties. The thermal mismatches between these materials under thermal excursion as well as the coupling flexural responses would be important reliability parameters. In this paper, the various mechanical properties of the mold compound and their impact on package reliability will be investigated. Using strain as the damage index, sensitivity studies based on the impact of effective Coefficient of thermal expansion (CTE (eff) ) and the Elastic modulus (E) are conducted. In all analyses, a D2- FBGA package with body size of 15mm x 15mm has been used as a benchmark (normalization control) with top and bottom die size of 4x4mm and 6x6mm (both with a thickness of 0.16mm) respectively. The substrate thickness is assumed at 0.30mm. A sensitivity sweep was conducted with CTE (eff) and E benchmarked at 22ppm/ o c and 30,000MPa respectively (the sweep range encompasses the bulk of CTE reported for common mold compounds). As shown in Figure 6, the normalized strain increases with increasing CTE (eff), highlighting that Stack-die FBGA packages using mold compound with higher CTE (eff) would be more prone to interfacial delamination along the bottom die-mold compound interface. It is envisaged that a mold compound with high CTE (eff) would aggravate CTE mismatches with the die inducing large strain, especially at the peak reflow temperature, where adhesion could be severely compromised. On the other hand, a decrease in normalized strain was observed under increasing E, which suggests that stiffer mold compound would relieve the risk of delamination concerned. In terms of structural integrity, a high modulus would be desirable since it inhibits strain. Based on the assumption that strain contribution from E and CTE (eff) are linear and independent, the combined effect of these properties could be assessed. Referring to the properties illustrated in Table 1, the normalized strain for EMC-A, B and C are derived using Figure 6 & 7 and the summary table is shown in Table 2. Within the context of current analysis, it is postulated that EMC-B would be less susceptible to the concerned interfacial delamination provided that thermo-mechanical aspect remains the main driver of failure and the interfacial adhesion of all mold compounds to the die are comparable. Normalized Strain 150.0 140.0 130.0 120.0 1.0 0.0 90.0 80.0 70.0 77.34 Variation of strain(y) with CTE of EMC 0.00 122.99 146.30 16.0 18.0 20.0 22.0 24.0 26.0 28.0 30.0 32.0 CTE of EMC, (ppm) Figure 6: Variation of normalized strain with CTE(eff) Normalized Strain (%) Effect of geometrical structure Besides improving reliability through mold compound optimization, another factor to look into would be the geometrical structure. Under normal circumstances, the Silicon die induces a large CTE mismatch with the rest of the packaging materials, which translates into residual stress (or strain) and is thus a prime cause of common reliability issues. It is thus of great interest to identify the impact of silicon die size on the concerned interfacial delamination. Within the context of current D2-FBGA, reliability impact from both the bottom and top die through silicon volume (within the mold cap) has been evaluated. In this analysis, the package size was kept at 15mm x 15mm while the substrate thickness was fixed at 0.30mm. Variation in silicon volume was achieved through changes in top and bottom die sizes and thickness. The corresponding thermal strains near to the edge of mold compound-bottom die interface (along package diagonal) were extracted. As shown in Figure 8, normalized strain is observed to increase with the increase of Silicon volume percentage within the package. It is thus postulated that there might be a greater tendency for delamination along the interface if the packaging ratio of Silicon is large. A full detailed engineering evaluation has been proposed to evaluate this postulation and will be discussed in the latter section. Normalized Strain 150.0 140.0 130.0 120.0 1.0 0.0 90.0 80.0 70.0 4.00E-03 3.60E-03 3.20E-03 2.80E-03 2.40E-03 2.00E-03 118.80 Variation of strain(y) with E of EMC 111.13 5.05 Variation of normalized strain with volume % of Si 0.00 16,000 18,000 20,000 22,000 24,000 26,000 28,000 30,000 32,000 Modulus, E (MPa) Figure 7: Variation of normalized strain with E 5.0.0 15.0 20.0 25.0 30.0 Volume % of Si in package EMC-A EMC-B EMC-C Figure 8: Variation of strain at different Si Volume (%) The concept of Si capacity within the package body could be extended further. Though it is convenient to express the top and bottom Si-die size through an equivalent volume, this parameter does not provide the comparative representation of aspect ratios in terms of top and bottom Si-die size. An

alternative factor to look into would be the span of bottom die diagonal-shoulder that resides outside the coverage of the topdie (refer to Figure 9). Interestingly, it was observed that when the diagonal span increases (i.e. the top die has a smaller aspect ratio compared to the bottom die size) whilst the overall Si volume remains unchanged, the normalized ratio of strain decreases (refer to Figure. ). This suggests that there would be less risk of delamination along the moldcompound-bottom die interface if the bottom-to-top die aspect ratio increases. Primarily, the diagonal span represents a gripping capacity of mold compound to the bottom die-top interface, which promotes a firmer adhesion. On the other extreme end, another alternative would be to eliminate the span altogether, such that the top and bottom size becomes identical. Figure 9: Illustration the of diagonal distance viewing from package top Normalized ratio of strain Top view of pkg 1.24 1.22 1.20 1.18 1.16 Diagonal Top die Bottom die Normalized strain vs diagonal distance with Si vol fixed 1.14 1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50 5.00 5.50 Diagonal distance (mm) Figure : Variation of Diagonal distance with Si vol. Other structural factors (substrate thickness) The impact of other structural variation, namely package substrate thickness on mold compound-bottom die interfacial delamination was also investigated. As shown in Figure 11, a sensitivity study on substrate thickness shows that normalized strain ratio decreases with increasing substrate thickness. In terms of mechanical integrity, a thicker substrate enforces greater compliance within the package, which assists in minimizing strain incurrence along the mold compoundbottom die interface. Thus the risk of delamination could be reduced accordingly. Interestingly, it is noted that the impact of substrate thickness on localized strain is much lower compared to other structural (silicon volume) and material variations. Computational analysis based on thermo-mechanical approach provides some physical insight into the failure mechanism observed under the current assessment as well as the impact of both material and structural variations on interfacial delamination along mold compound-bottom die interface. Based on this information, a more extensive and thorough engineering evaluation had been developed to examine package reliability in greater detail as well as verify the trends reported through simulation. Normalized Strain 1.05 1.04 1.03 1.02 1.01 1.00 0.99 0.98 Variation of normalized strain ratio with BT substrate thickness 1.04 Figure 11: The effect of variation in substrate thickness Process DOE Study Based on findings after the structural simulation, a DOE matrix was devised to validate the simulation results and thereby, find an optimum packaging solution for D2-FBGA. The process evaluation was primarily targeted to study the effects of materials and package structures on D2-FBGA s reliability performance. In this DOE matrix, four factors were considered: 1. Three different mold compounds: A, B, C. 2. Different die size groups: the different sizes of bottom die and top die. 3. Substrate thickness: 0.2mm and 0.3mm. 4. Die thickness: 0.14mm and 0.16mm Table 1 shows the various DOE parameters used in the study. The packages were build using 12 different compositions and were subjected to Jedec MSL2a (260C reflow) moisture preconditioning reliability test. Table 2 shows the detailed DOE matrix and the failure rate for each configuration. The failure was defined as delamination within the package. 1.00 0.99 0.15 0.20 0.25 0.30 0.35 0.40 0.45 BT substrate thickness, (mm) Table 3: DOE Parameters of full engineering evaluation MC (Mold Compounds) - A - B - C DSG (Die Size Group) - 8+4 Bottom Die Size: 8x8mm Top Die Size: 4x4mm - 8+6 Bottom Die Size: 8x8mm Top Die Size: 6x6mm - 6+4 Bottom Die Size: 6x6mm Top Die Size: 4x4mm ST (Substrate Thickness) - 0.2mm - 0.3mm DT (Die Thickness) - 0.14mm - 0.16mm

Table 4 DOE Matrix of full engineering evaluation No. MC DSG ST DT % of Si in Mold Cap Faliure Rate of MSL2a@260C 1 C 8+4 0.2 0.14 8.30 19/22 2 A 8+4 0.3 0.16 9.48 1/22 3 A 8+4 0.2 0.14 8.30 3/22 4 B 6+4 0.2 0.14 5.39 0/22 5 B 8+6 0.3 0.14.37 0/22 6 A 8+6 0.2 0.14.37 18/22 7 C 8+6 0.2 0.16 11.85 22/22 8 B 6+4 0.2 0.16 6.16 0/22 9 B 8+4 0.3 0.16 9.48 0/22 C 8+6 0.3 0.16 11.85 22/22 11 C 6+4 0.3 0.14 5.39 16/22 12 A 6+4 0.3 0.16 6.16 0/22 % of Si in mold cap = (Bottom die volume + Top die volume) / (Mold cap volume per unit). Package size is 15x15mm with 208 solder balls Shown in Figure 12 is the statistical analysis of the process DOE and based on the reliability test data, the following observations were made: 1. The type of mold compound plays the most significant effect on package s MSL performance: Packages assembled using mold compound C shows large delamination coverage and almost 0% test units had delamination problem. Packages using mold compound A performed better compared to that of compound C. Packages using compound B perform the best and all the test units passed the MSL test. Compound B has the best overall performance out of all tested mold compounds. This observation is in agreement with the earlier simulation prediction, which highlighted compound B as the best possible choice since it provides a lower option of strain intensity under thermal excursions. Failure Quantity 20 0 20 0 20 15 5 0 15 5 MC A B C A B C MC DSG 6+4 8+4 8+6 6+4 8+4 8+6 DSG 2. Variations in silicon volume within the mold compound showed a high dependence on the package reliability. The larger is the percentage of silicon in the mold compound, the poorer was the reliability performance. Please refer to Figure 13 and Figure 14 for detailed comparison for mold compounds A and C respectively. If the Si% is more than %, the package failure rate can be as high as around 80%.This effect will pose a major challenge for the ST Max(0.3) Midpoint(0.25) Min(0.2) 0.22 0.24 0.26 0.28 ST DT Max(0.16) Midpoint(0.15) Min(0.14) 0.145 0.15 0.155 DT Figure 12: Interaction chart of DOE result packaging community, as the demand for higher functionality on thinner packages will require large silicon volume in lesser amount of mold compound. 3. The ratio of top to bottom die size also shows a significant impact on the reliability performance. As shown in the Die-silicon-Group column of Figure 12, based on a common 8x8mm bottom die, a larger failure rate is observed for a larger top die (6x6mm) compared to its smaller counterpart (4x4mm). This is in good agreement with earlier simulation, which highlights an increase in strain intensity (and thus the risk of delamination) as the die top-to-bottom aspect ratio increases. 4. Variations in Substrate thickness did not have any significant effects on the package reliability. This phenomenon was also consistent with the structural simulation. 5. Although not evaluated as part of structural simulation, but it was also found that variation in die thickness (140-160um) by itself does not play a significant part in the package reliability performance. Delamaination % of tested units The Relationship between Si percentage in mold cap and package faliure rate with Compound C 0.00% 95.00% 90.00% 85.00% 80.00% 75.00% 70.00% 65.00% 60.00% 55.00% 50.00% 5.39% of Si 8.3% of Si 11.85% of Si Si % in mold cap 15x15mm Figure 13: Package failure rate with mold compound A When Si% in mold cap is around 6%, compound A can sustain the package to pass the reliability tests. When Si% increases to 8% to 9%, we have around 9% failure. Delamaination % of tested units The Relationship between Si percentage in mold cap and package faliure rate with Compound A 0.00% 80.00% 60.00% 40.00% 20.00% 0.00% 6.16% of Si 8.89% of Si.37% of Si Si % in mold cap 15x15mm Figure 14: Package failure rate with mold compound C

Conclusion In this paper, the reliability of 2 die stack fine pitch BGA package (D2-FBGA) after JEDEC MSL2a moisture preconditioning (260 o C reflow) has been discussed. Interfacial delamination between the mold compound-bottom die interface has been identified as a potential cause of reliability failures. It is envisaged that the cause of such delamination could be multi-faceted, including both moisture related (multiphysical impact both mechanical and chemical) as well as thermo-mechanical factors. Within the context of current work, a thermo-mechanical analysis approach has been used. Essentially, thermo-mechanical simulations provide a good correlation with actual experimental evaluation. This suggests that thermal mismatches between packaging materials under temperature excursion (which result in residual stress) remain one of the major factors that govern the risk of existing delamination along mold compound-bottom die interface. In particular, localized thermal strain along the interface has been shown to be a good indicator of the delamination concerned. Based on thermal simulation, mold compound with a higher modulus and lower effective CTE (CTE (eff) ) has been shown to reduce localized thermal strain at the interface. These postulations have correlated well with actual reliability results, which shows a better performing compound B compared to compound-a and compound-c. In terms of package structure, it has been validated that an increase in silicon volume within the package triggers a higher risk of interfacial delamination. The impact of top and bottom die size ratio and substrate thickness has also been discussed in the paper, and has been found to be of lesser impact on package reliability. Future work Development in the current work will be extended to include a more comprehensive mechanical characterization of mold compounds both structural and moisture related properties. An integrated multi-physical simulation methodology has been proposed to account for integrated stress distribution along the bi-material interface, which constitutes of stress from thermo-mechanical, hygromechanical and vapor pressure under preconditioning-reflow evaluation. The methodology has been successfully tested on a previous application [7] and development work is underway for Stack-die BGA packages. References 1. C. Val, T. Lemoine, 3-D interconnection for Ultradense mutlichip modules, IEEE transactions on CHMT, Vol. 13., No. 4., pp. 814-821, 2000. 2. S. Pinel, J. Tasselli, JP Baibe, A. Marty, P. Puech, D. Esteve, Mechanical Lapping of Ultra thin wafers for 3D integration, Proceedings fo 22 nd International Conf. on Microelectronics, Serbia, May, pp. 443-446, 2000. 3. Kenji Takahashi, 3-D LSI Chip Integration at ASET (ASET), 2002 IEEE Systems Packaging Japan Workshop, NTT Musashino R&D Center, Japan, February 4-6, 2002. 4. S.F.Al-Sarwai, D. Abbot and P. Franzon, A review on 3- D packaging Technology, IEEE transactions on CPMT PartB, Vol.21., No.1., pp.1-14. 1998. 5. Al-Sarawi, S. F. et al., a Review of 3-D Packaging Technology, IEEE Transactions on components, packaging, and manufacturing technology, part B, Vol 21, No. 1 (1998), pp. 2-14. 6. P.S. Teo, E.H. Wong, T.B. Lim, Requirements for moisture and thermal-shock resistance of a Plastic BGA package, Pan Pacific Symposium 2000. 7. B.K. Lim et al., Reliability assessment of Quad Flat No- Lead Packages through test & structural optimization, SEMICON Singapore Conference, 2004 pp. 165-171