Practical Applications for Nano- Electronics by Vimal Gopee E-mail: Vimal.gopee@npl.co.uk 10/10/12 Your Delegate Webinar Control Panel Open and close your panel Full screen view Raise hand for Q&A at the end Submit text questions during or at the end
Practical Applications for Nano- Electronics by Vimal Gopee E-mail: Vimal.gopee@npl.co.uk 10/10/12 Introduction: Part of the Engineering Doctorate (EngD) in Micro and Nano materials at The University of Surrey 2 nd year of the programme Full-time placement at NPL Currently working on Nanocarbon Electronic Interconnects (NEI) project
Contents Current issues with electronic interconnects Properties of carbon nanotubes Synthesis methods The nano-carbon interconnects project Uses of carbon nanotubes in circuits Summary Current issues with electronic interconnects
Moore s law Number of transistors per chip doubling every 18-24 months Interconnect pitch size decreasing
The International Technology Roadmap for Semiconductors (ITRS) predictions Challenges Dielectric Copper Conductor Tungsten contact plug Modern multi level interconnect of a microprocessor in cross sectional view Source: Intel Number of transistors per chip doubling every 18 24 months Interconnect pitch size is decreasing and number of interconnects is increasing Current density in interconnects is increasing Increased resistance and decreased current carrying capability due to electromigration Performance will be limited by current interconnect technology unless new materials are implemented ITRS
Current technologies and limitations Reduction of pitch of Ball Grid Array (BGA) Diameters currently greater than 70 μm. Susceptible to electromigration Crack formation due to stress and thermal coefficient of expansion (TCE) mismatch Modern components like Quad-Flat No-leads (QFN) produce a lot of heat Fast Heat dissipation required or performance is limited Voiding in solder contact reducing heat transfer Electromigration due to pitch reduction and heat dissipation limit performance of components ITRS requirements Introduction of new materials to meet conductivity requirements and reduce the dielectric permittivity Engineering manufacturable interconnect structures, processes and new materials Achieving necessary reliability Manufacturability and defect management that meet overall cost/performance requirements Integration of new processes and structures, including interconnects for emerging devices
Properties of Carbon nanotubes Nanocarbon Fullerene Tubes Graphene Carbon black Nanodiamonds Cones
Bonding Length: typical few μm Graphite sp 2 Diamond sp 3 Covalent Bonding Strong bond between individual neighbouring carbon atoms in a single tube Van der Waal Forces Weak bond between the individual nanotubes themselves Diameter: as low as 1 nm High aspect ratio: length diameter 1000 quasi 1D solid Types of carbon nanotubes Graphene Single-wall CNT (SWCNT) SWCNTs consist of single rolled sheet of graphene MWCNT MCWNTs consist of multiple rolled layers (concentric tubes) of graphene.
Nanotube Carbon nanotubes (CNTs) discovered 1991, Iijima Roll-up vector: C h na m 1 a 2 Nanotube Electrical conductivity depending on helicity C h n a1 m a 2 If 2n m i, then metallic 3 else semiconductor SWCNT can be semiconducting or metallic. It all depends on the angle of rolling and diameter of the nanotube MWCNTs almost always metallic
CNTs v/s metals Tensile Strength (GPa) Melting point (K) Max Current density (A/cm 2 ) Thermal Conductivity (kwmk 1 ) Cu SWCNT MWCNT ~10 6 ~10 9 ~10 9 1356 3800 0.22 22.2 11 63 0.385 ~5 3 CNTs have: Negligible Electromigration Efficient electron transport Low resistivities High thermal conductivities High tensile strengths CNT limitations Limitations of CNTs for application in interconnects: High contact resistance due to electron scattering at metal contact Inertness of CNTs requires chemical processing before application hence poor adhesion Defects increase resistivity SWCNTs can be metallic or semiconducting and hence have to be sorted before use CNTs have the potential to replace metals in electronic circuits if the above problems can be resolved
Synthesis Methods Synthesis: overview Commonly applied techniques: Chemical Vapor Deposition (CVD) Arc-Discharge Laser ablation Techniques differ in: Type of nanotubes (SWNT / MWNT / Aligned) Catalyst used Yield Purity
The arc discharge method Carbon contained in the negative electrode sublimates because of the high discharge temperatures forming Nanotubes Yield for this method is up to 30% by weight Produces both single- and multi-walled nanotubes with lengths of up to 50 μm with few structural defects The laser ablation method Inert gas atmosphere Pulsed Laser vaporises graphite target CNTs nucleate at cooler surfaces of the reactor primarily single-walled carbon nanotubes with a controllable diameter determined by the reaction temperature
Chemical vapour deposition (CVD) Catalyst deposited on silicon substrate Feedstock gases such as acetylene, methane, etc decomposed by catalyst during growth process Carbon atoms diffuse over catalyst surface and nucleate to form CNTs Several types including plasma enhanced (PECVD), photo thermal (PTCVD), Photo thermal CVD Low temperature growth ~350 C Suitable for CMOS applications Acetylene gas used as feedstock Top of sample heated by quartz lamp (Shang, Tan, Stolojan, Papakonstantinou, & Silva, 2010) Substrate kept cool (<250 C) by water cooled stage High pressure growth achievable
The nano-carbon electronic interconnects project (NEI) at NPL Aims of NEI To develop methodology for interconnect fabrication using carbon nanotubes To develop or adapt existing metrology for the characterisation ofcarbon nanotube interconnects To characterise the electrical properties, behaviour under mechanical deformation and thermal stress of carbon nanotube interconnects
CNT growth G Vertically aligned CNT D D2 50μm Si wafer = 0.42 2 = 50.9 ~150 μm sample shown above Dense vertical array High purity confirmed by low ratio Interconnect Fabrication Process
MWCNT-solder interconnects MWCNTs show poor adhesion to solder due to weak Van der Waals bonding Two treatments are applied to improve adhesion to solder Process 1 Process 2 Process 1+2 1. MWCNTs are treated with oxygen plasma to remove amorphous carbon and to activate the surface Wetting Force (mn) 2. Metal interface layers (Au, Pd or Ni) are deposited on the MWNCTs by sputtering Time (s) Sample characterisation XPS scans before and after oxygen plasma treatment Peak % Pristine Treated C 99.7 74.0 O 0.3 25.5 1 sp 2 32.4 24.9 2 sp 3 38.3 21.9 3 O H 2.9 0.1 4 C O 9.0 38.5 5 O C O 1.1 12.9 6 π π* 16.3 1.7
Metrology development Characterisation and Assembly of Nanocarbon Interconnect Systems (CANIS) 1 - motorised stage 2 - load cell 3 - digital microscope 4 - laser displacement monitor 5 - bottom stage 6- heater 7 - top stage 8 - multimeter for 4- probe measurements Allows the fabrication and subsequent tensile stressing Four-probe resistance measurements Force ~ 1mN Displacement ~ 0.1μm Resistance ~ mω CANIS schematic CNTs Solder Copper L a s e r Load cell Motorised Actuator Copper Sample holders Heater Base
Technical progress 5 μm Solving the adhesion problem: Encapsulation of the tip of MWCNT bundles with metal Metal nucleates at defect sites Metal then forms a metallurgical bond with solder alloy Displacement dependence of Stress for a Solder MWCNT Solder i nterconnect Treatments applied improve adhesion of MWCNTs to solder as non Treated samples show no adhesion to solder Stress (Nmm -2 ) Displacement (mm) Resistance issues Sources of high resistance in CNT interconnects Scattering of electrons at metal/cnt interface causes higher resistance Defects along the tube For MWCNTs, caps need to be removed in order to allow conduction from all inner tubes
Future development work Electrical measurements will be made to assess contact resistance and compare with standard interconnects Quantify thermal conductivity and compare with solder-copper joints Thermal-cycling followed by shear and continuity tests to assess use in harsh environments Low-cycle and high cycle fatigue tests and compare reliability with standard solder joints Reduction in pitch size of interconnect to compare performance with current interconnects Using CNTs in electronic circuits Field effect transistors Interconnects Field emitters Flexible electronics
CNT FETs Semiconducting SWCNTs can be used as transistors Challenges: Fine control of chirality, purity, doping, defect minimization Directed placement/handling of individual CNTs: grown in place, or deposited after growth and subsequent processing Scalability/assembly Repeatable and reliable addressing and contact CNT interconnect Advantages Less susceptible to electromigration Lower resistance than copper Higher thermal conductivity Challenges Directed placement/handling of individual CNTs: grown in place, or deposited after growth and subsequent processing High contact resistance Poor adhesion to substrates Scalability
Field Emmission Saito et al., Jpn. J. Appl. Phys. 37 (1998) L346. Flexible and transparent devices Flexible thin film substrates Can be transparent Scalable high throughput printing techniques Source: Nature Nanotechnology A fully transparent aligned single-walled carbon nanotube transistors on a 4 inch glass wafer Source: American chemical society
Summary Summary Current technologies reaching their limits, performance limited by physical dimensions New materials need to be found to replace existing ones CNTs offer an alternative to existing materials CNTs have excellent electrical, thermal and mechanical properties CNTs suffer from high contact resistance, poor adhesion, defects that limit their applications
CNTs may replace metal interconnects in future integrated circuits In this project we aim to fabricate CNT interconnects and assess thermal, mechanical and electrical properties A fabrication process was devised and demonstrated A key step has been in improving adhesion of CNTs to solder Plans for further development of the interconnect technology were outlined