Design of Experiments for Board Level Solder Joint Reliability of PBGA Package under Various Manufacturing and Multiple Environmental Loading Conditions Haiyu Qi, Michael Osterman, and Michael Pecht CALCE Electronic Products and Systems Center University of Maryland, College Park, MD, 2742 USA E-mail: qihaiyu@calce.umd.edu, osterman@calce.umd.edu, and pecht@calce.umd.edu Abstract A design of experiments was conducted to determine the reliability of plastic ball grid array packages under various manufacturing and multiple environmental loading conditions. Parameters included conformal coating methods, underfill, solder mask defined and non-solder mask defined pads. Board level temperature cycling, vibration, and combined temperature cycling and vibration testing were performed to quantify the reliability and identify preferred design parameters. Through the main effects and interaction analysis, test results show underfill is the key parameter related to the solder joint reliability improvement. Conformal coat method and printed circuit board pad design are not main effects on solder joint reliability. interactive relationship exists among these three factors under temperature cycling loading, but some interactive relationship between printed circuit board pad type and the conformal coating method exists under vibration and combined loading conditions. 1. Introduction Plastic ball grid array (PBGA) packages are commonly used in commercial applications including most computer related products. BGA packaging offers higher density for a much greater distance between interconnects and improved electrical performance, e.g., a lower electrical inductance [1] [2]. Compared to leaded packages, without the concerns of lead coplanarity and bent leads, BGA packages are much more easily handled and assembled. In spite of the advantages of BGA packages over leadframe packages, designers of long-life, high reliability systems, such as aerospace, under-the-hood automotive, and some telecommunications applications, have been reluctant to use PBGAs because of concerns related to their ability to survive in harsh environments over long periods of time. For example, the types of environments that can be experienced in aerospace applications include: extreme temperature changes between take off and cruising altitude, and significant vibration levels over a wide range of frequencies [3]. Given that the commercial marketplace for electronic packages is technologically ahead of the aerospace industry and furthermore, the aerospace industry purchase volume is low compared to commercial yearly volumes, there is a critical need to explore and understand the use of commercially available packages for high reliability applications. In an effort to start understanding the implications of using commercially readily available packages for the high reliability requirement applications, a 2-level factorial design of experiment (DOE) was conducted. Three analyzed factors were the printed circuit board (PCB) pad type, underfilling of the ball grid array with epoxy, and conformal coating of the assembled PCBs. The test conditions included air-to-air temperature cycling, vibration testing, and combined loadings. Results from the experiment were used to provide guidelines on those parameters which significantly affect solder-joint reliability and determine means to improve reliability by making changes to specific parameters. 2. Design of Experiments Layout Three design parameters identified as being important to PBGA usage in aerospace environments are underfilling BGAs, pad type (solder mask defined, SMD vs. non-solder mask defined, NSMD), and conformal coating method (spray vs. dip) [4]. is widely used to improve BGA interconnect reliability under thermal cycling condition. The underfill epoxy adds life to the solder-joints by spreading out the CTE mismatch forces from only on the solder joints to across the entire substrate surface area. [4-9]. The fill pattern and particles distribution of underfill material are two important factors [9-1]. However, the PCB assembly process with underfiling is more complex and rework is extremely difficult.
The advantage of SMD pads vs. NSMD pads is to provide increased bonding force to the Cu traces in the PCB. Additionally, the SMD pad keeps moisture out of the PCB in the area of the pad. However, since the SMD pad rests on the Cu pad, the solder mask edge deforms the shape of the solder ball and the solder-mask will usually touch the solder-ball. It is the combination of the shape deformation and the impingement that causes the stress riser [4]. Rorgren et. al. [6] studied a number of different BGA packages reliability under harsh automotive-like environmental conditions. The environmental tests comprised temperature cycling from -4 to 1 ºC, with and without simultaneous exposure to vibration (8 G, 1-5 Hz) during the high temperature phase, as well as humidity cycling from 25 to 65 ºC at 93 % RH. The results show that non-soldermask defined (NSMD) pads on both board and package gives superior performance for the PBGA361, compared to when solder mask defined (SMD) pads are used. Conformal coatings are intended to provide electrical insulation and environmental protection thus minimizing the performance degradation to electronic PCB s by humidity, handling, debris, and contamination [12]. Conformal coating can be applied to the PCB by either spray or dip. The dip approach covers the entire PCB by dipping the PCB into the coating bath. The extraction rate shall be such as to obtain uniform thickness [13]. This method is more popular when PCBs are mostly populated with through-hole components [14]. conformal coating method works best with low-viscosity coatings since high-viscosity materials tend to sputter [14]. In this study, a design of experiments (DOE) was set up to investigate the effect of solder joint reliability due to various thermal and vibration stress conditions. Three design parameters were chosen as discussed above: underfilling, pad type, and conformal coating method. The focus was on two-level factorial design (see Table 1), in which each input variable was varied at high (+) and low (-) levels. Environmental tests included temperature cycling, vibration and combined loadings. For temperature cycling, the temperature range was -4 to 125 C which follows the JEDEC temperature cycling standard (JESD22-A14-B). A complete cycle is one hour with 15 minutes ramp times between extremes temperature and 15 minutes dwell times at the extremes temperature. Vibration test levels were set to.1 G 2 /Hz based on previous step stress studies [3, 4]. The random vibration load occurred over a frequency range of 1 to 1 Hz g 2 /Hz. Combined loading included both temperature cycling and vibration concurrently. A matrix for the tests is shown in Table 2. Each cell of the test is comprised of all groups from Table 1. 3. Experimental Setup Table 1. Factors for the design of experiments Design Factors Low (-) High (+) Conformal Coating Pad Type SMD NSMD Underfill Table 2. Summary of environmental tests Tests Level tes Temperature Cycling -4/125 C 15 minutes ramp and 15 minutes dwell Vibration.1 G 2 /Hz Frequency from 1 to 1 Hz Combined Loading -4/125 C &.1 G 2 /Hz Concurrently The experimental specimen consisted of 15 commercially available daisy-chained 272 PBGAs [15] mounted onto a FR-4 PCB. The packages have 272 balls in a partially depopulated array (4 perimeter ball rows and a 4x4 thermal ball area), with a ball pitch of 1.27 mm. The package itself is 27x27 mm sq. in size with solder mask defined ball pads of.635 mm diameter and.15mm thickness. Standoff of solder joint height is.45mm. Figure 1 shows the test board with the packages numbered. An underfill of Alpha Metals Staychip U181 and a conformal coating of Humiseal 2A64 polyurethane were applied to the assemblies. The approximate thickness of conformal coating is.5 mil, i.e., 1.27E-4mm. The general material properties of underfill and conformal coating are listed in Table 3. 2
Table 3. Material Properties Material Coefficient of Thermal Expansion (CTE) (ppm/ºc) Young s Modulus (MPa) Underfill 29.7 86 Conformal Coating 14 75 common U1 U7 U1 U2 U3 U4 U5 U6 U7 U8 U9 U1 U15 U11 U12 U13 U14 U15 Figure 1. Layout of a test vehicle During all of the experiments, the resistance of each daisy-chained circuit through each BGA was continuously monitored using an event detector. The advantage of this method is that any individual BGA interconnect failure will result in an increase in the resistance of the circuit. During a 6-second data logging interval, the event detector can detect any resistance over 3 Ohms [16] which persists for more than 12 microseconds and record it as an event. A BGA solder joint failure is reported when ten consecutive events are recorded. 4. Results and Discussions Experimental results under temperature cycling, vibration, and combined loading conditions were analyzed. The main effects and interactions between design parameters were identified using Minitab 14. 4.1 Temperature cycling test Eight test runs were carried out based on different design parameter combinations as Table 4 shows. The sample size for each design parameter combinations were 15. Of the 12 of packages tested, 52 failed after 4675 temperature cycles (hours). Based on distribution analysis, 2-parameter Weibull distributions were the best fit for the experimental results. Table 4 summarizes the Weibull shape factor and characteristic life with respect to the different design parameters tested. Weibull plots are shown in Figure 2. The last two test runs (NSMD-UF- and NSMD-UF-) in Table 4 did have any failures when the test was completed after 4675 cycles. Therefore, for these tests, we calculated the characteristic life using the largest shape factor obtained from SMD-UF- test run and assumed the first failure occurred at 4676, just one cycle after the test was completed. These Weibull characteristic lives were then chosen as the response characteristic for the two-level factorial design with eight runs to perform factorial design analysis. It needs to be aware some huge variation of shape factors observed in Table 4. For example, shape factor for SMD-UF- is 3.8 but 12.6 for SMD-UF-. It might indicate different failure mechanisms existing. Figure 3 shows a Pareto chart of the effects with response to the characteristic life. The y-axis in the Pareto chart shows the factors that potentially influence the response characteristics. The x-axis in the Pareto chart is the analysis result of absolute value of the effects. The larger the value, the greater is the influence on the response characteristics. A reference line was drawn on the chart based on Lenth's method 3
[17, 18]. Any factor with an effect which extends past this reference line is potentially important. In this case, underfilling is the only factor exceeds past this reference line. Therefore, underfilling is the most important effect on the response characteristics, i.e., solder joint fatigue life. The mean values of the response variable for each level of a factor were also plotted in Figure 3 as a main effects plot. A reference line at the grand mean of the response data was drawn in that plot. A main effect occurs when the mean response changes across the levels of a factor. The main effects plot shows there is no significant difference on the mean of solder joint fatigue characteristic life for different pad type and coating methods. However, packages with underfill significantly improved the solder joint durability compared to non-underfilled packages. This confirms the Pareto Chart observations that the underfilling has the greatest influence on solder joint fatigue life. Table 4. Times to failure under temperature cycling test Pad Type / SMD-UF NSMD-UF SMD-UF NSMD-UF Weibull 2-P Distribution Coating Confidence bounds Method Characteristic Life (.9, 2 sided) Shape Factor (β) (η, # of cycles) Low Upper Limit (η) Limit (η) 3.8 4682 4332 561 12.6 4415 4256 458 6.2 4861 4477 5278 7.3 4521 3924 528 7.1 523 4541 5961 4.6 5455 4694 69 12.6 5781 NA NA 12.6 5781 NA NA 4
Figure 2 Weibull plots of time to failure under temperature cycling test An interaction plot shows the impact that changing the settings of one factor has on another factor. Because an interaction can magnify or diminish main effects, evaluating interactions is extremely important. Parallel lines in an interactions plot indicate no interaction. The greater the departure of the lines from the parallel state, the higher the degree of interaction. The interactions plot in Figure 4 shows that there exists negligible interaction between PCB pad type and underfilling and only a little interaction between PCB pad type and coating method. On the other hand, underfilling has a high degree of interaction with the coating method. For example, the characteristic life of the underfilled package does not significantly change when the coating method changes from dip to spray. On the contrary, non-underfilled packages with spray coating have much better durability than those subject to dip coating. The reason that non-underfilled package with dip coating method has less durability is that some coating intrude under the package which can weaken the solder-joints due to coefficient of thermal expansion (CTE) mismatch. On the other hand, spray conformal coating will not get under the packages. For underfilled package, there is no chance for conformal coating intrusion under the package due to the existence of underfill. Therefore, the coating method does not significantly affect the reliability of underfilled packages. 5
Cube plots are used to show the relationships among eight factors with a response measure for 2-level factorial. The optimum design or designs can then be found from the cube plot. In this study, there are 2 designs with the same longest fatigue life (5781 cycles): NSMD-UF- and NSMD-UF-, based on our assumption. Taking into account the interaction plot observation, the optimum design parameters can be determined as NSMD-UF- in the temperature cycling study. If compared to the worst case with design parameters (SMD--UF), the characteristic life was improved around 31% using the optimum design parameters (NSMD-UF-). 4.2 Vibration test The vibration test board was clamped along the long edges with a card guide. The vibration stress level was set to.1 G 2 /Hz. The random vibration load frequency range was from 1 to 1 Hz. Of 12 packages tested (6 non-underfilled and 6 underfilled), 16 non-underfilled packages failed and 1 underfilled package failed. Table 5 shows the number of failures per the different design parameters. Since the locations of packages on PCB board can affect stress distributions and stress responses of packages, it is not appropriate to use any distribution to obtain the mean life or characteristic life for each test run. On the other hand, the number of failures for different design parameters provides a good response characteristic for DOE analysis because each test run was carried out under the same boundary and stress conditions. The Pareto chart in Figure 5 shows underfilling has the largest effect number compared to other factors, though it does not extend beyond the reference line. The main effects plot shows a main effect occurs when the mean response changes across the levels of the underfilling factor. Therefore, underfilling is the most important factor under vibration loading in this study, which is similar with the conclusion drawn from temperature cycling test. The interaction plot in Figure 6 shows that there exists the greatest interaction between PCB pad type and coating method. For example, when the PCB pad type is NSMD, dip coating method is better than spray coating method in terms of the number of failures. However, when the PCB pad type is changed to SMD, spray coating method is better than dip in terms of the number of failures. The cube plot in Figure 6 identifies three conditions for the least number of failures (): SMD-UF-, NSMD-UF-, and NSMD-UF-. Among them, NSMD-UF- was eliminated from the possible optimum designs based on the interaction plot observations. Therefore, NSMD-UF- and SMD-UF- can be considered as the best design. Compared to SMD-UF- design parameters, the reliability with the optimum design parameters was improved at least four times in terms of number of failures. Table 5. Number of failures under vibration test Pad Type / SMD-UF NSMD-UF SMD-UF NSMD-UF Number of Failures 4 4 6 2 1 4.3 Combined loading A combined temperature cycling and vibration test was conducted at -4/125 C and.1 G 2 /Hz stress level. The test exposure duration was 2175 hours. As mentioned before, different package locations can cause different stress responses under vibration loading conditions. Therefore, the same package location was chosen for DOE analysis under combined loading condition. Table 6 lists the time to failure of package U1s (see Figure 1) for all test vehicles. Since there was no failure observed for last test run (NSMD-UF-) when the test was completed after 2175 hours, the time to failure was then 6
conservatively assumed as 2176 hours, just one hour after the test was completed. The time to failure was then used as the response characteristic for DOE analysis. The Pareto chart and main effects plot in Figure 7 shows underfilling has the largest effect on solder joint time to failure. This observation is consistent with temperature cycling and vibration testing. The interaction plot in Figure 8 shows that there are no interactions between PCB pad type and underfilling, or between coating method and underfilling. An interaction exists between PCB pad type and coating method and the trend is the same as that under vibration loading, i.e., dip coating method is better than spray coating method for solder joint durability if PCB pad type is NSMD, but worse if the PCB pad type is SMD. From the cube plot in Figure 8, the optimum design parameters are identified NSMD-UF- in terms of time to failure. These design parameters are also found to be the best combination under temperature cycling and vibration testing. If compared time-to-failure between SMD-UF- and NSMD-UF- under combined loading, the durability under the optimum design parameters were dramatically improved with several orders. However, this comparison should only be used as a qualitative way, instead of quantitatively with considering the sample size and distribution. 4.4 Failure Analysis Table 6. Times to failure under combined loading test Pad Type / SMD-UF NSMD-UF SMD-UF NSMD-UF Time to failure (# of hours) 5 2 19 13 1983 1934 1432 2176 n-destructive and destructive failure analysis were performed on test vehicles when accelerated tests done. Electrical resistances of daisy-chained packages were measured using Fluke 75 multimeter. The failed packages were observed from either the electrical open or extremely high resistance number (at ~MΩ order). Several packages identified as having failed electrical probe tests were removed from boards for cross sectioning. Figure 9 through Figure 11 show shows the cross section images of some typical solder joint balls from non-underfilled packages under the various loadings. The observed failure mode was fatigue cracks that initiated from the comer and propagated through the eutectic solder. Cracks occurred at either or both the component side and the PCB board side. This is consistent with other observations [5, 19]. Crosssection work is being continued on the underfilled packages to identify the possible failure site. 7
Component Side Crack PCB Side Figure 9. A cross-section image of a failed solder joint (NSMD-UF-) under thermal cycling Component Side PCB Side Crack Figure 1. A cross-section image of a failed solder joint (NSMD-UF-) under thermal cycling Component Side Cracks PCB Side Figure 11. A cross-section image of a failed solder joint (SMD-UF-) under combined loading 5. Conclusions PBGA interconnect reliability was investigated through a 3-factors 2-level factorial design of experiments. These three factors were PCB pad type (NSMD or SMD), underfilling ( or ), and conformal coating method ( or ). Environmental conditions included temperature cycling, vibration, and combined temperature cycling and vibration. 8
Both Pareto charts and main effects charts identified the main factor among the three factors to be the underfilling, which has the greatest impact on solder joint reliability. For all environmental conditions, underfilled packages had better durability than non-underfilled ones. Through interaction analysis, an interactive relationship was found between underfilling and the coating method under temperature cycling loading. For example, the non-underfilled package with dip coating method was identified to be less durable than those subject to the spray coating method. The reason is the intrusion of coating under the package due to dip coating method, which caused enhanced CTE mismatch. On the other hand, spray conformal coating will not get under the packages and results in better durability. The interaction between PCB pad type and coating method was found under vibration loading and combined loading. For example, when the PCB pad type was NSMD, dip coating method was better than spray coating method for solder joint reliability. However, when the PCB pad type was changed to SMD, spray coating method had better durability than the dip method. Based on Cube and interaction plots, the preferred design parameters in terms of solder joint reliability were identified as NSMD pad type, with underfill, and dip coating method under all environmental conditions in this study. Therefore, these parameters may be considered as the base-line to design durable solder joint of PBGAs. 6. Acknowledgments The authors thank Manufacturers' Services Ltd. (MSL) for assembling test boards, and Motorola Inc., Honeywell Inc. and the CALCE Electronic Products and Systems Consortium for providing test facilities and performing tests. 7. References [1] Vardaman, E.J., Crowley, R., and Goodman, T., The Market for Ball Grid Array Packages, In: 1995 Japan IEMT Symposium. Proceedings of 1995 Japan International Electronic Manufacturing Technology Symposium, New York, NY, USA: IEEE, p. 25-7, 1996. [2] Bjorndahl, W.D., Selk, K., and Chen, W., Surface Mount Technology Capabilities and Requirements, 1997 IEEE Aerospace Conference, Proceedings, New York, NY, USA: IEEE, vol.4, p. 285-91, 1997. [3] Guha, R., Humphrey, D., Prodromides, K., Burnette, T., Koschmieder, T., Osterman, M., Qi, H., Kennedy, J. and Veum, J. Plastic Ball-Grid-Arrays (PBGA): Are They Ready for Environmentally Harsh Aerospace Applications?, 2WAC-149, World Aviation Congress & Display (WAC), Phoenix, Arizona, vember. 22. [4] Baumann, T., Burnette, T., Humphrey, D., Kennedy, J., Koschmieder, T., Osterman, M., Qi, H., Prodromides, K., and Veum, J., Underfilled PBGA Packages and Their Board Level Cycling and Vibration Performance, SMTA International 22, Rosemont, Illinois, Sept. 22. [5] Burnette, T., Johnson, Z., Koschmieder, T., and Oyler, W. Underfilled BGAs for a Variety of Plastic BGA Package Types and the Impact on Board-Level Reliability, Proc 51st Electronic Components and Technology Conf, Orlando, FL, May 29-June 1 21, p. 145 51, 21. [6] Rorgren, R., Tegehall, P.-E., Carlsson, P. Test Methods and Reliability Evaluation of BGA Packages for Automotive Electronics, Proceedings. The 34th ISHM-rdic Annual Conference. Molndal, Sweden: ISHM-rdic, 186/1-2, p. 179-85, 1997. [7] Johnson, Z. and T. Koschmieder, BGA Underfills, Advanced Packaging, vol. 1 #12, p. 29-33, Dec. 21. [8] Cho, S. and Han, B., Effect of Underfill on Flip-Chip Solder Bumps: An Experimental Study By Microscopic Moire Interferometry, The International Journal of Microcircuits and Electronic Packaging, Vol. 24,. 3, pp. 217-239, 22. [9] Okura, J.H., Shetty, S., Ramakrishnan, B., and Dasgupta, A., Guidelines to Select Underfills for Flip Chip on Board Assemblies and Compliant Interposers for Chip Scale Package Assemblies, Microelectronics Reliability, Vol. 4,. 7, pp. 1173-118, July 2. [1] Darbha, K., Okura, J.H. and Dasgupta, A., Impact of Underfill Filler Particles on Reliability of Flip Chip Interconnects, IEEE Transactions on Components, Packaging and Manufacturing Technology- Part A, Vol. 21,. 2, June 1998. 9
[11] Hang, Y., Bigio, D., and Pecht, M., Fill Pattern and Particle Distribution of Underfill Material, IEEE Transactions on Components and Packaging Technologies, Vol.27,. 3, pp. 493-498, September 24. [12] Zhang, K. and Pecht, M., Effectiveness of Conformal Coatings on a PBGA Subjected to Unbiased High Humidity High Temperature Tests, Microelectronics International, 17/3, p. 16-2, 2. [13] Workmanship Standard for Staking and Conformal Coating of Printed Wiring Boards and Electronic Assemblies, NASA Technical Standard, NASA-STD-8739.1, August 6, 1999, http://www.hq.nasa.gov/office/codeq/doctree/87391.pdf, (Oct. 11, 25) [14] Sprovieri, J., The thin polymer line, Assembly Magazine, Jan. 1, 23, http://www.assemblymag.com/cda/articleinformation/features/bnp Features Item/,6493,9854,.html, (Sep. 26, 25) [15] Motorola part #: DSYCHN-272PBGA. [16] Guidelines for Accelerated Reliability Testing of Surface Mount Attachments, IPC-SM-785, Institute of Interconnecting and Packaging Electronic Circuits, rthbrook, IL, v. 1992. [17] Pareto Chart of the Effects, Minitab Help, Minitab Release 14, 25 [18] Lenth, R.V. "Quick and Easy Analysis of Unreplicated Factorials," Technometrics, 31, p. 469-473, 1989. [19] Qi, H., Lee, M., Osterman, M., Lee, K., Oh, S., and Schmidt, T., Simulation Model Development for Solder Joint Reliability for High Performance FBGA Assemblies, 2th Semiconductor Thermal Measurement and Management Symposium, San Jose, California, March 9-11, 24. 1
Factor B A BC AB C AC ABC Pareto Chart of the Effects (response is Characteristic Life, Alpha =.5) 687.4 Factor A B C Name 2 4 6 Effect Value Lenth's PSE = 182.625 8 Main Effects Plot (data means) for Characteristic Life 55 Mean of Characteristic Life 525 5 475 45 55 525 5 NSMD SMD 475 45 Figure 3. Pareto chart of effects and main effects plot for characteristic life under temperature cycling loading 11
Interaction Plot (data means) for Characteristic Life 55 5 45 55 5 45 PCB Pad Type NSMD SMD Cube Plot (data means) for Characteristic Life 5781 5455 5781 523 4521 4415 4861 NSMD 4682 SMD Figure 4. Interaction plot and cube plot for characteristic life under temperature cycling loading 12
Pareto Chart of the Effects (response is Number of Failure, Alpha =.5) 4.235 Factor B BC AC ABC C Factor A B C Name AB A Lenth's PSE = 1.125 1 2 3 Effect Value 4 Main Effects Plot (data means) for Number of Failure Mean of Characteristic Life 4 3 2 1 4 3 2 1 NSMD SMD Figure 5. Pareto chart of effects and main effects plot for characteristic life under vibration loading 13
Interaction Plot (data means) for Number of Failure 4 2 4 2 PCB Pad Type NSMD SMD Cube Plot (data means) for Number of Failure 1 2 4 6 NSMD 4 SMD Figure 6. Interaction plot and cube plot for number of failures under vibration loading 14
Factor B ABC AC BC C AB A Pareto Chart of the Effects (response is Time to Failure (hours), Alpha =.5) 981 Factor A B C Name 5 1 15 Effect Value Lenth's PSE = 26.625 2 Main Effects Plot (data means) for Time to Failure (hours) Mean of Time to Failure (hours) 2 15 1 5 2 15 1 5 NSMD SMD Figure 7. Pareto chart of effects and main effects plot for characteristic life under combined loading 15
Interaction Plot (data means) for Time to Failure (hours) 2 1 2 1 PCB Pad Type NSMD SMD Cube Plot (data means) for Time to Failure (hours) 2176 1934 1432 1983 13 2 19 NSMD 5 SMD Figure 8. Interaction plot and cube plot for number of failures under combined loading 16