SEMATECH Symposium Korea 2012 Practical Analysis Techniques of Nanostructured Semiconductors by Electron Microscopy

Similar documents
Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Specimen Preparation Technique for a Microstructure Analysis Using the Focused Ion Beam Process

State of the art quality of a GeOx interfacial passivation layer formed on Ge(001)

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

Laser Spike Annealing for sub-20nm Logic Devices

Lecture 030 Integrated Circuit Technology - I (5/8/03) Page 030-1

Metallization. Typical current density ~10 5 A/cm 2 Wires introduce parasitic resistance and capacitance

The Significance of Bragg s Law in Electron Diffraction and Microscopy and Bragg s Second Law

Supplementary Figure S1 Crystal structure of the conducting filaments in sputtered SiO 2

MARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices

Materials Characterization for Stress Management

Conventional TEM. N o r t h w e s t e r n U n i v e r s i t y - M a t e r i a l s S c i e n c e

Metallization. Typical current density ~105 A/cm2 Wires introduce parasitic resistance and capacitance

Section 4: Thermal Oxidation. Jaeger Chapter 3. EE143 - Ali Javey

Interconnects. Outline. Interconnect scaling issues Aluminum technology Copper technology. Properties of Interconnect Materials

Atomic Layer Deposition of High-k k Dielectric and Metal Gate Stacks for MOS Devices

Chapter 2. Density 2.65 g/cm 3 Melting point Young s modulus Tensile strength Thermal conductivity Dielectric constant 3.

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005

Isolation Technology. Dr. Lynn Fuller

Lecture 8. Deposition of dielectrics and metal gate stacks (CVD, ALD)

p. 57 p. 89 p. 97 p. 119

Effect of High Pressure Deuterium Annealing on Performance and Reliability of MOSFETs with High-k Gate Dielectrics and Metal Gate

Effects of Lead on Tin Whisker Elimination

COMPATIBILITY OF THE ALTERNATIVE SEED LAYER (ASL) PROCESS WITH MONO- Si AND POLY-Si SUBSTRATES PATTERNED BY LASER OR WET ETCHING

Section 4: Thermal Oxidation. Jaeger Chapter 3

Low Resistance TiAl Ohmic Contacts with Multi-Layered Structure for p-type 4H SiC

Chemical analysis of Ti/Al/Ni/Au ohmic contacts to AlGaN/GaN heterostructures

Low contact resistance a-igzo TFT based on. Copper-Molybdenum Source/Drain electrode

Silicon Wafer Processing PAKAGING AND TEST

2. High Efficiency Crystalline Si Solar Cells

Chapter 5 Epitaxial Growth of Si 1-y C y Alloys

3.46 OPTICAL AND OPTOELECTRONIC MATERIALS

Transmission Kikuchi Diffraction in the Scanning Electron Microscope

New Materials as an enabler for Advanced Chip Manufacturing

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Kinematical theory of contrast

Electrical Characteristics of Rare Earth (La, Ce, Pr and Tm) Oxides/Silicates Gate Dielectric

EBSD Basics EBSD. Marco Cantoni 021/ Centre Interdisciplinaire de Microscopie Electronique CIME. Phosphor Screen. Pole piece.

Recrystallization in CdTe/CdS

ION-IMPLANTED PHOTORESIST STRIPPING USING SUPERCRITICAL CARBON DIOXIDE

1. Introduction. What is implantation? Advantages

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

R Sensor resistance (Ω) ρ Specific resistivity of bulk Silicon (Ω cm) d Diameter of measuring point (cm)

id : class06 passwd: class06

DIFFERENT MECHANISMS FOR SYNTHESIS OF NANOWIRES AND THEIR APPLICATIONS

Supporting Information

Contact Resistance Reduction using Advanced Implant and Anneal Techniques for 7nm Node and Beyond

High-Resolution, Electrohydrodynamic Inkjet Printing of Stretchable, Metal Oxide Semiconductor Transistors with High Performances

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

Blisters formation mechanism during High Dose Implanted Resist Stripping

Oxide Growth. 1. Introduction

Cu Wiring Process for TFTs - Improved Hydrogen Plasma Resistance with a New Cu Alloy -

2006 UPDATE METROLOGY

Materials Science for Achieving Green Innovation Thermoelectric Modules that Exploit Unutilized Heat for Revolutionizing Energy Conversion

TEM Study of the Morphology Of GaN/SiC (0001) Grown at Various Temperatures by MBE

Alternative Methods of Yttria Deposition For Semiconductor Applications. Rajan Bamola Paul Robinson

Production of PV cells

Advanced Gate Stack, Source/Drain, and Channel Engineering for Si-Based CMOS 6: New Materials, Processes, and Equipment

Rockwell R RF to IF Down Converter

High Temperature Oxygen Out-Diffusion from the Interfacial SiOx Bond Layer in Direct Silicon Bonded (DSB) Substrates

Measurement of thickness of native silicon dioxide with a scanning electron microscope

RHEED AND XPS STUDIES OF THE DECOMPOSITION OF SILICON DIOXIDE BY THE BOMBARDMENT OF METAL IONS

Schottky Tunnel Contacts for Efficient Coupling of Photovoltaics and Catalysts

Combinatorial RF Magnetron Sputtering for Rapid Materials Discovery: Methodology and Applications

GaAs nanowires with oxidation-proof arsenic capping for the growth of epitaxial shell

Fabrication Technology

National Semiconductor LM2672 Simple Switcher Voltage Regulator

Transmission Electron Microscopy. J.G. Wen, C.H. Lei, M. Marshall W. Swiech, J. Mabon, I. Petrov

Manufacturer Part Number. Module 2: CMOS FEOL Analysis

VLSI Technology. By: Ajay Kumar Gautam

Polycrystalline CdS/CdTe solar cells

INVESTIGATION OF ANTIPHASE DOMAIN BOUNDARY ENERGETICS IN GAAS-ON-SI(001)

Advanced CMOS Process Technology Part 3 Dr. Lynn Fuller

The growth of patterned ceramic thin films from polymer precursor solutions Göbel, Ole

Corrosion Protect DLC Coating on Steel and Hastelloy

Ex-situ Ohmic Contacts to n-ingaas

From microelectronics down to nanotechnology.

Focused Ion Beam CENTRE INTERDISCIPLINAIRE DE MICROSCOPIE ELECTRONIQUE. Marco Cantoni, EPFL-CIME CIME ASSEMBLEE GENERALE 2007

Transmission Electron Microscopy (TEM) Prof.Dr.Figen KAYA

THIN IMMERSION TIN USING ORGANIC METALS

EPITAXY extended single-crystal film formation on top of a crystalline substrate. Homoepitaxy (Si on Si) Heteroepitaxy (AlAs on GaAs)

Thermal Evaporation. Theory

Nanocrystalline structure and Mechanical Properties of Vapor Quenched Al-Zr-Fe Alloy Sheets Prepared by Electron-Beam Deposition

VLSI Systems and Computer Architecture Lab

What if your diffractometer aligned itself?

Kerf! Microns. Driving Forces Impact of kerf is substantial in terms of silicon usage 50 % of total thickness for 100 mm wafers

Copyright by. Puneet Kohli

Fabrication of Ru/Bi 4-x La x Ti 3 O 12 /Ru Ferroelectric Capacitor Structure Using a Ru Film Deposited by Metalorganic Chemical Vapor Deposition

EXCIMER LASER ANNEALING FOR LOW- TEMPERATURE POLYSILICON THIN FILM TRANSISTOR FABRICATION ON PLASTIC SUBSTRATES

Analysis of the Intermetallic Compound Formed in Hot Dip Aluminized Steel

Studies of the AZ91 magnesium alloy / SiO 2. - coated carbon fibres composite microstructure. IOP Conference Series: Materials Science and Engineering

Low temperature deposition of thin passivation layers by plasma ALD

Analysis of plating grain size effect on whisker

Ultra High Barrier Coatings by PECVD

Specimen configuration

MODEL PicoMill TEM specimen preparation system. Achieve ultimate specimen quality free from amorphous and implanted layers

Study of Phase Evolution in Sputtered Al/Ru Bi-layers Nanocrystalline Thin Films

Layout-related stress effects on TID-induced leakage current

Aging Treatment Characteristics of Shear Strength in Micro Solder Bump

Piezoresistance in Silicon. Dr. Lynn Fuller Webpage:

Transcription:

SEMATECH Symposium Korea 2012 Practical Analysis Techniques of Nanostructured Semiconductors by Electron Microscopy Jun-Mo Yang, Ph.D. Measurement & Analysis Team National NanoFab Center, Korea

Introduction Recent ULSI Si devices : the transistor size smaller than 30 nm Energy devices : solar cell, power device For process development and failure analysis : structural observation at the atomic scale : compositional analysis at the nanometer scale or the atomic scale FE-(S)TEM techniques combined with EDS and EELS are ideal for nanoscale analyses of real patterned samples. : practical spatial resolution of EDS and EELS of 1 2 nm : possible to analyze in the Å scale by Cs-corrected STEM Further, in order to evaluate a junction in Si devices, investigation of 2D dopant profiles of both vertical and lateral is very important. P 2

Recent FE-(S)TEM FEG CL Cs-corrector EDS Biprism Stage Screen EELS P 3 STEM Resolution: ~80 pm

Interface Analysis of Epi-Si(111)/Y 2 O 3 /Pr 2 O 3 /Si(111) Heterostructures

Cross Sectional TEM SF Epi-Si SF Epi-Si Y 2 O 3 Pr 2 O 3 Y 2 O 3 Pr 2 O 3 Substrate Substrate 50 nm 50 nm P 5

Cross Sectional TEM : Electron Diffraction Y 2 O 3 (666) Si (333) Si (422) Y 2 O 3 (466) Y 2 O 3 (655) Y 2 O 3 (266) Y 2 O 3 (455) Y 2 O 3 (644) Si (133) Y Y 2 O 3 (255) 2 O 3 (066) Si (222)+Y 2 O 3 (444) Y Si (311) 2 O 3 (055) Y 2 O 3 (244) Y 2 O 3 (433) Y 2 O 3 (633) Y 2 O 3 (044) Y 2 O 3 (233) Y 2 O 3 (422) Y 2 O 3 (033) Si (111)+Y 2 O 3 (222) Si (200) Y 2 O 3 (022) Y 2 O 3 (211) Y 2 O 3 (011) Pr 2 O 3 (202) T Y 2 O 3 (200) Pr 2 O 3 (301) P 6

Cross Sectional HRTEM Si (200) Si (111) Si (200) Epi-Si Si (111) Si (111) Y 2 O 3 Y 2 O 3 (222) Y 2 O 3 (211) Y 2 O 3 (200) Y 2 O 3 (011) Pr 2 O 3 A-IF P 7 Substrate Si (111) Si (200) Si (111)

Cross Sectional HR-STEM (a) Epi-Si BF-STEM (b) Epi-Si ADF-STEM 3 Y 2 O 3 Y 2 O 3 2 Pr 2 O 3 Pr 2 O 3 S I-O 1 S I-O Substrate Substrate 10 nm P 8

ADF-STEM/EELS of Interface Region : Pr 2 O 3 /Si (111) Intensity [ 10 3 ] Intensity [ 10 3 ] (a) 8 (b) O-K Pr 2 O 3 Thickness of Interfacial Oxide : ~1 nm S I-O Sub. 6 4 Pr-silicate 2 Interfacial Oxide 2 nm 0 200 150 (c) Si-L 1 Si Substrate 250 200 150 (d) 520 540 560 580 Energy Loss (ev) Interfacial Pr-silicate : By the direct chemical Pr-N reaction 4,5 between the Pr 2 O 3 and interfacial Si suboxide layer during post thermal process 100 50 Si-L 2,3 Si-L 1 Interfacial Oxide 100 50 Si-L 2,3 Pr 2 O 3 Pr-silicate 0 0 P 9 100 120 140 160 Energy Loss (ev) 100 120 140 160 Energy Loss (ev)

In Situ XPS/ADF-STEM of Interface Region : Y 2 O 3 /Pr 2 O 3 Normalized Y 3d (squares) and Pr 3d 5/2 (triangles) XPS intensity vs Y 2 O 3 layer thickness Pr x Y z O 3 mixed layer Pr 2 O 3 Bright Contrast Pr x Y z O 3 Changing Contrast Y 2 O 3 Dark Contrast P 10

Intensity [ 10 3 ] ADF-STEM/EELS of Interface Region : Epi-Si(111)/Y 2 O 3 (a) 150 (b) 120 Epi-Si Si-L 1 90 Epi-Si Y 2 O 3 3 2 1 2 nm 60 30 0 Si-L 2,3 Si-L 2,3 Si-L 1 Interfacial Oxide Y-silicate Y-M 4,5 3 2 1 P 11 It is not clear if there is a distinct interfacial layer at the boundary. 90 120 150 180 210 Energy Loss (ev) It seems that the Y-silicate and the interfacial oxide were initially formed with a total thickness of 1.2 nm when epitaxial Si was deposited on the Y 2 O 3 (111) surface, but the quantity of Si diffusion into the Y 2 O 3 layer surface was insufficient to result in an amorphization reaction towards a true Y-silicate interface layer.

Summary Epi-Si(111) Interfacial Oxide + Y-silicate Layer, ~1.2 nm Deficient Y-silicate Layer without an amorphization reaction Y 2 O 3 Pr 2 O 3 Amorphous Pr-silicate, >2 nm Interfacial Oxide, ~1 nm Si(111) Substrate Although the atomistic processes of the interface reactions differ, epi-si(111)/y 2 O 3 and the Pr 2 O 3 /Si(111) boundaries exhibit a similar bi-layer morphology, consisting of an interfacial Si suboxide in combination with a metal silicate layer. P 12

Nanoanalysis of the Poly-Si/Si Substrate Contact Surface

Analysis of the Poly-Si/Si Substrate Contact Surface As smaller DRAM design rule, contact resistance (Rc) of real cells became more critical. Generally, from the viewpoint of patterning process, Rc is mainly determined by both the effective contact area and the cleanness of contact surface. Commercial DRAM CELL STRUCTURE BL Plug W/L W/L W/L W/L FOX CAP 1 2 4 3 FOX 1 SN_SNC 2 SNC_LPC 3 LPC_N- 4 BLC_LPC P 14

HRTEM + EDS + EELS @ Poly-Si/Si Contact Bulk Plasma Residual oxide with C, F Original surface Perfect Crystal Sub. Si loss Normal Fail P 15

HRTEM + EDS + EELS @ Poly-Si/Si Contact 불량 No LET Si contact interface in ULSI device EELS, Chemical state of oxide P 16

Nanoanalysis of the Metal/Barrier Metal Interface

Analysis of the Metal/Barrier Metal Interface Al Al Metallization system of Al alloys/ti or TiN film : Ti or TiN films improve the reliability of the Al films by increasing the resistance against electro-migration in the films. : This migration is related to the texture of the Al films and to the formation of intermetallic compound layers at the interface between the Al and Ti or TiN films during heat treatment. : In order to develop improved metallization systems, a better understanding of the interfacial reactions is very important. In this study, solid-phase reactions at the Al-Si- Cu/Ti interface were precisely investigated at extremely high resolution by HRTEM and EDS combined with FE-(S)TEM. P 18 Nanoscale analysis on interfacial reactions in Al-Si-Cu alloys and Ti underlayer films

HRTEM + Nanodiffraction @ Al-Si-Cu/Ti film Al Al-Si-Cu/Ti film : Metallization in ULSI device A: TiAl 3 (112) (200) Al TiAl 3 B: Intermediate C 8.58A Ti 3 nm Al Ti Al A C 4.05A 3.85A (111) (200) (111)Al // (112)TiAl 3, [011]Al // [021]TiAl 3 Lattice mismatch: 4.9% along the a-direction 5.9% along the c-direction P 19

HRTEM + STEM + EDS @ Al-Si-Cu/Ti film P 20 Analysis Method - EDS map - Intensity profile, - k-factor correction - Quantitative analysis Results A 층의조성 Ti:Al:Si=1:3:1 C 층의조성 Ti:Si=1:1

2D Dopant Profile Measurement by Electron Microscopy Techniques

2D Dopant Profiling Techniques Investigation of junction profile in semiconductor devices is necessary to evaluate their electrical characteristics. Generally, 1D dopant profile can be obtained from SIMS and the 1D carrier profile can be derived from SRP. Owing to continuous shrinkage of n + (As) WSix Poly-Si Channel n + (As) LDD semiconductor devices, investigation of 2D junction profiles of both vertical and lateral became p- well (B) very important with real patterned samples. Si substrate So, various analysis techniques have been developed to obtain 2D information for junction profiles. In this presentation, we show chemical etching, SCM and LV-SEM techniques for 2D dopant profiling. P 22

Junction Delineation by Chemical Etching Technique P 23 Junction delineated SEM image of the n-mos region after the RTA treatment. (a) and (b) were obtained by dipping for 1 s and 5 s in the solution of HF:HNO 3 = 1.5:200, respectively. (a) Cross-sectional TEM image obtained in the n-mos region. (b) Junction delineated TEM image of (a). Delineation was carried out for 3 s with the solution of HF:HNO 3 = 1.5:200.

2D Dopant Profiling of MOSFETs by LV-SEM p-mosfet Power MOSFET Gate n - epi p + p + n - well 300 nm p - sub 50 μm n + n + p - base n + p - base n + n - epi 3 μm n - epi 5 μm P 24

Thank you for your attention!