Short Title: Full Title: IC Layout and APPROVED IC Layout and Module Code: CAEE H3002 Credits: 4 NFQ Level: 7 Field of Study: Electronics and automation Module Delivered in 2 programme(s) Reviewed By: JAMES WRIGHT Module Author: PATRICK O FRIEL Module Description: The objective of this course is to familiarise students with the process of implementing a MOS device using full custom layout and verification techniques. Students will use state-ofthe art CAD tools to design, simulate, and complete mask level layout of a circuit before finally fabricating the device in the college laboratory. Learning Outcomes On successful completion of this module the learner will be able to: LO1 LO2 LO3 LO4 LO5 LO6 LO7 Describe the component technologies in use in the electronics industry. Describe the structure and layout of MOS devices. Create and simulate transistor level designs. and implement MOS devices using custom layout tools, requiring layout, simulation, DRC ( Rule Checking) and LVS ( Layout versus schematic). Describe the basic process steps in the fabrication of MOS devices. Apply their knowledge in a team based design project that involves the verification of silicon layout and fabrication of a semiconductor device in the college laboratory. Present the design project in a formal report. Pre-requisite learning Co-requisite Modules No Co-requisite modules listed
Module Content & Assessment Content (The percentage workload breakdown is inidcative and subject to change) % Target Technologies Overview: Overview of Standard Cell and Full Custom methodologies. Process technologies for NMOS, PMOS and CMOS. Layout: Layout of active, poly and metal layers, laying out of diffusion Wells, Contacts and Vias. Standard Cell frame layout. Floorplan for power and ground. Verification: IC design rules, LVS, DRC and device simulation. Measurement of device propagation delays and output rise and fall times. Power consumption measurement. Laboratory Process Flow: PMOS Process Flow and Layout of a basic semiconductor device such as a Diode or PMOS transistor for fabrication in the college laboratory. Overview of laboratory process and rule. Measurement Evaluation of resistivity and mobility, 4-point probe measurement of resistivity, PN-Junction capacitance, determination of carrier concentration, electric field and depletion layer width with CV measurements. 10.00% 25.00% 20.00% 30.00% 15.00% Assessment Breakdown % Course Work 100.00% Course Work Assessment Type Assessment Description Outcome addressed % of total Assessment Date Continuous Assessment Simulation of MOS transistors. 3,7 15.00 4 Continuous Assessment Lab assessment in layout/simulation. 1,2,3 15.00 6 Continuous Assessment Layout and simulation of device for fabrication. 3,4,7 25.00 8 Continuous Assessment Lab assessment in layout/simulation. 2,3,4 15.00 10 Continuous Assessment Device test and performance 5,6,7 15.00 11 Continuous Assessment Project Report 1,2,3,4,5,6,7 15.00 Sem 1 End No End of Module Formal Examination IT Tallaght reserves the right to alter the nature and timings of assessment
Module Workload Workload: Full Time Workload Type Workload Description Hours Frequency Average ly Learner Workload Lecturer/Lab No Description 4.00 Every Independent Learning No Description 3.00 Every 4.00 3.00 Total ly Learner Workload 7.00 Total ly Contact Hours 4.00 Workload: Part Time Workload Type Workload Description Hours Frequency Average ly Learner Workload Lecturer/Lab No Description 4.00 Every Independent Learning No Description 3.00 Every 4.00 3.00 Total ly Learner Workload 7.00 Total ly Contact Hours 4.00
Module Resources Required Book Resources Dan Clein; technical contributor, Gregg Shimokura 2000, CMOS IC layout, Newnes Boston [ISBN: 0-750671947] Christopher Saint, Judy Saint 2002, IC layout basics, McGraw-Hill New York [ISBN: 0-071386254] This module does not have any article/paper resources This module does not have any other resources
Module Delivered in Programme Code Programme Semester Delivery TA_EAELE_D Bachelor of Engineering in Electronic Engineering 6 Elective TA_EELEC_D Bachelor of Engineering In Electronic Engineering 6 Elective