I N S T I T U T D E R E C H E R C H E T E C H N O L O G I Q U E Optimization of optical performances in submicron silicon-on-insulator rib and strip waveguides by H thermal annealing Erwine Pargon 1, Cyril Bellegarde 1, Corrado Sciancalepore, Camille Petit-Etienne 1, Marc Fouchier 1, Vincent Hughes, Philippe Lyan, Jean-Michel Hartmann 1 CNRS-LTM, Univ. Grenoble Alpes CEA-LETI, Grenoble Workshop IRT, Paris 7-11-017
Advanced Silicon photonic integrated circuit High performance Si photonics platform on advanced CMOS technology is a key to produce low-power integrated photonic chips for the optical interconnect in data transmission Requirements: Hybrid III-V/silicon Photonic integrated circuit Ultra-low-power active devices integrated on SOI substrate Ultra-low-loss passive devices elaborated in SOI substrate Goal: achieve ultra low-loss silicon waveguides Si patterning has a key role
Optical losses in Si/SiO Waveguide Waveguide architecture Loss by roughness scattering 310*360 cross-section waveguide on 800nm thick SiO BOX 3.5 3.5, ξ = cste α (db/cm) 1.5 1 0.5 SOI substrate: Si 310nm /BOX 800nm Sources of optical loss: Absorption in bulk Substrate leakage Non-linear effects Scattering by sidewalls roughness 0 0 0.5 1 1.5.5 Width (um) Width α= ( ξ,,β) With: = roughness amplitude ξ = correlation length β = modal propagation constant 4 from F. P. Payne, J. P. R. Lacey, Optical and Quantum Electronics 6, 977 (1994)
Rib and Strip Waveguides Strip Si/SiO waveguide Rib Si/SiO waveguide Si 310 nm Si 150 nm BOX 800 nm BOX 800 nm Si Substrate Si Substrate More confined mode Strong interaction with sidewalls High scattering loss How to achieve low scattering loss? FromPayne and Laceysmodel: α<1 db/cm if σ<0.3 nmfor any ξ State of the art Si roughness: σ= 1nm (immersion 193nm lithography) ξ=0nm Payne and lacey: α=5.4 db/cm Littérature: 1.3 db/cm Horikawa et al., MRS Communication, vol. 6, 015 Less confined mode Less interaction with sidewalls Lower scattering loss STRIP case, Width=350nm, λ=1310nm 0.3 nm
Roughness transfer during silicon patterning The significant sidewalls roughness of Photoresist pattern after lithography is transferred into the silicon during the subsequent plasma etching process 193nm resist after lithography Silicon after plasma etching Roughness transfer LER (=3σ): after lithography : 4.3 nm Si LER : 4.3 nm Minimize the resist mask roughness before pattern transfer by introducing post-lithography resist treatments Reduce the Si roughness by post-etching treatment H thermal annealing
Roughness metrology PSD CD-SEM Top view roughness measurement: Average roughness along the pattern height y N 1 = σ réel πn m= N + 1 e Power spectrum density (nm 3 ) m y α ξ cos( k n y m y)( N m ) + σ π Spectral analysis of the roughness Estimation of the roughness parameter: amplitude (σ) and correlation length (ξ) 10 1 Self affine fractal function ξ 0.1 1E-3 0.01 0.1 Wavenumber k (nm -1 ) bruit White noise Echantillon Angle variable AFM on tilted sample Axe de rotation Roughness estimation all along the pattern heigth Line edge roughness (LER) =3σ 6
Process flow Waveguide patterning by top-down approach in ICP reactor Strip Waveguide finishing -HM deposition - nd Lithography - HM + Si etching - Oxide deposition 1.1µm RIB Optical measurements @1310nm Optical Losses α (db/cm) H thermal annealing
H annealing post-etching treatments: Strip waveguide Thermal annealing under H ambient leads to surface atomic migration Si reflow Rounded and swelled waveguides but dimension respected Without H annealing 314 450 With H annealing 317 436 LER (nm) Roughness smoothening 4 3 1 0 4.3 Without H annealing 8% LER decrease 0.75 With H annealing σ=0.5nm PSD LER (nm 3 ) 100 10 1 ξ >50nm Without H annealing With H annealing 1E-3 0.01 0.1 Wavenumber k (nm -1 ) 850 C / 0 Torr / min ξ =17nm Significant roughness decrease while maintaining acceptable guide profile
Impact of H annealing on optical losses in Strip waveguides α (db/cm) Optical Losses @ 1310nm 8 6 4 0 4.4 1.3 1 db/cm Without H annealing With H annealing 0.8 0. 5.6 0.44.6 00 300 400 500 600 700 800 900 Waveguide width (nm) 1.6 0.37 α(db/cm) 0 18 16 14 1 10 8 6 4 0 5 Experimental losses vs calculated scattering losses (with Payne and Laceys model) High roughness case (without H annealing) Loss in bend Simulated scatetring loss Experimental loss 00 300 400 500 600 700 800 Waveguide width (nm) Scattering loss : main cause of propagation loss (except below 300nm) Low roughness case (with H annealing) 80% loss reduction 1dB/cm target is achieved when CD>380 nm 1.3 db/cm @ 300nm α(db/cm) 4 3 1 0 Simulated scatetring loss Experimental loss 00 300 400 500 600 700 800 Experimental loss> calculated scattering loss Other sources of losses (substrate leakage, defect at Si/SiO interface) become non negligible Waveguide width (nm)
H annealing post-etching treatments : Strip vs RIB 850 C / 0 Torr / min Strip Rib Severe reflow of the RIB structure Roughness metrology issue by CD-SEM AFM measurements The presence of the SiO / Si interface in the strip case limits the Si reflow: H annealing conditions have to be adapted to RIB structure Compromise to be found between roughness reduction and shape conservation
Hydrogen annealing: Temperature Impact Profile and roughness Annealing at 0 Torr 1min Optical Losses @ 1310nm 1.5 θ = 87 LER =.6 nm θ = 83 LER = 1. nm θ =54 LER = 0.76 nm Optical losses (db/cm) 1. 0.9 0.6 0.3 1.9 0.55 0.76 1.7 1 0.4 0.84 0.67 0.38 0.45 0.9 300 400 500 600 700 800 Waveguide width (nm) No annealing 800 C/0 Torr/1 min 850 C/0 Torr/1 min 0.5 Increasing annealing temperature: Pattern Shape deformation Enhanced LER reduction Significant optical losses reduction with annealing temperature Pattern profile deformation 1 does not seem to be an issue for optical transmission
Hydrogen annealing: Pressure Impact Profile and roughness Annealing at 850 C, 1 min Optical Losses @ 1310nm θ = 87 LER =.6 nm θ = 54 LER = 0.76 nm Increasing pressure θ =70 LER = 1 nm Optical losses (db/cm) 1.5 1. 0.9 0.6 0.3 0.86 0.76 1.7 0.5 0.84 0.47 0.5 0.55 0.4 0.38 0.9 0.18 300 400 500 600 700 800 Waveguide width (nm) No annealing 850 C/0 Torr/1 min 850 C/60 Torr/1 min Limit pattern Shape deformation and LER reduction Optical loss reduction follows LER reduction High pressure 1annealing conditions interesting in terms of shape preservation and optical results
Conclusion: Rib VS Strip Strip Waveguide Annealing at 850 C/0 Torr/ min Rib Waveguide Annealing at 800 C/0 Torr/8 min Annealing at 850 C/60T/1 min 145 44 $% x 150# LER = 0.75 nm Losses (CD~436nm) = 0.8dB/cm LER = 1 nm Losses (CD~44nm) = 0.49dB/cm H annealing post-etching treatment shows interesting capabilities to decrease Si sidewalls roughness and thus reduce scattering optical losses Record low loss values could be obtained for Strip and Rib waveguides while maintaining acceptable profile and width dimension Find the optimal H annealing conditions to be applied to all Si components elaborated in the SOI substrate 18
InP laser etching in Cl /CH 4 /Ar Cl /CH 4 = 0.65 Cl /CH 4 = 0.5714 LER analysis by AFM LER= 13nm LER= 5nm Sidewalls stoechiometry analysis by Nanoauger In/P=1.15 In/P=1.6 ER= 800nm/min Selectivity InP/SiO = Top view Section Optical analyses by cathodoluminescence And DOP
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