Reliability in Large Area Solder Joint Assemblies and Effects of Thermal Expansion Mismatch and Die Sizen

Reliability in Large Area Solder Joint Assemblies and Effects of Thermal Expansion Mismatch and Die Sizen Jun He, W. L. Morris, M. C. Shaw, J. C. Mather* and N. Sridhar Rockwell Science Center 1049 Camino Dos Rios Thousand Oaks, California 91358-0085 Phone: 805-373-4688/ 4504/ 4444/ 4774 Fax: 805-373-4017 e-mail: jhe@rsc, wlmorris@rsc, mcshaw@rsc, and sridhar@rsc.rockwell.com *Rockwell Collins Inc. 400 Collins Road NE Cedar Rapids, Iowa 52498 Phone: 319-295-1910 Fax: 319-295-3751 e-mail: jcmather@collins.rockwell.com n Best Paper of IMAPS 98 Conference. Abstract Current applications for high power electronic devices such as microprocessors, communications devices and power transistors demand solder joints with well known reliability under a wide range of conditions. This reliability represents a major design challenge requiring detailed information about the constitutive response of the solder joints and the manner in which they impart stress to the overall module assembly. In this paper, the investigators will describe some recent progress on the relationships between CTE mismatch, die size, and the expected reliability of the package. An experimental test matrix has been constructed of specimens comprised of direct die bonded Si test vehicles to include various 1) solder alloys; 2) silicon die sizes; 3) substrate CTEs. The absolute magnitudes and spatial distributions of thermal residual stress in silicon dice are measured directly by Raman piezospectroscopic techniques. The measured stress profiles are critically compared with both analytical models and Finite Element results. Based on these comparisons, a number of common assumptions in stress analyses and their applicability are addressed. Finally, the implications of these findings on the device and the solder joint reliability are discussed. Key words: 1. Introduction Raman Piezospectroscopy, Thermal Stress, Solder Joint, Die Fracture, Finite Element Model, and Reliability. Semiconductor devices capable of dissipating significant power are widely used for computers, power supplies, motor controls, and automotive electronics. All devices have finite on-state voltage drops when conducting the on-state currents and finite switching times during turn-on and turn-off. These effects result in significant power dissipation in the system that needs to be removed through electronic packaging. For example, in a typical IGBT based motor drive, 4% of the controlled power is dissipated as heat within the device, 297

Intl. Journal of Microcircuits and Electronic Packaging that is, 1500 W for a 50 Hp drive. Therefore, thermal management is one of the key packaging issues requiring the use of highly thermally conductive substrates and baseplates. Typical substrates may exhibit coefficients of thermal expansion (CTE) that are several times that of silicon and other common semiconductors. As a result, thermal residual stress, r, is developed in the devices, solder interconnections and substrates during package assembly, which typically involves high temperature exposure. Indeed, in cases where high power semiconductor devices are utilized, significant stresses can develop and cause mechanical failure, or lead to changes in the operational characteristics of the device. In addition to the mismatch in CTEs, the maximum thermal stress in the device is also proportional to the die area up to a certain critical size 1. A great deal of study, both analytical and numerical, has been devoted to thermal stress problems in joining materials with different CTEs. Almost all of the research findings are based on the classical work achieved by Timoshenko 2. This theory, however, predicts only the in-plane normal stress in the assembly components, and is based on the assumption that this stress is uniformly distributed over the assembly length. This work has been followed by more sophisticated analyses including the effect of interfacial shear and peeling stresses 3-5. In a direct application to electronic assemblies, Suhir 6 has provided an insightful approximation where all principal stress components can be estimated by very simple closedform formulas. In contrast to the relatively large number of theoretical studies, until recently there has been no experimental comparison available to help validate the solutions. Furthermore, direct experiment data are needed in order to obtain the in-situ constitutive properties of solder and joint materials. In the present paper, the authors describe a systematic study on the reliability of large area die attaches. An experimental test matrix has been constructed of specimens comprised of direct die bonded silicon test vehicles to include various 1) solder alloys; 2) silicon die sizes, 3) substrate CTEs. The detailed distributions of thermal residual stresses in silicon die are measured directly by a novel piezospectroscopic technique based on Raman spectra from silicon 7. Results are then compared to Finite Element analyses as well as Suhir s equations. Based on these comparisons, a number of common assumptions in stress analyses and their applicability are addressed, especially in terms of edge effects and interfacial peeling stresses. These results are then related to the strain distribution within the solder layer utilizing simple micromechanics concepts. Finally, implications on the solder joint reliability are discussed along with a number of different die fracture modes observed during thermal cycling. 2. Theoretical and Experimental Methodology 2.1. Silicon Raman Piezospectroscopy Piezospectroscopy is concerned with the effect of strain on the spectroscopic properties of solids. In a typical measurement, a laser beam is focused on the sample by an optical microscope to obtain a spectral signal (fluorescence or Raman). Analysis of the frequency and the width of intensity peaks in such spectra reveals the local state of stress. The technique is non-destructive and can be used to analyze regions just a few microns in dimension. In the present work, Raman spectra were obtained from silicon surfaces in a backscattering configuration using the 514.5-nm line of an argon laser and a beam power of 10 mw. The dimensions of the probed region were less than 2 µm in diameter and 20 nm in depth, such that only the near-surface region is investigated. Specimens were moved with an X-Y translation stage in minimum steps of 0.01 mm. The relationship between the Raman frequency shift, Du, and the bi-axial stress state, r xx + r yy, is of the form, Du = S(r xx + r yy ) (1) where S = -1.92 Rcm -1 /GPa 7. The measured shift is thus proportional to the sum of the two in-plane stress components, r xx + r yy. The Raman signal of a freestanding c-silicon wafer is used as the stress-free standard. 2.2. Specimen Preparation Each test article was fabricated using three square silicon test chips, 0.2, 0.6 and 1.0 inch in dimension (Figure 1). The devices were attached to ¼ inch metal substrates, including copper, mild steel and Kovar, with 50 µm thick continuous solder layers. Die attachment materials included four common solder alloys (Table 2). Soldering was achieved in all cases by heating the test article above the liquidus temperature of the solder alloy (Table 2), in a reducing environment. After bonding, the test articles were cooled to room temperature by controlled nitrogen flow with typical cooling rates of 1 C/s. Following fabrication, the quality of each solder joint was evaluated by a high frequency ultrasonic C-scan imaging technique that confirmed good quality joints with only a relatively small area fraction of disbonds/voids. 298

h c Stress, σ xx + σ yy Silicon Chip 1/4 inch metal Substrate H Z Y X Solder, h s Table 1. Material properties used in the analyses. Material Modulus E (GPa) CTE α (ppm/k) # Plane Strain Modulus, E/(1-ν) (GPa) Copper 126 17.4 191 Mild steel 207 11.0 --- Kovar 138 5.3 --- 80Au20Sn 59 16.8 98 within {100} plane 130 169 3.1 180 within {110} plane 130 187 3.1 180 229 Silicon within {111} plane 169 3.1 229 #Values averaging over 0-200 C Figure 1. Schematic of test article configuration including coordinates and notations. Table 2. Solder constitutive properties in layered joints obtained from analysis of experimental data. Solder Alloys Shear Yield Critical Die Stress Onset Temperature, T* ( C) Liquidus Strength, τy Size #, H* (mm) Isotropic. FEM Modified Suhir Anisotropic. FEM Temperature ( C) 80Au20Sn 270 4 259 271 302 280 95Sn5Ag 24 8.2 191 199 222 240 97.5Pb1.5AG1Sn 11 22 177 185 205 309 63Sn37Pb 8 22 137 143 159 183 # Based on 200 µm thick device attached to ¼ inch thick copper substrates 2.3. Finite Element Analysis The various stress component values reported below were obtained using elastic Finite Element models of a 1/8 symmetric section of the test sample, meshed with 18,000 elements, primarily bricks (Figure 2). The models included the base plate in full detail, as the silicon baseplate edge spacing was found to affect the calculated stresses slightly. Note the mesh element density is highest near the free edge and corner where large stress gradients are expected. Despite the well-known anisotropy of silicon (Table I), isotropic physical properties have been used in most of the previous investigations with no attempt to qualify this approximation. Therefore, the researchers calculate the stress distribution in the die using an assump- Cosh( kx) σ xx( x) + σ yy ( y) = σ 0 2 (1+ ν ) (2) c H tion of an isotropic modulus as well as cases where they incorporate Cosh k 2 the full stiffness tensor of the silicon. The copper and solder moduli are assumed to be isotropic, with an average value of CTE over the 1 temperature range of interest. and k = ( G ( ) ( ) 2 s 1 νc / Echchs 2. E c and u c are the Young s modulus and Poisson s ratio of the device, respectively. r 0 is the maximum in-plane thermal stress that can be reached in the die. Equa- Solder Die tion (2) can be extended to general cases by simply replacing r 0 and k by Suhir s definition 6. Both equations will be plotted along with the FEM results in comparison with Raman data as described below. Copper The experimentally measured stress distribution along the midplane of the 1 inch square silicon device bonded on ¼ inch copper substrates is shown in Figure 3 for four solder alloys. The device thickness is 200 µm. Experimental results based on Raman piezospectroscopic measurements are shown as points, and the predictions of the numerical models fitted to the data are shown as either solid and dashed lines, based, in turn, on plastic and elastic Figure 2. 1/8 symmetric mesh used in FEM analyses. responses of the solder, respectively. The 80Au20Sn solder follows the elastic behavior predicted by Equation (2), in which the stress 3. Results and Discussion 3.1. Thermal stresses in devices 1) Effects of chemical composition of solder alloy: As demonstrated previously 1,7, the thermal stress distribution in such devices can be divided into two regions, a transient region near the die edge, defined in this case as the shear-lag zone, where the in-plane stress increases with position from the edges, and a central region of constant, spatially-invariant stress (Figure 3), defined in this case as the plateau region. The magnitude and distribution of these thermal stresses are governed by the CTE mismatch, the elastic and the geometric properties of the device, the substrates and most importantly by the solder shear yield strength t y and creep rate. The elastic stress distribution within shear lag zone has been calculated by Suhir 6 under the plane strain approximation, where dimension of y- direction is assumed to be infinite. When the length and width of a device are comparable to each other, such an approximation breaks down and the modified stress distribution at the mid-plane of the device is given under thin film limit 7, 299

Intl. Journal of Microcircuits and Electronic Packaging rises rapidly with increasing position from the edges, and the length of elastic shear lag zone is determined to be 2 mm in this case. For most of solder alloys, however, the shear yield strength, which is the maximum sustainable shear stress, is far less than the interfacial shear stress required by the rapid stress buildup near the edge. In these cases, the in-plane stress increases linearly with the distance from the edge before reaching its maximum value as given by Reference 7, σ XX τ ( x) = y ( H / 2 x ) for( H / 2 x ) hc for( H / 2 x) > L σ 0 L where the plastic shear lag zone length L = r 0 h c /t y. Results in Figure 3 clearly demonstrated the plastic response of three solder alloys with the values of t y determined by fitting the data using Equation (3). Thermal Stresses, σ xx +σ yy -200-400 -600-800 -1000-1200 -1400 95Sn5Ag 80Au20Sn σ xx 63Sn37Pb 97.5Pb1.5Ag1Sn σyy -10-5 0 5 10 Position along x axis(mm) Figure 3. Stress distributions in silicon die attach on copper after fabrication. In addition to the shear lag zone size, the solder composition also determines the value of r 0. It is well known that the maximum thermal stress is proportional to DaDT. In this case, Da is the difference in CTE between the substrate and the device and DT is the temperature range over which the stresses develop. Note that DT does not correspond to the difference between the processing temperature and room temperature, T room ; instead DT is defined as, (3) at the center of the 1 inch die to the analytical and FEM models. As shown in Table 2, there is considerable discrepancy in the value of T* using different models. 2) Die size dependence and critical die size: If the lateral dimension of the device, H, is less than twice the elastic or plastic shearlag length, L, the stress within the die never reaches the maximum level, or plateau, dictated by the CTE mismatch between the device/ substrate and the creep of the solder material. That is, the maximum stress thus depends on the device dimension, but only for devices smaller than a critical size. In turn, as shown in Figure 3, this critical size is inversely proportional to the shear strength of specific solder alloy used to attach the device to the substrate. This critical die size H* is equal to twice the length of shear lag zone. It also applies to both stress components, r xx and r yy, below which both the edge and center stresses are less than their peak value. One example of this phenomenon is demonstrated in Figure 4, in which experimentally measured stress distributions are presented from devices of different sizes (0.2, 0.6 and 1.0 square inches) attached to copper by 80Au20Sn eutectic solder (cf. Figure 2). For the 0.6 and 1.0 inch silicon devices, the distributions of residual stress within the elastic shear lag zone are essentially identical. The primary difference is only observed in the differing lengths of the constant stress zone within the device interior. On the other hand, the overall magnitudes of thermal stress in the 0.2 inch device are significantly smaller, indicating that the size of the device is well below H* for 80Au20Sn eutectic solder. Thermal Stress, σ xx +σ yy -300-400 -500-600 -700-800 -900-1000 -1100 σ xx σyy -10-5 0 5 10 80Au20Sn h c =500µm Figure 4. Thermal stress in silicon devices attached to copper substrates. DT = T*-T room (4) 3) CTE mismatch of devices and substrates: Both shear lag zone length and maximum thermal stresses have strong dependence on where T* is designated as the stress onset temperature, below which the value of Da. In the present investigation, Kovar, mild steel and the creep of solder alloy is so slow in comparison to cooling rate that copper have been used as substrate materials; the resulting values of there is no notable stress relaxation during subsequent cooling. Due Da are 2.2, 7.8 and 14.3 ppm/k, respectively. The in-plane thermal to the complex nature of solder creep processes and their dependence on the actual processing conditions, the value of T* can be shown in Figure 5. Values for both L and r 0 stresses of 80Au20Sn die attach using these three substrates are decrease dramatically determined only through experiments. In the current study, DT and by lowering the CTE mismatch. T* are determined by matching the experimentally measured r The International Journal of Microcircuits and Electronic xx +r Packaging, yy Volume 21, Number 3, Third Quarter 1998 (ISSN 1063-1674) 300

Thermal Stresses, σ xx +σ yy -200-400 -600-800 -1000-1200 -1400 σ xx Kovar σyy Mild Steel Copper 80Au20Sn h c =500µm -10-5 0 5 10 Thermal Stresses, σ xx +σ yy -400-600 -800-1000 -1200-1400 200µm silicon/80au20sn/1/4 inch copper Anisotropic FEM Modified Suhir He&Sridhar -10-5 0 5 10 Figure 5. Thermal stress in 1 inch silicon devices attached to 3 different substrates. Figure 6. Comparison of Experimental data and various theoretical models for in-plane stresses. 3.2. Comparison and Verification of Analytical and FEM models All analytical and FEM models compared so far are based on elastic calculations. Therefore, the 80Au20Sn die attach on copper was chosen as the test case in comparing the results of Suhir s equations and FEM analyses to the experimental data. In this thin film limit case (Equation (2)) and Suhir s models, silicon is assumed to be isotropic, so the plane strain modulus, E/(1-m), is taken as the average value of that along [100] and [110] direction (Table 1). In the case of FEM analyses, both isotropic and anisotropic computations are performed. 1) In-plane and interfacial shear stress distribution: The measured distribution of in-plane die stresses (circles) is plotted in Figure 6 along with the predictions based on this thin film limit solution, modified Suhir s equation (Equation (2)) and FEM analysis using the full stiffness tensor for silicon. Note that the value of DT for all three models has been adjusted to match the experimental stress value at the device center. The corresponding value of stress onset temperatures T* are listed in Table 2. All three models predict similar stress profiles; however, Suhir s formula gives a much longer shear lag zone than the experimental data indicates, and this thin film approximation under-predicts the value of L. On the other hand, there is extremely good agreement between the FEM model using the full stiffness tensor and the experiment results. The shear stress at the silicon/solder interfaces t s, or r xz and r yz, is also compared in Figure 7. Both numerical and analytical models predict a monotonic increase of shear stress approaching the free edge. Suhir s formula underestimates the maximum shear stress by more than 50%. The FEM model, assuming isotropic mechanical properties in silicon, predicts in-plane and shear stress distributions very close to those of the full anisotropic model; however, there is a significant discrepancy in peeling stresses as discussed in the next section. Die/Solder Interfacial Shear Stress, τ s 300 250 200 150 100 50 0-50 Anisotropic FEM Modified Suhir's Equation -12-10 -8-6 -4-2 0 Figure 7. Comparison of Suhir and FEM predictions of device/solder interfacial shear stresses. 2) Peeling stress: The contribution to the normal or peeling stresses, r zz, from beam bending is given by Suhir s equation. The FEM results given in Figure 8 have been extrapolated to the silicon solder interface from gaussian points in elements at the bottom of the silicon FE mesh. In this case, the normal stress is dominated by an edge effect. The in-plane stress at the solder copper interface causes the silicon to curl down near its edge (Figure 9), producing a vertical displacement vs. position which is almost mirrored by the stresses. The vertical free edge, comprised of end surfaces of solder and silicon, is also bent slightly. This produces a small tensile r zz component along the surface of the free end, which is at its maximum at the silicon free end near its mid thickness in the vertical direction. As a result, the most compressive value of r zz occurs at the solder copper interface at the free edge. The peak r zz stress along the solder silicon interface occurs slightly inwards from the 301

Intl. Journal of Microcircuits and Electronic Packaging free edge, giving the curious decrease in the compressive magnitude seen at the free edge in Figure 8. Although the mesh of the FE model used was not sufficiently fine to give an accurate value for this edge stress, the isotropic FEM analysis does capture the nature of the peeling stress distribution. However, it underestimates the magnitude of maximum tensile and compressive normal stresses by 10 to 20%. Interface Peeling Stress, σ zz 50 0-50 -100-150 Isotropic FEM Anisotropic FEM Suhir's Equation -200-13 -12.5-12 -11.5-11 Figure 8. Peeling stresses at the silicon/solder interface near the free edge. silicon copper solder Figure 9. Deformed FED mesh near the edge with displacements magnified 40X. In the case of Suhir s formulas, the prediction of normal stresses is rather poor. There is no expectation of compressive normal stresses near the edge due to the fact that the free end boundary condition is not considered and the bend is assumed to be uniform throughout the silicon die. As a result, the maximum peeling stress is only 15% of that predicted by the FEM model. 3) Stress onset temperature T*: The determination of stress onset temperature, T*, is of crucial importance. It is required in order to estimate the stress/strain range imposed upon the solder layers during thermal cycling. Also, information about creep behavior of the solder alloys at high temperature can be obtained by studying the effects of cooling rate following solder reflow on T*. However, the evaluation of T* requires accurate analyses from both experiments and modeling. In Table 2, one can list values of T* predicted by different numerical and analytical models based on comparison with the Raman data for Si/Cu assemblies using different solder alloys. The FEM calculations were performed only on 80Au20Sn solder joint assemblies. The value of DT and T* for other solders are extrapolated based on the ratio of their peak die stresses over that of the Au-Sn eutectic. Both Suhir s formula and isotropic FEM predict a lower value of T* than anisotropic FEM. This is the major discrepancy introduced by assuming that silicon is elastic isotropic. In addition, note that the T* predicted by the full FEM analysis is 22 degrees higher than the melting temperature of the original eutectic gold-tin solder alloy. This is due to the fact that gold-plated copper has been used on silicon device as well as the substrate as solder pads, and they tend to form intermetallic compounds with tin in the solder during reflow. Furthermore, in-situ reflow observation reveals that the solder preform solidifies immediately after melting and remains solid until 330 C. Subsequent chemical composition analysis indicates a notable drop in tin content after this process. Similar results are known to occur if gold coatings dissolves into solder during reflow. As a result, the authors simply note that the thickness and composition of solder pads need to be carefully considered with respect to the physical and mechanical properties of the resultant solder joint. 3.3. Implications on Device and Solder Joint Reliability 1) Interfacial delamination and device fracture: As shown in previous sections, there is a significant driving force for crack growth initiating from interfacial defects near free edges or corners. Cracking processes from such effects in layered systems have been studied extensively in recent years. Also, it is now known 8 that cracks that initiate at such interfaces can either continue to propagate along the interface or deviate into the layer subject to compressive stresses provided its toughness is lower than that of the interface. However, the crack initiation process is rather complicated and depends on the defect distribution in the system. Although detail analyses based on fracture mechanics is beyond the scope of this paper, some general conclusions can be drawn based upon the current results. Since the interfacial shear and peeling stresses are proportional to the solder yield strength, cracks are more likely to grow in assemblies containing hard solders such as Au-Sn alloy than those using soft solders, for a comparably sized defect. Indeed, fractures around the die edge have been observed in some gold-tin solder die attaches. One example is shown in Figure 10, where a crack propagated spontane- 302

ously along the solder/silicon interface for a distance of approximately 1-2 die thicknesses. At this point, the crack left the interface to propagate within the silicon creating a conchoidal fracture surface around the device perimeter. This scenario is a clear indication that the adhesion between solder and silicon is very good and, furthermore, is tougher than the toughness of bulk silicon. Finally, one can note that if the silicon was substantially thicker, say 5 or 6 mm, then the crack path within the silicon would eventually rotate and become oriented parallel to the silicon/solder. Figure 10. Top view of a fractured Si/Cu die attach using eutectic gold-tin solder. Although large area solder joint assemblies using soft solder, such as eutectic Pb-Sn, are less likely to induce die fracture around device edges due to local stresses during cooling, they are prone to a different mode of failure. As demonstrated elsewhere 1, 7, there can be significant stress relaxation in a device, even at room temperature for some solder alloys, due to creep of the solder. This can lead to failure of the device during subsequent reheating, whereupon the entire device is placed under tension owing to the greater expansion of the base plate. Fracture of the die can occur before T* is reached. Indeed, a number of die fractures by this mode have been observed during thermal cycling following room temperature aging. One such example is shown in Figure 11. A 15 mm by 10 mm silicon/copper die attach using 97.5Pb/1.5Ag/1Sn solder was aged at room temperature for two weeks. The peak in-plane stresses fell 27%. Upon reheating, at 2 C/s, the die fractured abruptly at 170 C, 35 C below T*. Numerous cleavage cracks appeared, forming a grid pattern through the die center. A crude elastic interpolation gives an estimated peak stress in the die at 170 C of +39 MPa. This is well below the typical tensile strength of silicon die. The cracks could have initiated from cutting damage at the die edge, but the edge 4. Conclusion defect cracks would have needed to be bigger than 100 µm. A simple creep analysis predicts that stresses at and parallel to an edge will fall from the edge center to the die corner much faster than the stresses fall with location from the die center to the die edge. The observed In this paper, the researchers have presented the results from a crack/ die edge intersections lie within a zone along the edge for systematic study on the reliability of large area solder joint assemblies. Specifically, the spatial distributions of stress within silicon which the tensile stresses are barely within 50% of their maximum value. This helps explain why there is no cracking any closer to the devices bonded to substrates with a range of solder alloys have been die corners. But, it also probably means that the true value of the determined. These measurements are obtained directly by a novel peak edge stress is higher than estimated. Also, since small peak piezospectroscopic technique with unprecedented resolution. These stresses will develop, a device smaller than the critical die size H* is data are then related to the strains and corresponding constitutive less likely to fracture upon subsequent heating or power up. behavior of the solder layer. Results are then compared with the predictions of numerical and analytical analyses. Based on these Figure 11. Top view of a fractured Si/Cu die attach using 97.5Pb/1.5Ag/1Sn. 2) Solder joint fatigue life: The critical die size concept also has important effects on solder joint fatigue life. To illustrate this point, one can recall that the number of cycles to failure for a solder joint under thermal-mechanical cycling is believed to be inversely proportional to the plastic strain range experienced during the cycle through a power law as predicted by Coffin-Manson relation 9. For devices that are smaller than the critical die size, the solder joint lifetime is thus predicted to decrease with increasing die size. This fact is due to the increase in shear strain in the solder joint with increase in device dimension, but only until H* is reached. Further increases in die size beyond H* do not change the shear strain distribution in the solder layer since the solder layer is under zero shear strain within the constant stress region. Therefore, the plastic strain range induced by thermal-mechanical cycling remains invariant for device sizes greater than H*. As a result, one can predict that there is no reduction of fatigue lifetime of the joint upon further size increase beyond H*. Furthermore, the value of H* is in turn related to device thickness and solder shear strength. Therefore, one can expect that a relatively thick solder layer with high stiffness and high yield strength, in combination with thin die, will lead to a longer solder joint fatigue life. All testing articles used in current studies are under thermal cycling and preliminary results to support these conclusions. 303

Intl. Journal of Microcircuits and Electronic Packaging comparisons, a number of common assumptions in stress analyses and their applicability are addressed and related to the reliability of the solder joint, especially in terms of edge effects and interfacial peeling stresses. References 1. Jun He, M.C. Shaw, J. C. Mather, and R.C. Addison, Jr., Direct Measurement and Analysis of the Time-Dependent Evolution of Stress in Silicon Devices and Solder Interconnections in Power Assemblies, Proceedings of IEEE Industry Application Society Conference, San Louis, Missouri, October 12-15, pp.1038-1045, 1998. 2. S. P. Timoshenko, Analysis of Bi-Metal Thermostats, Journal of the Optical Society of America, Vol. 11, pp. 233-255, 1925. 3. M. S. Hess, The End Problem for a Laminated Elastic Strip- II. Differential Expansion Stresses, Journal of Composite Materials, Vol. 3, pp. 630-641, 1969. 4. D. Bogy, On the Problem of Edge-Bonded Elastic Quarter- Planes Loaded at the Boundary, International Journal of Solids and Structures, Vol. 6, pp. 1287-1313, 1970. 5. W. T. Chen and C. W. Nelson, Thermal Stress in Bonded Joints, IBM Journal of Research & Development, Vol. 23, pp.179-188, March 1979. 6. E. Suhir, Stresses in Adhesively Bonded Bi-material Assemblies used in Electronic Packaging, Proceedings of the Electronic Packaging Materials Science Symposium II, Palo Alto, California, April 15-18, pp.133-138, 1986. 7. Jun He, M. C. Shaw, N. Sridhar, B. N. Cox and D. R. Clarke, Direct Measurements of Thermal Stress Distributions in Large Die Bonds for Power Electronics, Proceedings of the Electronic Packaging Materials Science Symposium X, San Francisco, California, April 14-16, pp. 99-104, 1998. 8. J. W. Hutchinson and Z. Suo, Mixed Mode Cracking in Layered Materials, Advance in Applied Mechanics, Vol. 29, pp. 63-191, 1992. 9. S. S. Manson, Thermal Stress and Low Cycle Fatigue, McGraw-Hill Publishers, New York, 1966. About the authors Jun He is a Member of Technical Staff in the Design and Reliability Department at the Rockwell Science Center. He received his B. S. Degree in Physics (1991) and Ph.D. in Materials Science (1996) from the University of California, Santa Barbara. His primary research areas are in thermomechanical behavior as well as the reliability of electronic packages and composite materials. Since joined Rockwell in 1997, he has been working on advanced packaging, thermal management, and reliability aspects of power assemblies. Dr. He is the author or co-author of 9 technical papers. He is a member of IMAPS Society. Winfred L. Morris is a Member of Technical Staff in the Design and Reliability Department at the Rockwell Science Center. He earned his Ph. D. Degree in experimental physics from Northwestern University in 1968 and joined Rockwell in 1973. His expertise is in modeling the thermomechanical behavior of materials and structures. Lately, his research includes the development of advanced reliability modeling techniques in the electronics, power modules, and cooled IR-focal plane array areas. A good part of his work is currently directly on design support for new products. Dr. Morris has more than 100 publications and 3 patents. Dr. Shaw is the Manager of a Design and Reliability Department, Rockwell Science Center, Thousand Oaks, California. He received the Ph.D. Degree in Materials Engineering from the University of California, Santa Barbara, in 1993, an M.S. Degree in Ceramic Engineering from the Ohio State University in 1986, and a B.S. Degree in Materials Science and Engineering from the University of California, Berkeley in 1984. He first joined the Rockwell Science Center in 1988. His expertise lies in developing and experimentally validating structural models for the response of materials/architectures to applied stimuli, including statistical effects. He has 28 publications. Dr. Shaw is a member of the IMAPS Society. 304

John C. Mather is a Principal Engineer at Rockwell Collins Inc., in Cedar Rapids, Iowa. Mr. Mather holds Degrees in Mechanical Engineering and in Metallurgy. During the past twenty-plus years, he has made numerous innovative and technical contributions to Rockwell Collins and to the electronics industry in several areas, including printed wiring board construction and processing, electronics manufacturing technologies, and next-generation interconnect and packaging technologies. He received Rockwell s prestigious Engineer of the Year award in 1996, for distinguished contributions and outstanding leadership in developing advanced interconnect and packaging technology for electronic products. Mr. Mather holds several patents, and has published numerous technical papers on topics related to electronic packaging. Sridhar Narayanaswamy is a Member of the Technical Staff in the Materials Science Division since July 1997. He obtained his B. Tech. Degree (Metallurgy, 1991) from India, M.S.(Materials Science, 1993), M.S. (Mechanical Engineering, 1995) and Ph.D. (Materials Science, 1996) Degrees, all from the University of Michigan, Ann Arbor. His primary research areas are in the mechanics of structural materials, fracture mechanics, composite design and reliability, and computational materials science. He has authored or co-authored around 15 research publications. 305