Thermo-Mechanical Reliability Assessment of TSV Die Stacks by Finite Element Analysis Dr. Roland Irsigler, emens AG Corporate Technology, CT T P HTC
Outline TSV SOLID µbump Stacking TSV application FEA modeling appoaches Material parameter set TSV FE/BE build-up process Impact of TSV geometry on internal die level stress Regions of critical loading Packaging related stress on TSVs Options to lower the risks Summary Packaging Page 2
TSV Application: DRAM TSV-Package TSV-Interconnect Chip (UP-TV) TSV s DRAM wafer TSV-Testvehicle Power Pad gnal Pad 8,0 mm Dummy Pad Via Ø 5-10 µm 12,4 mm SOLID Interconnect TSV stack (4-fold) Benefits: Challenges: memory/volume low parasitics new technology new equipment cost, yield reliability Page 3
FEA modeling approaches IZM Fraunhofer Institut Zuverlässigkeit und Mikrointegration 2D via model 3D via model Global/Submodel approach Al Ti/ W O2 Coupled z DOFs Coupled x DOFs O2 Polymer W Ti/ Symmetric BC Symmetric BC rotatio symmetry periodic bounderies variation in: - via diameter & pitch - layer thickness - material set Page 4 full 3D model variation in: - via shape, dimensions - via arrays - pad geometry fixed material set include build-up process flow 3D model of complete TSV-package boundary conditions for TSV submodel are determined by the global model variation in: - # of dies/stack - package construction
Material Regions and Dimensions 3D FE quarter -Via model with circular via cross section Coupled z DOFs* Pad of next die top region -pad Al-pad 30 µm Dielectric layer opening 17 µm 15 µm Via Ø 10 µm Sn, 2 µm, 50 µm, 4 µm O 2, 1,5 µm bottom region, 4 µm Pad of next die Polymer, here 1 µm Ti/, 50/150 nm Al, 850 nm, Ø10 µm O 2, 100 nm *Coupled degrees of freedom of the nodes at the outside area Page 5
3D Global Stacked Die Model and Submodelling Submodel: single via Global model: 8 fold stack in package global-local matching Interconnect side view Top die Bottom -pad IMC 3 Sn mplified die global model Bottom die Top -pad Via region At the so-called cut boundaries the displacements, which were calculated in the global model, are extrapolated on the finer mesh of the submodel. Package warpage Page 6
Material Parameter Set Micro Materials Center Berlin and Chemnitz Head: Prof. B. Michel Material Constitutive law (Instantaneous-) E-Modulus [MPa] Poissons ratio CTE [1/K] Initial yield stress [MPa] Source Chip Elastic 168,000 0.30 2.8 10-6 Normally used for <100> O 2 - Passivation x N 4 - Passivation Elastic 72,000 0.20 1.7 10-6 Normally used in semiconductor fabrication Elastic 160000 0.20 2.1 10-6 Normally used in semiconductor fabrication Al-Pad Elastic-plastic 70,000 at 233 K 50,000 at 523 K W-via Elastic-plastic 210,000 at 233 K -via/pad Elastic-plastic 180,000 at 523 K 103,000 at 233 K 83,000 at 673 K Ti/ Elastic-plastic 110,000 at 233 K 90,000 at 523 K 0.32 24 10-6 σ 0 : 210;E tan : 4000 at 233K σ 0 : 180;E tan : 5000 at 523K 0.32 4.5 10-6 σ0: 3100;Etan: 6900 at 233K σ 0 : 2810;E tan : 6900 at 523K 0.35 17 10-6 σ 0 : 410;E tan : 1090 at 233K σ 0: 350;E tan: 1090 at 553K 0.31 15 10-6 σ 0 : 540;E tan : 16000 at 233K σ 0 : 450;E tan : 7353 at 523K CINDAS (after Nanoindentation and simulation) (after Nanoindentation and simulation updated) CINDAS WPR Backside Polymer Viscoelastic, T g =100 C 4,200 at 218 K 2,800 at 423 K 0.3 0.32 45 10-6 < 373K 85 10-6 > 373K Shear:a1: 0.0351; a 2 : 0.0659 at t 1 : 45.68; t 2 : 914.64 Measured in previous project IMC 3 Sn Elastic-plastic 115,000 0.32 19 10-6 σ 0 : 400 Applied in previous projects *Microelectronics Packaging Materials Database developed at Purdue University, Center for Numerical Data Analysis and Synthesis (CINDAS) under the Sponsorship of Semiconductor Research Corporation (SRC), Version 2.32, 1999 Thin film material parameter can differ significantly from bulk material parameter They can also depend on the deposition process and the source chemistry Measurements on dedicated testsamples required Page 7
Initial condition Process temperature [ C] 450 400 350 300 250 200 150 100 50 0 TSV build-up process Elastic-plastic conditions Al-layer deposition Process Flow I deposition hard passivation upside 0 5 10 15 20 25 Process Time [s] step Adjusting deposition T Wafer/die level Visco-elastic conditions Heating up to polymer deposition Process temperature [ C] 300 250 200 150 100 50 Polymer deposition Ti/ deposition upside and backside Process Flow II Resist deposition 0 20 1020 2020 3020 4020 5020 Polymer etch plating upside and backside Resist strip Ti/ etch Time [s] Process Flow III 0 20 1020 2020 3020 4020 502 The process steps up to the starting point (initial condition) can be neglected in the FE analysis because only elastic strains occur Process steps with elastic-plastic conditions were realized as loading steps with fictive time scale. Layer is stress free at deposition temperature. Non-thermal intrinsic stress (e.g. chemical shrink) were not considered. The first time step with real process time becomes effective after the deposition of the viscoelastic polymer at the wafer bottom due to its time dependent properties. Process temperature [ C] 300 250 200 150 100 50 Package level Packaging Heating up to 270 C and adding 3 Sn solder Reflow soldering and cooling Molding - cooling to RT Ti/ etch Time [s] Page 8
ngle step vs. TSV build-up process results 1 after one equivalent cooling step Equivalent plastic strain after an intermediate step of the processing sequence Al active elements TSV / Pad interface edge Deactivated (dead) elements Al W O 2 Max. 1.9 % Max. 3.9 % W O 2 effects of the process steps have to be modeled adequately differences in stress and strain distribution patterns as well as in their amplitudes are obvious single-step approach even fails qualitatively. Page 9
Schematic representation of results and tendencies Results after process flow 2 Ø 15 µm Ø 2,5 µm <1 µm 10 µm Page 10
Results from 2D and 3D Modeling Maximum stress values in and 10x40 via 10x20 via 10x10 via 13 via array 5x1 via array circ.tsv arrays ngle rect. TSV s Page 11
Regions of critical loading 2D Model Al-pad Top region O 2 W S eqv [MPa] Bottom region Top region, Al Pad Al-pad W O 2 3D Model Al-pad pad O 2 Polym. Al-pad Ε pl,eqv pad Regions of stress concentrations (Indicator: v.mises stress and equiv. plastic strain) in the via structure independent of the via shape, dimension, and the level of modeling Page 12
FE modeling procedure to include process flow 3 ( packaging ) Create submodel (TSV) Calculation Sequential building of the TSV structure up to molding temperature 180 C Deposition temperature is stress free (reference) temperature Delete boundary conditions set for build-up Save submodel Write cut boundary nodes Create global model (package) Calculation Molding 180 C to RT Execute cut boundary interpolation for molding step Set cut boundary DOF specifications for molding-step Calculation Molding 180 C to RT Page 13
Via loading depending on the number of -chips in the stack Z displacements [µm] of the global model Page 14
Results after process flow 3 ( packaging ) Top region Bottom region The via is located at the edge of a 4fold stack in package in the 2nd die from bottom of. -Pad pad O 2 ε pl,eqv Max. stress moved to outer edge of pad Polym. WPR-Pad Factor 6 higher than die level stress! Displacement scaling: 3x tilt and shear! 1% higher New quality and quantity of stress loading for the via structure after the inclusion of soldering and molding in the sequence of the build-up process Page 15
Results after process flow 3 ( packaging ) -via filling Top region S z [MPa] ε pleqv Bottom region Plastic straining is induced at the via bottom region, which accumulates during thermal cycling fatigue risk Page 16
Impact of bottom isolation layer material substitution Temperature Cycle: 125 C -55 C van-mises Stress [MPa] 2500 2000 1500 1000 500 O2 Stress in Via Passivation Plastic Strain in the Via Initial Design PI 1.2 1.0 0.8 0.6 0.4 0.2 Plastic Strain per Thermal Cylce [%] 0 72 36 18 3.6 3.1 Young's Modulus of Bottom Insulator Film [GPa] 0.0 A more rigid bottom isolation layer can lower stresses and strains in the TSV bottom region Page 17
Impact of underfiller between dies Package without underfilling S eqv [MPa] Package with underfilling S eqv [MPa] S z [MPa] S eqv [MPa] S z [MPa] S eqv [MPa] Page 18
Summary General: TSV process temperature sequence has to be modeled adequately to identify critical regions and stress levels. Thin film material parameter needs to be determined properly measurements Die level: No clear failure risk for all simulated variants of via shapes found. Circuar vias and via arrays show less stress in than single, rectanular vias Local stress concentrations are /O2/Al at the top region and /O2/Polymer at the bottom region. Package level: No clear failure risk at via top region identified Clear failure risk on via bottom region due to the low stiffness of the polymer layer. Use of rigid bottom isolation layer or underfill significantly reduces stress at the via Page 19
Contact Dr. Roland Irsigler emens AG, CT T P HTC, Erlangen E-mail: roland.irsigler@siemens.com Dr. Rainer Dudek Fraunhofer ENAS, Micro Materials Center Berlin and Chemnitz E-mail: rainer.dudek@enas.fraunhofer.de Dr. Sven Rzepka Fraunhofer ENAS, Micro Materials Center Berlin and Chemnitz E-mail: Sven.Rzepka@ENAS.Fraunhofer.de Thermo-Mechanical Reliability Assessment for 3D Through- Stacking, R. Dudek et al. EuromE 2009, Delft, April 2009 Virtual Prototyping in Microelectronics and Packaging, S. Rzepka et al., 33th International Conference and Exhibition IMAPS Poland 2009, 21-24 September 2009 Page 20