SITV s Stack-ups and Loss. Add a subtitle

Similar documents
PEC (Printed Electronic Circuit) process for LED interconnection

IS410 Processing Guide

Astra MT77 Processing Guide

Stack-up and routing optimization by understanding micro-scale PCB effects

High Frequency Circuit Materials Attributes John Coonrod, Rogers Corporation

Flex and Rigid-Flex Printed Circuit Design

Introduction Conductors. Supply Planes. Dielectric. Vias PCB Manufacturing Process Electronic Assembly Manufacturing Process

Low CTE / High Tg FR-4 with High Heat Resistance

Advances in Intense Pulsed Light Solutions For Display Manufacturing. XENON Corporation Dr. Saad Ahmed Japan IDW 2016

GRAPHIC MANUFACTURING CAPABILITY Q217-18

PCB Production Process HOW TO PRODUCE A PRINTED CIRCUIT BOARD

LOW TEMPERATURE PHOTONIC SINTERING FOR PRINTED ELECTRONICS. Dr. Saad Ahmed XENON Corporation November 19, 2015

RF-43. General Processing Guidelines

UL PCB Recognition what is it & why do you need to know about it

How to select PCB materials for highfrequency

NiP Resistor Manufacturing Overview

Thermal Reliability of Laser Ablated Microvias and Standard Through-Hole Technologies as a Function of Materials and Processing

Additive Circuit Technology Roadmap for HDD Suspension

High Tg Bromine-free Laminates for PWB Applications

Pad Crater Project Definition Stage. Joe Smetana Alcatel-Lucent For Member Meeting 2/9/2011 San Jose, CA

Lead Free Assembly: A Practical Tool For Laminate Materials Selection

Characterizing the Lead-Free Impact on PCB Pad Craters

Measuring Copper Surface Roughness for High Speed Applications

3D Packaging- Synthetic Quartz Substrate and Interposers for High Frequency Applications. Vern Stygar #1, Tim Mobley* 2 # Asahi Glass Corporation

MCPCB Material (Heat sync)

MICROWAVE & RF MATERIALS GUIDE

New Technology to Improve Etching Performance Using Shiny Side Surface Treatment for HDI

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

Scotch-Weld TM. Epoxy Adhesive/Coating Technical Data July, 2011

2015 IEEE. REPRINTED, WITH PERMISSION, FROM Next Generation Metallization Technique for IC Package Application

BASE MATERIALS Through Assembly

NCAB Group PCB Specification

DIELECTRICS FOR EMBEDDING ACTIVE AND PASSIVE COMPONENTS

Gage Series Stress Analysis Gages

Cycom Modified Cyanate Prepreg System

IMPACT OF MICROVIA-IN-PAD DESIGN ON VOID FORMATION

Embedding Passive and Active Components: PCB Design and Fabrication Process Variations

ROLINX Laminated Busbar. Design Rules Version 01 (12/2015)

c/bach, 2-B Pol. Ind Foinvasa Montcada i Reixac (Barcelona) SPAIN Tel FAX

Via Life vs. Temperature Stress Analysis of Interconnect Stress Test

Novel Materials and Activities for Next Generation Package. Hitachi Chemical., Co.Ltd. Packaging Solution Center Hiroaki Miyajima

Fysisk institutt, Universitetet i Oslo Lille Fysiske Auditorium 10. and 17. Mars John Steinar Johnsen Senior Application Engineer PCB

ThunderClad 2. TU-883 HF Very Low Loss Material. Laminates & Prepregs Mass Lamination Service Insulated Metal Substrate Materials

COFAN USA. Meeting your Project needs.

inemi BFR-Free Free PCB Material Evaluation Project Chair : Stephen Tisdale Intel Corporation SMTAi Presentation August 21, 2008

Cu Wiring Process for TFTs - Improved Hydrogen Plasma Resistance with a New Cu Alloy -

3M Electromagnetic Compatible Products

Lecture Day 2 Deposition

RF System in Packages using Integrated Passive Devices

PRODUCT DATA SHEET TYPICAL NEAT RESIN PROPERTIES. Dielectric Constant at 10 Ghz on 4581 quartz Loss Tangent at 10 Ghz on 4581 quartz...0.

MATERIALS. September Construction Profiles and Material Decomposition p.18. Improved Thin-Film Resistor Material p.24

Advanced Technology Option. Users Guide

Step-By-Step Product Selection Guide

Heritage Quality Performance

Woven Electrodes for Optoelectronic Devices. Peter Chabrecek. Sefar AG, 9425 Thal, Switzerland

Newsletter. Test Services & Failure Analysis Laboratory. April The Reality of Flip-Chip Solder Bump Electromigration Failure INSIDE THIS ISSUE

DuPont Kapton HN POLYIMIDE FILM

The Compensation Problem and Solution Using Design of Experiments for Dense Multilayer Printed Circuit Boards

DuPont Kapton FPC POLYIMIDE FILM

DEVELOPMENT OF HIGH EFFICIENCY FLEXIBLE CdTe SOLAR CELLS

Convolute Rolled Tube Products Phenolic Resins, Paper Substrates. Phenolic Resins Paper Substrates

20 W Power Resistor, Thick Film Technology, TO-220

SilGrip* PSA595 Pressure Sensitive Adhesive

Substrate Materials. Aliza Mizrachi

TECHNICAL DATA NEAT RESIN MECHANICAL PROPERTIES

Label Tape FAQs and Technical Information Pertaining to Brother Label Printers PT-9700PC and PT-9800PCN

Innovative MID Plating Solutions

Conductive Anodic Filament Growth Failure

Military Specifications

Simulation of Embedded Components in PCB Environment and Verification of Board Reliability

Military Specifications

FILM ADHESIVES NOMINAL CURE TEMP F (C ) / TIME. 250 (121) / 60 min Cream. 250 (121) / 60 min Cream. 250 (121) / 60 min Cream. 260 (126) / 20 min Cream

Optimizing the Insulated Metal Substrate Application with Proper Material Selection and Circuit Fabrication

Ricerca e Sviluppo Produzione resine Servizio clienti Servizio tecnico

SilGrip* PSA518 Pressure Sensitive Adhesive

Qualification and Performance Specification for Flexible Printed Boards

DATA SHEET A5000 RELEASE FILM

Topics. Glazing Materials. Glass. Hail damage. Light transmittance through glazing material. Glass Rigid panels Film plastic.

TOP 5 REASONS TO USE FILM-CAST PTFE LINER TUBING FOR YOUR NEXT CATHETER DESIGN

Avery Dennison L-3050 & LP-0500 Series Retroreflective License Plate Film Integrated Digital Printing Issued: July 2013

ELECTROMAGNETIC NOISE SUPPRESSION SHEETS

Photonic Drying Pulsed Light as a low Temperature Sintering Process

Adhesion in Extrusion Coating & Laminating - the Importance of Machine Variables. Bruce Foster Mica Corporation

Dicing Glass Optical Devices

DuPont ETFE Coatings High-Build Topcoat Powder Powder Primer and 699N-129 Liquid Primer

Process & Capability Manual (Vol )

Rockwell R RF to IF Down Converter

Overview of CMP for TSV Applications. Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA

Nano- And Micro-Filled Conducting Adhesives For Z-axis Interconnects

IPC-TM-650 TEST METHODS MANUAL

CYCOM 7668 EPOXY RESIN

Chips Face-up Panelization Approach For Fan-out Packaging

Contact plating material options for electronic connectors A comparison of hard gold and hard gold flashed palladium-nickel (80/20)

IBM Laminate Study Group

Multilayer Polyethylene Films For Food Service Packaging Applications FlexPackCon 2017

PCB Technologies for LED Applications Application note

* Corresponding Keywords: Cu thin foil, Thermal conditions, Etching factor, Pattern shape, Microstructures

Transcription:

SITV s Stack-ups and Loss Add a subtitle

SITV Stack-ups General Signal Integrity TV s are often used to characterize material performance There are a variety of TV s that use differing approaches and measurement methods Many users now are trying to specify the resin content (RC) range and match both sides of a stripline This issue is the main point of this presentation

Loss Characterization Generally, the following is accepted Wide traces are better Core is more consistent and foil roughness towards the core is known side is difficult to fully control Cure may vary, resin content varies, oxide surface may vary Thin prepreg openings compared to core thickness do not perform as well as balanced or core thinner constructions

Balancing Resin Content The main misunderstanding on SITV s is this: The core RC is tightly controlled and does not change once core is built The prepreg resin has to flow into the space around the etched transmission lines This reduces the resin content of the prepreg above the transmission line Many SITV s are specified with starting RC values, not finishing RC values. Starting with prepreg and cores having the same RC value and same glass style will not result in the intended result

Example Target 70-75% Resin Before Lamination Thickness After Lamination 30 um (1.2 mils 135 um 110 um 5.4 mils 4.2 mils 2x1067 66% Resin Signal 30 um (1.2 mils Signal Core Core 135 um 5.4 mils 30 um (1.2 mils 100% Resin During lamination, the prepreg melts and flows into the areas around copper etched feature. In most SITV s the copper area is very small, so the resin requirement to fill this space is about 90-95% of copper thickness. This outflow of resin lowers the resin content of the prepreg layer, above the copper layer. The effective resin content in this case, is 66%, not 72%. In example above the resin content is reduced about 6% This results in higher dielectric constant, may change dielectric loss, creates high current density on the prepreg side of the etched circuit which usually gives higher loss values, and does not meet the 70% resin content requirement.

Making a Balanced TV To make a balanced TV, you need a higher starting resin content on the prepreg layer In some cases, a different glass style on the prepreg layer may be needed to correctly match The basic rules are: If same glass style, the prepreg RC value needs to be chosen to result in the same thickness as the core. If a different glass style is chosen, it needs to result in a prepreg thickness equal to or thicker than the core layer

Example Target 70-75% Resin Alternate Before Lamination Thickness After Lamination 2x1067 76% Resin 30 um (1.2 mils) 165 um 135 um 6.5 mils 5.4 mils Signal 30 um (1.2 mils) Signal Core Core 135 um 5.4 mils 30 um (1.2 mils) 100% Resin In this approach, the initial prepreg resin content is high, above the target, but after the resin loss into the circuit area, the structure is nearly balanced. Note-This is an example, the 76% prepreg may not be feasible to make. This also helps to show how high resin content structures can be hard to make balanced.

Feasibility Resin Content In some cases, particularly when high RC values are requested, it may not be feasible for a material system to create the needed prepreg There is a maximum amount of resin that can be coated onto glass layers. Beyond this amount the product is inconsistent and impractical to produce. Different glass styles can accept differing maximum RC values. Allowing glass style substitution can help in these cases Most PCB fabricators have good thickness calculators. They may not have good RC calculators So specifying thickness helps if same glass style is being used

Summary To obtain consistent and accurate SI material properties, the TV stack-up designs should: Clearly state that the Resin Content % is after lamination This provides a more symmetrical stripline Alternately, specify the prepreg thickness to be the same as the core Allow mixed glass styles It may not be feasible to match glass styles in the core and the prepreg. If you have specific restrictions on some glass styles, this should be communicated. layers should be maintained at core thickness DSTF, DSRFoil, DSRFoil, GETEK, I-Fill, I-Speed, I-Tera, IsoDesign, Isola, IsoStack, Norplex, Polyclad, RCC, Lo-Flo and TURBO are registered trademarks of Isola USA Corp. in the U.S.A. and other countries. The Isola logo is a trademark of Isola USA Corp. in the U.S.A. and other countries. All other trademarks mentioned herein are property of their respective companies. Copyright 2013 Isola Group, S.à.r.l. All rights reserved.