Effect of nanoimprinted surface relief on Si and Ge nucleation and ordering

Similar documents
Figure 2.3 (cont., p. 60) (e) Block diagram of Pentium 4 processor with 42 million transistors (2000). [Courtesy Intel Corporation.

Isolation Technology. Dr. Lynn Fuller

Morphology of Thin Aluminum Film Grown by DC Magnetron Sputtering onto SiO 2 on Si(100) Substrate

Alternative Methods of Yttria Deposition For Semiconductor Applications. Rajan Bamola Paul Robinson

Fabrication of Ru/Bi 4-x La x Ti 3 O 12 /Ru Ferroelectric Capacitor Structure Using a Ru Film Deposited by Metalorganic Chemical Vapor Deposition

Invited paper. Issues on nanoimprint lithography with a single-layer resist structure. Applied Physics A Materials Science & Processing

Isolation of elements

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

Lecture 19 Microfabrication 4/1/03 Prof. Andy Neureuther

In-Situ Monitoring of Pattern Filling in Nano-Imprint Lithography Using Surface Plasmon Resonance

Heavily Aluminum-Doped Epitaxial Layers for Ohmic Contact Formation to p-type 4H-SiC Produced by Low-Temperature Homoepitaxial Growth

Semiconductor Manufacturing Technology. IC Fabrication Process Overview

Mater. Res. Soc. Symp. Proc. Vol Materials Research Society

Rapid Thermal Processing (RTP) Dr. Lynn Fuller

Introduction to Micro/Nano Fabrication Techniques. Date: 2015/05/22 Dr. Yi-Chung Tung. Fabrication of Nanomaterials

Anomaly of Film Porosity Dependence on Deposition Rate

One-kilobit cross-bar molecular memory circuits at 30-nm half-pitch fabricated by nanoimprint lithography

Lecture Day 2 Deposition

HOMEWORK 4 and 5. March 15, Homework is due on Monday March 30, 2009 in Class. Answer the following questions from the Course Textbook:

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS

Fabrication Technology

Section 4: Thermal Oxidation. Jaeger Chapter 3. EE143 - Ali Javey

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Process Flow in Cross Sections

Fabrication of CdTe thin films by close space sublimation

Activation Behavior of Boron and Phosphorus Atoms Implanted in Polycrystalline Silicon Films by Heat Treatment at 250 C

MARORA A Plasma Selective-oxidation Apparatus for Metal-gate Devices

ME 141B: The MEMS Class Introduction to MEMS and MEMS Design. Sumita Pennathur UCSB

Radiation Tolerant Isolation Technology

and Technology of Thin Films

CMOS FABRICATION. n WELL PROCESS

Technology. Semiconductor Manufacturing. Hong Xiao INTRODUCTION TO SECOND EDITION SPIE PRESS

Vertical Group IV Nanowires: Potential Enablers for 3D Integration and BioFET Sensor Arrays

Supporting Information

Vertically aligned Ni magnetic nanowires fabricated by diblock-copolymer-directed Al thin film anodization

Micro-Electro-Mechanical Systems (MEMS) Fabrication. Special Process Modules for MEMS. Principle of Sensing and Actuation

VLSI Technology Dr. Nandita Dasgupta Department of Electrical Engineering Indian Institute of Technology, Madras

Dr. Priyabrat Dash Office: BM-406, Mob: Webpage: MB: 205

PARAMETER EFFECTS FOR THE GROWTH OF THIN POROUS ANODIC ALUMINUM OXIDES

Materials Characterization

Boron Diffusion and Silicon Self-Interstitial Recycling between SiGeC layers

Atomic Layer Deposition(ALD)

Measurement of thickness of native silicon dioxide with a scanning electron microscope

Silicon Wafer Processing PAKAGING AND TEST

LANDOLT-BÖRNSTEIN. Zahlenwerte und Funktionen aus Naturwissenschaften und Technik. Neue Serie. Gesamtherausgabe: K.-H. Hellwege O.

COMPATIBILITY OF THE ALTERNATIVE SEED LAYER (ASL) PROCESS WITH MONO- Si AND POLY-Si SUBSTRATES PATTERNED BY LASER OR WET ETCHING

5.8 Diaphragm Uniaxial Optical Accelerometer

Surface Analysis of Electrochromic Switchable Mirror Glass Based on Magnesium-Nickel Thin Film in Accelerated Degradation Test

Oxide Growth. 1. Introduction

X-ray Photoelectron Spectroscopy

VLSI Systems and Computer Architecture Lab

Chapter 5 Epitaxial Growth of Si 1-y C y Alloys

Fabrication Techniques for Thin-Film Silicon Layer Transfer

Modeling of Local Oxidation Processes

Fabrication of sawtooth diffraction gratings using nanoimprint lithography

1. Introduction. What is implantation? Advantages

Chapter 2. Density 2.65 g/cm 3 Melting point Young s modulus Tensile strength Thermal conductivity Dielectric constant 3.

Development of different copper seed layers with respect to the copper electroplating process

Ajay Kumar Gautam [VLSI TECHNOLOGY] VLSI Technology for 3RD Year ECE/EEE Uttarakhand Technical University

Fabrication of a Crossbar Structure at 50 nm Half-pitch by UV-based Nanoimprint Lithography

Amorphous Silicon Solar Cells

VLSI Technology. By: Ajay Kumar Gautam

In-Situ Low-Angle Cross Sectioning: Bevel Slope Flattening due to Self-Alignment Effects

Step and Flash Imprint Lithography for sub-100nm Patterning

Growth of SiC thin films on graphite for oxidation-protective coating

Application of ultra-thin aluminum oxide etch mask made by atomic layer deposition technique

ALD and CVD of Copper-Based Metallization for. Microelectronic Fabrication. Department of Chemistry and Chemical Biology

Overview of CMP for TSV Applications. Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA

DEPOSITION OF Al 2 O 3 ON CERAMIC SUBSTRATES BY PECVD METHOD. Lucie Špirková a Vlastimil Brožek a Jean Durand b

Lab #2 Wafer Cleaning (RCA cleaning)

Lecture 12. Physical Vapor Deposition: Evaporation and Sputtering Reading: Chapter 12. ECE Dr. Alan Doolittle

Citation JOURNAL OF APPLIED PHYSICS (1995),

Surface Acoustic Wave fabrication using nanoimprint. Zachary J. Davis, Senior Consultant,

High Dose Hydrogen Implant Blistering Effects As a Function of Selected Implanter And Substrate Conditions

Nanoimprinting in Polymers and Applications in Cell Studies. Albert F. YEE Chemical Engineering & Materials Science UC Irvine

Lecture 8. Deposition of dielectrics and metal gate stacks (CVD, ALD)

A Novel Method for Low-Resistivity Metal-Interconnection by Using Metallic Functional Liquids and Catalytically Generated Hydrogen Atoms.

Thermal Evaporation. Theory

Poly-SiGe MEMS actuators for adaptive optics

CSI G SYSTEMS CSI GAS DELIVERY SUPPORT. Chemical Vapor Deposition (CVD)

Plasma-Enhanced Chemical Vapor Deposition

3.155J / 6.152J Micro/Nano Processing Technology TAKE-HOME QUIZ FALL TERM 2005

QUARTERLY TECHNICAL REPORT

Fabrication and Layout

Ultra High Barrier Coatings by PECVD

EFFECT OF GROWTH TEMPERATURE ON THE CATALYST-FREE GROWTH OF LONG SILICON NANOWIRES USING RADIO FREQUENCY MAGNETRON SPUTTERING

KGC SCIENTIFIC Making of a Chip

Project III. 4: THIN FILM DEVICES FOR LARGE AREA ELECTRONICS

ION-IMPLANTED PHOTORESIST STRIPPING USING SUPERCRITICAL CARBON DIOXIDE

Section 4: Thermal Oxidation. Jaeger Chapter 3

Regents of the University of California

Surface micromachining and Process flow part 1

An XPS and Atomic Force Microscopy Study of the Micro-Wetting Behavior of Water on Pure Chromium* 1

High Temperature Oxygen Out-Diffusion from the Interfacial SiOx Bond Layer in Direct Silicon Bonded (DSB) Substrates

ENS 06 Paris, France, December 2006

Imprint lithography for curved cross-sectional structure using replicated Ni mold

Microstructure and Vacuum Leak Characteristics of SiC coating Layer by Three Different Deposition Methods

Corrosion Protect DLC Coating on Steel and Hastelloy

Thermal Annealing Effects on the Thermoelectric and Optical Properties of SiO 2 /SiO 2 +Au Multilayer Thin Films

Excimer Laser Annealing of Hydrogen Modulation Doped a-si Film

Transcription:

Microelectronics Journal 37 (2006) 1481 1485 www.elsevier.com/locate/mejo Effect of nanoimprinted surface relief on Si and Ge nucleation and ordering T.I. Kamins a,, A.A. Yasseri a,1, S. Sharma a,2, R.F.W. Pease b, Q. Xia c, S.Y. Chou c a Quantum Science Research, Hewlett-Packard Laboratories, Palo Alto, CA 94304-1100, USA b Department of Electrical Engineering, Stanford University, Stanford, CA 94305, USA c NanoStructure Laboratory, Department of Electrical Engineering, Princeton University, Princeton, NJ, 08544 USA Available online 5 July 2006 Abstract Surface relief formed by nanoimprinting and etching into a thermally grown SiO 2 layer on Si was used to position the initial nuclei formed by chemically vapor deposited Si and Ge. By controlling the deposition conditions, the surface diffusion length was adjusted to be comparable to or larger than the spacing between features, thus favoring nucleation adjacent to steps, rather than random nucleation. Random nucleation was further suppressed by a two-stage deposition process. Ge nucleation on oxide by chemical vapor deposition was enhanced by coating the oxide surface with an organic self-assembled monolayer (SAM) and by the nanoimprinted surface relief. The nanoimprinted surface relief also provides long-range order in the SAM. r 2006 Elsevier Ltd. All rights reserved. Keywords: Epitaxy; Graphoepitaxy; Self-assembled monolayers; Nucleation 1. Introduction Corresponding author. Tel.: +1 650 857 1501; fax: +1 650 236 9885. E-mail address: kamins@hp.com (T.I. Kamins). 1 Now at Lam Research, Fremont, CA, USA. 2 Now at Spansion, Inc., Sunnyvale, CA, USA. Forming single-crystal semiconductors on amorphous insulating layers has been an elusive goal of integratedcircuit technology for at least three decades. Early radiation-hardened integrated circuits used deposition of thick polycrystalline silicon (polysilicon) layers on an oxidized silicon wafer, followed by grinding and polishing of the single-crystal substrate, to achieve a thin singlecrystal Si layer on an insulator. The process was expensive, and control of the polycrystalline-silicon deposition was difficult. Wafer warpage during polysilicon deposition made alignment difficult and decreased yield. Bonding of a handle wafer to an oxidized Si wafer avoids the need to deposit a thick layer of polysilicon. Implantation of high doses of oxygen into a single-crystal silicon wafer, followed by extremely high-temperature annealing, also allows forming the desired silicon/oxide/silicon structure, but is expensive. Both techniques allow formation of a single-crystal Si layer on an insulated substrate. The latter is limited to one layer, while the former can be extended to multiple layers of Si. The possibility of directly depositing a single-crystal semiconductor layer on an insulated Si substrate remains attractive, however, to avoid the mechanical complexity of wafer thinning techniques and the extreme temperatures associated with annealing after oxygen implantation. The ability to form multiple layers of devices on a silicon wafer is especially attractive. Early investigation of Si deposition on insulating layers with surface topography produced intriguing results, but the technique, labeled as graphoepitaxy, [1 3] was not pursued aggressively. One difficulty was the large lateral size of patterned surface relief that could be formed at the time that the technique was being investigated. If the diffusion length of the depositing species is small compared to the spacing between features, the surface relief cannot significantly influence the deposited material, and random nucleation between features produces a disordered layer. For a given materials system, the diffusion length is controlled by the temperature and arrival rate of the 0026-2692/$ - see front matter r 2006 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2006.05.023

1482 ARTICLE IN PRESS T.I. Kamins et al. / Microelectronics Journal 37 (2006) 1481 1485 depositing atoms. At higher temperatures, the adsorbed atoms can diffuse farther in a given time to find favorable sites at the patterned features for nucleation. At lower adatom arrival rates, the adatoms can diffuse for a longer period of time before encountering other adsorbed atoms and forming random nuclei on the surface. Therefore, the diffusion length L D relevant to this discussion depends on temperature and arrival rate. A useful functional expression to help visualize the behavior follows: L D ¼ðD t Þ 1=2 ¼ D 1=2 0 expð E as =2kTÞ=R 1=2, where D is the surface diffusion coefficient, which depends on a slowly varying pre-exponential factor D 0 and a rapidly varying exponential factor containing the surface diffusion energy E as and the temperature T, and t is a characteristic time associated with the arrival rate R of adatoms. For CVD, the effective arrival rate can be limited by either transport of the gaseous precursors to the surface or by the reaction rate at the surface. In this study, we attempted to extend the concept of graphoepitaxy to the finer patterns that can be formed by advanced patterning techniques such as nanoimprint lithography (NIL). By depositing Si and Ge under conditions where the diffusion length is comparable to or larger than the feature spacing formed by NIL, we attempted to obtain nucleation adjacent to the features while minimizing random nucleation between features. Si nucleates well on SiO 2, but nucleation of Ge by CVD is difficult; we attempted to enhance the nucleation of Ge by using an organic, self-assembled monolayer (SAM) on the patterned SiO 2. This paper contains a preliminary report of the work. 2. Experimental techniques Surface relief was formed in thermally grown SiO 2 by NIL [4]. After oxidation to form an SiO 2 layer approximately 200 nm thick, a 180 nm thick thermoplastic imprint resist was applied and baked at 70 1C for 15 min. The pattern was then imprinted into the resist using 4-in Si molds with gratings over the entire mold area using an NX- 2000 imprint machine. The Air Cushion Press (ACP TM )in the NX-2000 ensures uniformity over the entire 4-in wafer. After removing the residual resist layer in the regions to be etched, the pattern was transferred into the oxide by reactive ion etching using a CHF 3 /O 2 gas mixture. Details of the NIL procedure have been previously described elsewhere [4]. After patterning, the substrates were cleaned in NH 4 OH/H 2 O 2 /H 2 O (1:1:5, heated to 80 1C for 15 min), rinsed and dried. Fig. 1 shows atomic-force micrographs of the array of raised regions and recessed trenches after etching. The recessed regions were typically 115 or 155 nm wide with a pitch of 190 nm ( narrow and wide trenches, respectively), allowing investigation of the effect of the ratio of Fig. 1. Atomic-force micrographs of nanoimprinted patterns with 190 nm pitch and (a) 115 nm or (b) 155 nm recessed regions etched 12 15 nm into the 200 nm thick thermally grown oxide layers. width to diffusion length. The trenches were etched 12 15 nm into the 200 nm-thick SiO 2 layer. For the study of Ge nucleation, organic SAMs were formed on unpatterned or patterned, oxidized Si substrates. Alkylsiloxane monolayers were spontaneously formed on SiO 2 by immersing the oxidized Si into a solution containing the octadecyltrichlorosilane (OTS) precursor for varying durations. As will be discussed below, on the unpatterned layers isolated domains formed initially, and extended times (20 h) were needed to obtain a completely saturated monolayer. The completely saturated SAM formed in a much shorter time on nanoimprinted substrates. To minimize effects of water on SAM formation, the solutions of OTS were prepared in bicyclohexyl, toluene, or chloroform, in a glove box. Bicyclohexyl produced the most reproducible and highest quality films. The samples were rinsed repeatedly before using. Si and Ge were deposited by chemical vapor deposition (CVD) in a lamp-heated, reduced-pressure reactor, in which the walls of the process chamber remain at a much lower temperature than the substrates. The substrates were placed on a SiC-coated graphite support plate of moderate thermal mass in a load lock before being introduced into the process chamber, so that the process chamber was not exposed to air during normal operation. Silane (SiH 4 ) and germane (GeH 4 ) were used as gaseous precursors in a hydrogen ambient. The total pressure was in the range of 10 90 Torr during deposition. Deposition temperatures were 400 600 1C for Ge and 700 900 1C for Si. After the samples were removed from the reactor, they were analyzed by scanning electron microscopy (SEM),

T.I. Kamins et al. / Microelectronics Journal 37 (2006) 1481 1485 1483 atomic-force microscopy (AFM), and X-ray diffraction. To determine the stability of the SAMs, they were annealed in hydrogen in the same reactor and analyzed by X-ray photoelectron spectroscopy (XPS) and water contact angle. 3. Experimental results To study the initial stages of deposition, patterned substrates were exposed to SiH 4 /H 2 for short durations (from 30 s to 2 min), with the results shown in Fig. 2. For the shorter deposition time of 30 s (Fig. 2(a)), only a very few nuclei formed. These nuclei were adjacent to the step edges, as desired, indicating that the surface diffusion length was sufficient for the adsorbed atoms to reach a step edge before random nucleation occurred. A typical island was 35 nm in lateral dimension and 3 nm in height. After 2 min of deposition, islands were again positioned adjacent to the step edges. Most islands were located in the recessed areas, but some were on the raised regions. The typical island dimensions in the recessed region were 75 nm in lateral dimension and 13 nm in height. As seen in Figs. 2(b) and (d), the island top is relatively flat. For comparison, islands on unpatterned substrates (Figs. 2(e) and (f)) have a rounded profile without a distinct flat top. As the deposition continues, the islands adjacent to the edges become larger, but the probability of random nucleation increases with increasing deposition time. To minimize random nucleation during additional deposition and enlarge the silicon nuclei formed at the pattern edges, in a second deposition step the temperature was lowered and the silane partial pressure was reduced (by decreasing the total pressure). Fig. 3(a) shows an SEM of a deposit formed by two-step growth on a patterned substrate. Silicon nuclei initially formed adjacent to the pattern edges at 900 1C were further grown for 5 min at 800 1C at a lower total pressure. Some islands appear to extend completely across the 115 nm-wide recessed region or the 75 nm-wide raised region, indicating that the two-step deposition can suppress random nucleation. Discontinuities along the length of each region show that the nucleation is random Fig. 2. Atomic-force micrographs of Si nucleation at 900 1C for (a) 30 s and (c) 2 min on nanoimprinted substrates. Corresponding sections are shown in (b) and (d), respectively. (e) 2 min deposition on an unpatterned substrate. (f) Typical section of islands shown in (e).

1484 ARTICLE IN PRESS T.I. Kamins et al. / Microelectronics Journal 37 (2006) 1481 1485 Fig. 3. SEM of deposits formed by nucleation at 900 1C and 10 Torr for 45 s followed by continued deposition at 800 1C and 3 Torr for 5 min on (a) patterned substrate and (b) unpatterned substrate. along the length of the pattern, as expected. An unpatterned control sample on which Si was deposited at the same time is shown in Fig. 3(b) for comparison. To observe the effect of a SAM on the nucleation, unpatterned samples with and without a SAM were exposed to SiH 4 at 700 1C. Atomic-force and scanningelectron micrographs show much finer grains on the SAM than on bare oxide, suggesting that the SAM aids nucleation even though the majority of the C was removed by the 700 1C heat treatment. After extended Si deposition (90 min), the differences between samples with and without a SAM were less readily observed. When Ge is deposited on SiO 2 by CVD, nucleation does not occur readily. Therefore, a SAM was formed on the oxide surface in an attempt to improve nucleation. Ge was deposited at either 400 or 600 1C. The lower deposition temperature does not degrade the SAM significantly; the higher temperature is expected to degrade, but not completely remove, the SAM [5]. On an unpatterned surface the SAM enhances nucleation at both temperatures, but the grains do not grow together readily at either temperature. Fig. 4. (a) Atomic-force micrograph of OTS SAM showing isolated domains after 5 min deposition onto unpatterned thermal SiO 2 surfaces; x ¼ y ¼ 800 nm full scale. (b) Continuous SAM on nanoimprint-patterned SiO 2 reacted with OTS for 5 min; x ¼ y ¼ 1 mm full scale. One difficulty with using SAMs is the limited domain size over which lateral order is obtained. The disordered domain boundaries might be locations of preferential semiconductor nucleation, and the different in-plane ordering in different domains prevents growth of large areas of single-crystal semiconductor. In an attempt to impose longer-range order, a SAM was formed on nanoimprinted substrates. To obtain information about the domain size, SAMs were formed on unpatterned substrates for limited lengths of time so that the domains remained isolated and could be readily observed by AFM. Fig. 4(a) shows isolated domains of a SAM formed for the limited time of 5 min. The islands are 1.9 nm high, as expected for this type of SAM [6], and extend laterally about 300 400 nm. When the islands coalesce to form a saturated SAM, the boundaries are less readily imaged, but are still expected to influence the nucleation of a subsequently deposited semiconductor. When the SAM is formed on a nanoimprinted substrate even for a short time, it appears to cover the entire surface

T.I. Kamins et al. / Microelectronics Journal 37 (2006) 1481 1485 1485 (Fig. 4(b)). The presence of C corresponding to the SAM was confirmed by XPS. No isolated islands are visible by AFM. We speculate that the edges of the nanoimprint pattern serve as efficient nucleation sites for the SAM, so that ordered islands quickly coalesce to form a continuous film. To compare the effect of SAM and nanoimprinting on Ge nucleation, substrates with nanoimprint-patterned surfaces and unpatterned and patterned surfaces covered with SAMs were compared with bare, unpatterned surfaces. Both the SAM and the nanoimprinted surface aided Ge nucleation, and the combination (SAM on a nanoimprinted surface) was even more effective. We speculate that the discontinuity in packing of the SAM at the feature edges provides effective sites for Ge nucleation. 4. Summary Surface relief formed by nanoimprinting and etching into a thermally grown oxide layer was used to position the initial nuclei formed by chemically vapor deposited Si and Ge. By controlling the deposition conditions, the surface diffusion length was adjusted to be comparable to or larger than the spacing between features, thus favoring nucleation adjacent to steps, rather than random nucleation. Random nucleation was further suppressed by a two-stage deposition process. Ge nucleation on oxide by CVD was enhanced by coating the oxide surface with an organic SAM and by the nanoimprinted surface relief. The nanoimprinted surface relief also provides long-range order in the SAM. Acknowledgement The authors thank Dr. R. Stanley Williams of Hewlett- Packard for useful discussions and Filip Crnogorac and Daniel Witte of Stanford University for their assistance in the fabrication of NIL samples. This work was supported in part by the Defense Advanced Research Projects Agency (DARPA) and the Office of Naval Research (ONR). References [1] M.W. Geis, D.C. Flanders, H.I. Smith, Appl. Phys. Lett. 35 (1979) 71. [2] E.I. Givargizov, Heterogen. Chem. Rev. 2 (1995) 69. [3] H. Mori, Jpn. J. Appl. Phys. 20 (1981) L905. [4] S.Y. Chou, P.R. Krauss, P.J. Renstrom, Science 272 (1996) 85. [5] A.A. Yasseri, et al., Unpublished. [6] Y. Wang, M. Lieberman, Langmuir 19 (2003) 1159.