Mask Substrate/Blank Cleaning Progress Challenges

Similar documents
Roadmap in Mask Fab for Particles/Component Performance

Status and Challenges in EUV Mask Cleaning

Surface Preparation and Cleaning Conference April 19-20, 2016, Santa Clara, CA, USA. Nano-Bio Electronic Materials and Processing Lab.

EUV Defect Repair Strategy

Process Optimization in Post W CMP In-situ Cleaning. Hong Jin Kim, Si-Gyung Ahn, Liqiao Qin CMP, Advanced Module Engineering GLOBALFOUNDRIES, USA

LITHOGRAPHY MATERIAL READINESS FOR HVM EUV TECHNOLOGY DANILO DE SIMONE

Simulation Analysis of Defect Repair Methods for EUVL Mask Blanks

Resolution, LER, and Sensitivity Limitations of Photoresist

Atomic Layer Deposition(ALD)

450mm Metrology and Inspection: The Current State and the Road Ahead. Rand Cottle (CNSE), Nithin Yathapu (GF), Katherine Sieg (Intel)

Film loss-free cleaning chemicals for EUV mask lifetime elongation developed through combinatorial chemical screening

Photolithography I ( Part 2 )

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller

EDA Assessment. Steve Fulton Charisse Nabors

Electroplating. Copyright 2016 Industrial Metallurgists, LLC

EE40 Lec 22. IC Fabrication Technology. Prof. Nathan Cheung 11/19/2009

Metallization deposition and etching. Material mainly taken from Campbell, UCCS

micro resist technology

Processing guidelines. Negative Tone Photoresist Series ma-n 2400

DuPont MX5000 Series

5.8 Diaphragm Uniaxial Optical Accelerometer

E-Beam Coating Technology for EUVL Optics

Post CMP Cleaning SPCC2017 March 27, 2017 Jin-Goo Park

Lithography options for the 32nm half pitch node. imec

TSV Processing and Wafer Stacking. Kathy Cook and Maggie Zoberbier, 3D Business Development

125nXT Series. EMD PeRFoRmaNce MaTeRIaLs. technical datasheet. Photopolymer Negative Tone Photoresists APPLICATION TYPICAL PROCESS THICKNESS GRADES

CMP challenges in sub-14nm FinFET and RMG technologies

Mask Cleaning Strategies Particle Elimination with Minimal Surface Damage

Processing guidelines

Amorphous Oxide Transistor Electrokinetic Reflective Display on Flexible Glass

Lubricant Varnishing and Mitigation Strategies

CMP Defects and Evolution of PCMP Cleans

TSV Interposer Process Flow with IME 300mm Facilities

Metal Oxide EUV Photoresists for N7 Relevant Patterns

Laser Produced Plasma for Production EUV Lithography

COMPATIBILITY OF THE ALTERNATIVE SEED LAYER (ASL) PROCESS WITH MONO- Si AND POLY-Si SUBSTRATES PATTERNED BY LASER OR WET ETCHING

Using Argon Plasma to Remove Fluorine, Organic and Metal Oxide Contamination for Improved Wire Bonding Performance

ENVIRO/Etch Replenisher

Fabrication Techniques for Thin-Film Silicon Layer Transfer

US A1 (19) United States (12) Patent Application Publication (10) Pub. N0.: US 2013/ A1 Jindal et a]. (43) Pub. Date: Aug.

Process Flow in Cross Sections

SAES experience in NEG coating of narrow gap insertion devices and small diameter chambers for accelerators

Lecture 5. SOI Micromachining. SOI MUMPs. SOI Micromachining. Silicon-on-Insulator Microstructures. Agenda:

Surface Preparation Challenges in Crystalline Silicon Photovoltaic Manufacturing

BONDING OF MULTIPLE WAFERS FOR HIGH THROUGHPUT LED PRODUCTION. S. Sood and A. Wong

Lithography Tool Package

Reactor wall plasma cleaning processes after InP etching in Cl 2 /CH 4 /Ar ICP discharge

Lab #2 Wafer Cleaning (RCA cleaning)

EV Group 300mm Wafer Bonding Technology July 16, 2008

Overview of SEMI Standards for EUV Masks. Scott Hector ISMT/Motorola Chairman of SEMI EUV Mask Task Force

High-efficiency GaN-based light-emitting diodes fabricated with identical Ag contact formed on both n- and p-layers

Plasma for Underfill Process in Flip Chip Packaging

2006 UPDATE METROLOGY

Fabrication of Ru/Bi 4-x La x Ti 3 O 12 /Ru Ferroelectric Capacitor Structure Using a Ru Film Deposited by Metalorganic Chemical Vapor Deposition

Electrical Characteristics of Rare Earth (La, Ce, Pr and Tm) Oxides/Silicates Gate Dielectric

THE NEXT GENERATION OF GERMANIUM SUBSTRATES: EXPOGER

Visualization and Control of Particulate Contamination Phenomena in a Plasma Enhanced CVD Reactor

Enabling Low Defectivity Solutions Through Co- Development of CMP Slurries and Cleaning Solutions for Cobalt Interconnect Applications

EUVL Mask Defect Strategy

CMOS Manufacturing Process

Alternative Methods of Yttria Deposition For Semiconductor Applications. Rajan Bamola Paul Robinson

UTILIZATION OF ATMOSPHERIC PLASMA SURFACE PREPARATION TO IMPROVE COPPER PLATING PROCESSES.

High Power Gas Discharge and Laser Produced Plasma Sources for EUV Lithography

Overview of CMP for TSV Applications. Robert L. Rhoades, Ph.D. Presentation for AVS Joint Meeting June 2013 San Jose, CA

X-ray Photoelectron Spectroscopy

Technical Data Sheet. Physical Specifications

Enabling Technology in Thin Wafer Dicing

Linear Plasma Sources for Surface Modification and Deposition for Large Area Coating

NSF Center for Micro and Nanoscale Contamination Control

Plasma-Enhanced Chemical Vapor Deposition

FIB mask repair technology for EUV mask 1. INTRODUCTION

Ultra High Barrier Coatings by PECVD

Fabrication Technology

HF last passivation for high efficiency a-si:h/c-si heterojunction solar cells

Optical and Physical Characteristics of EUV Phase Shift Masks

Etching Mask Properties of Diamond-Like Carbon Films

Mater. Res. Soc. Symp. Proc. Vol Materials Research Society

Contamination control in EUV exposure tools

Steam Cycle Chemistry in Air-Cooled Condensers. NV Energy ACC User s Group * November 12-13, 2009 Andrew Howell * Xcel Energy

Damage Threats and Response of Final Optics for Laser-Fusion Power Plants

Introduction to Micro/Nano Fabrication Techniques. Date: 2015/05/22 Dr. Yi-Chung Tung. Fabrication of Nanomaterials

Atomic Oxygen-Resistant, Static-Dissipative, Pinhole-Free Coatings for Spacecraft

EE C245 ME C218 Introduction to MEMS Design Fall 2011

Comparison of Atmospheric Plasma and Corona Treatments in Promoting Seal Strength

Applied Research for Vacuum Web Coating: What is Coming Next?

Chemraz (FFKM) Overview

FABRICATION ENGINEERING MICRO- NANOSCALE ATTHE AND. Fourth Edition STEPHEN A. CAMPBELL. of Minnesota. University OXFORD UNIVERSITY PRESS

2. High Efficiency Crystalline Si Solar Cells

Process steps for Field Emitter devices built on Silicon wafers And 3D Photovoltaics on Silicon wafers

Creating a Process-based Cost Model

Design & Fabrication of a High-Voltage Photovoltaic Cell. Jennifer Felder

High Performance, Ceria Post-CMP Cleaning Formulations for STI/ILD Dielectric Substrates

Surface micromachining and Process flow part 1

LOW TEMPERATURE PHOTONIC SINTERING FOR PRINTED ELECTRONICS. Dr. Saad Ahmed XENON Corporation November 19, 2015

Silicon Nitride Substrates for Power Electronics. Ulrich Voeller, Bernd Lehmeier

Amorphous Silicon Solar Cells

Lecture Day 2 Deposition

Nano-imprinting Lithography Technology І

2015 EE410-LOCOS 0.5µm Poly CMOS Process Run Card Lot ID:

Imprint Lithography: Getting to the Next Level

Transcription:

Accelerating the next technology revolution Mask Substrate/Blank Cleaning Progress Challenges Arun JohnKadaksham and Frank Goodwin SEMATECH, Albany, NY 10/06/2013 Copyright 2012 SEMATECH, Inc. SEMATECH, and the SEMATECH logo are registered servicemarks of SEMATECH, Inc. International SEMATECH Manufacturing Initiative, ISMI, Advanced Materials Research Center and AMRC are servicemarks of SEMATECH, Inc. All other servicemarks and trademarks are the property of their respective owners.

Outline EUV Substrate and Mask cleaning challenges Current capability Challenges in mask and substrate cleaning Steps taken by SEMATECH for addressing the challenges and closing the gaps in cleaning technology Immediate focus Long term

Substrate Cleaning Challenge: Quality of Substrates Quality of substrates is the primary challenge in substrate cleaning Poor quality substrates have low cleaning yield and blank yield M7360 inspection images of substrates with low quality Cleaning yield is reduced by substrates of low quality

Overcoming Substrate Quality Issue with Cleaning Current solution is to introduce substrate etching to remove killer particles and defects Optimize for all particles @ 36 nm+ All particle removal and No adders @ 10 nm+ Complete residual removal @ 10 nm + Surface Conditioning Organic removal Killer Particle removal Soft Particle removal Chemical residue removal Etch surface and remove High Freq Megasonics Chemistry

Issues with Current Substrate Cleaning Method Substrate roughness and pit counts increase by removal of killer particles, although not significant enough to impact blank properties and total defects Ideal Solution: Cleaning process that removes all particles without roughening or generating pits or a complementary process that will mitigate pits and roughness Substrate roughness and pits post etch clean process

Complete Substrate Cleaning Solution Dressed Photon NanoPolishing (DPNP) has been identified as a potential technique for pit and surface smoothing. Process integration into a cleaning tool is ongoing

Particle Removal Technology Megasonics is still the primary particle removal technology Pit damage from megasonics is a well known issue SEMATECH has optimized megasonics for no pit generation on substrates at defect sizes above 38nm and on blanks above 50 nm (SiO 2 equivalent size) Frequency and power were used as optimization parameters Megasonics can be further optimized by the gas and medium properties Other particle removal technologies with better PRE might exist Binary spray, ion beam, plasma etc. R + 3 2 R 2 + 2σ ρr + 4μR ρr + 1 ρ P 0 P 0 + 2σ R 0 R 0 R 3γ P A sin ωt = 0

Chemicals for Cleaning Industry still relies on harsh acids and bases for cleaning Effect of these chemistries on EUV mask degradation, outgassing, and molecular and progressive contamination is well known Alternative chemicals and advanced cleaning techniques need to be investigated and implemented Current Technology Purpose Issues Alternative Advantage SPM (H2SO4/H2O2) APM (NH4OH/H2O2) Ozone Process Organic removal, metallic particle removal Particle removal Organic removal, particle removal Oxidation, outgassing, progressive contamination Oxidation, Etching, pitting, residual contamination Oxidation, particle adders Insitu-UV, Plasma TMAH, dilute Ammonia H2 water, Insitu UV No residues, dry cleaning No pit generation and residues No oxidation and residues, recovery of blanks from oxidized state

Backside Cleaning A cleaning process for removing large particles from EUV mask backside without affecting front surface does not exist Primarily due to spin-spray technique currently used for cleaning An alternative process for backside cleaning needs to be developed Images from Suss-microtec Spin spray clean with backside rinse is not the ideal solution for cleaning backside of mask

EUV Mask Cleaning for Lifetime SPM/APM chemistries have known issues with lifetime cleaning of EUV masks Insitu-UV cleaning developed for EUV mask cleaning needs to be optimized for damage free lifetime cleaning Plasma/dry cleaning need to be characterized/optimized and incorporated into mask cleaning Hydrogen plasma chamber at CNSE for mask cleaning How to improve mask lifetime by improving mask material? Understanding the Mechanism of Capping Layer Damage and Development of a Robust Capping Material for 16 nm HP EUV Mask, Il-Yong Jang et. al., SEMATECH, Oct 7, Session 2 EUV Symposium

Collaborate and Innovate Concepts are not going to materialize into products without partnerships CNSE (University) Concept Fundamental Leaning SEMATECH Feasibility Product Suss- Microtech Member Company Requirements

SEMATECH/Suss-Microtech Projects for Near Future Integrated tool for substrate cleaning with pit smoothing DPNP integrated with mask cleaning tools Insitu-UV process optimization Status: New lamp installed and Mask cleaning tests ongoing Backside cleaning without impacting front side Status: Working on concepts and supplier/literature search Development of plasma module for dry cleaning and mask lifetime cleaning Status: Fully functional feasibility test module at CNSE Third party tool supplied to SEMATECH from Suss-Microtech Tool installation and cleaning tests start this year Alternate particle removal methods and chemicals Status: Alternate particle removal methods identified Status: TMAH delivered

Summary SEMATECH has entered into a partnership with Suss- Microtech to address the gaps in advanced mask cleaning technology Together with the partnership with CNSE, SEMATECH is enabled to do rapid product and process development from concepts Immediate needs and gaps have been identified and SEMATECH and Suss-Microtech is working in closing the gaps Any further requirements and suggestions from member companies can be addressed and incorporated into plans