Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive

Similar documents
Supporting Information

Supporting Information: Model Based Design of a Microfluidic. Mixer Driven by Induced Charge Electroosmosis

MICROFLUIDIC ASSEMBLY BLOCKS

Wireless implantable chip with integrated Nitinol-based pump for radio-controlled local drug delivery

All fabrication was performed on Si wafers with 285 nm of thermally grown oxide to

Supporting Information. Fabrication of Flexible Transparent Electrode with Enhanced Conductivity from Hierarchical Metal Grids

Because of equipment availability, cost, and time, we will use aluminum as the top side conductor

Supporting Information

Electronic Supplementary Information

micro resist technology

UV15: For Fabrication of Polymer Optical Waveguides

Fabrication of Oxygenation Microfluidic Devices for Cell Cultures

Fabrication of Oxygenation Microfluidic Devices for Cell Cultures

Microelectronic Device Instructional Laboratory. Table of Contents

Figure SI-1. Fabrication process of the microchip. (A) Heater and sensor. 1) Au/Cr

SUPPLEMENTAL INFORMATION: 1. Supplemental methods 2. Supplemental figure legends 3. Supplemental figures

Supporting information for: Microfluidic single cell mrna isolation and analysis

EE 5344 Introduction to MEMS. CHAPTER 3 Conventional Si Processing

Supporting Information for. Co-Fabrication of Electromagnets and Microfluidic Systems. in Poly(dimethylsiloxane)

SEPARATING PLASMA AND BLOOD CELLS BY DIELECTROPHORESIS IN MICROFLUIDIC CHIPS

PHYS 534 (Fall 2008) Process Integration OUTLINE. Examples of PROCESS FLOW SEQUENCES. >Surface-Micromachined Beam

GLM General information. Technical Datasheet

Microstructures using RF sputtered PSG film as a sacrificial layer in surface micromachining

Czochralski Crystal Growth

Supporting Information for

Lab #2 Wafer Cleaning (RCA cleaning)

How To Write A Flowchart

Patterned photoresist spacers and photo-induced alignment coatings for liquid crystal waveplates and polarizers

ELECTRONIC SUPPLEMENTARY INFORMATION Particle Sorting Using a Porous Membrane in a Microfluidic Device

TI 35ES image reversal resist

Fabrication Process. Crystal Growth Doping Deposition Patterning Lithography Oxidation Ion Implementation CONCORDIA VLSI DESIGN LAB

Introduction to CMOS VLSI Design. Layout, Fabrication, and Elementary Logic Design

Screen Printing of Highly Loaded Silver Inks on. Plastic Substrates Using Silicon Stencils

A Millisecond Micromixer via Single-Bubble-Based Acoustic Streaming

Filling and Planarizing Deep Trenches with Polymeric Material for Through-Silicon Via Technology

Single-digit-resolution nanopatterning with. extreme ultraviolet light for the 2.5 nm. technology node and beyond

Supporting informations

Mostafa Soliman, Ph.D. May 5 th 2014

Supporting Information

This Appendix discusses the main IC fabrication processes.

Adhesion analysis of single circulating tumor cell on base layer of

Supplementary information

Transfer Printing of Thermoreversible Ion Gels for Flexible Electronics

Cost Effective 3D Glass Microfabrication for Advanced Packaging Applications

Using PDMS Micro-Transfer Moulding for Polymer Flip Chip Packaging on MEMS

SUPPLEMENTARY INFORMATION

Fabrication of Microchannel and Micro Chamber for Microfluidic Lab-on-Chip

BEFORE you can do any resist processing, you must be familiar with the chemicals you will be using, and know and respect the dangers of them.

EXPLORING VACUUM CASTING TECHNIQUES FOR MICRON AND SUBMICRON FEATURES. Campus Ker Lann, av Robert Schumann Bruz, France

MEMS Fabrication. Beyond Integrated Circuits. MEMS Basic Concepts

Microelectronics. Integrated circuits. Introduction to the IC technology M.Rencz 11 September, Expected decrease in line width

COMPARATIVE ASSESSMENT OF DIFFERENT SACRIFICIAL MATERIALS FOR RELEASING SU-8 STRUCTURES

Today s Class. Materials for MEMS

Microcontact Printing Procedures for Adhesive and Conductive Epoxies

The Physical Structure (NMOS)

CMOS Fabrication. Dr. Bassam Jamil. Adopted from slides of the textbook

- Supporting Information - Nanoporous Dual-Electrodes with Millimetre Extensions: Parallelized Fabrication & Area Effects on Redox Cycling

High-throughput Immunoassay through In-channel Microfluidic Patterning

A Functional Micro-Solid Oxide Fuel Cell with. Nanometer Freestanding Electrolyte

Chapter 2 MOS Fabrication Technology

Artificial Alveolar-Capillary Membrane on a Microchip

Polymer-based Microfabrication

Process Flow in Cross Sections

2300 Hayward St H.H. Dow Building, Ann Arbor, MI Palmer Commons, 100 Washtenaw Avenue, Ann Arbor, MI

Final Project Report. Date Jan. 30 th, To: Kenji Homma, Adaptive Technologies, Blackburgh, Virginia.

CYCLOTENE* 3000 Series Advanced Electronic Resins

Electronics Design Center Equipment

Galvanic Porous Silicon for High Velocity Nanoenergetics

Fabrication Techniques for Thin-Film Silicon Layer Transfer

Photoresist Coat, Expose and Develop Laboratory Dr. Lynn Fuller

FABRICATION OF CMOS INTEGRATED CIRCUITS. Dr. Mohammed M. Farag

Chapter 4. Sample preparation

Bulk MEMS Fabrication Details Dr. Lynn Fuller, Casey Gonta, Patsy Cadareanu

Surface Micromachining

Development and Characterization of Large Silicon Microchannel Heat Sink Packages for Thermal Management of High Power Microelectronics Modules

IC/MEMS Fabrication - Outline. Fabrication

Report 1. B. Starting Wafer Specs Number: 10 Total, 6 Device and 4 Test wafers

micro resist technology

Supporting Information. Microfabrication and Integration of Diazonium-based Aromatic Molecular Junctions

Ultra Fine Pitch Bumping Using e-ni/au and Sn Lift-Off Processes

MCC. PMGI Resists NANO PMGI RESISTS OFFER RANGE OF PRODUCTS

Lecture 10: MultiUser MEMS Process (MUMPS)

EE 527 MICROFABRICATION. Lecture 15 Tai-Chang Chen University of Washington EE-527 M4 MASK SET: NPN BJT. C (sub) A E = 40 µm x 40 µm

Photolithography I ( Part 2 )

Introduction to Micro/Nano Fabrication Techniques. Date: 2015/05/22 Dr. Yi-Chung Tung. Fabrication of Nanomaterials

CS/ECE 5710/6710. N-type Transistor. N-type from the top. Diffusion Mask. Polysilicon Mask. CMOS Processing

ELEC 3908, Physical Electronics, Lecture 4. Basic Integrated Circuit Processing

NanoSystemsEngineering: NanoNose Final Status, March 2011

Thomas M. Adams Richard A. Layton. Introductory MEMS. Fabrication and Applications. Springer

Soft Lithography. Jin-Goo Park. Materials and Chemical Engineering Hanyang University, Ansan. Electronic Materials and Processing Lab.

L5: Micromachining processes 1/7 01/22/02

Supplementary Information

Lecture 6. Through-Wafer Interconnect. Agenda: Through-wafer Interconnect Polymer MEMS. Through-Wafer Interconnect -1. Through-Wafer Interconnect -2

Fraunhofer ENAS Current results and future approaches in Wafer-level-packaging FRANK ROSCHER

4. Thermal Oxidation. a) Equipment Atmospheric Furnace

Alternative MicroFabrication and Applications in Medicine and Biology

Uncrosslinked SU-8 as a sacrificial material

The Effect of Hydrophobic Patterning on Micromolding of Aqueous-Derived Silk Structures

Platypus Gold Coated Substrates. Bringing Science to the Surface

Transcription:

Low-temperature, Simple and Fast Integration Technique of Microfluidic Chips by using a UV-curable Adhesive Supplementary Information Channel fabrication Glass microchannels. A borosilicate glass wafer (Borofloat 33, 4-inch, 500-μm thick, Schott Technical Glasses Germany) was first thoroughly cleaned in fuming 100% HNO 3 solution for 10 min and subsequently rinsed in DI water and dried. Subsequently, a goldchromium layer was sputtered (Au 150 nm, Cr 30 nm) on the cleaned glass substrate and patterned using positive photoresist (OIR 907-17) by using a standard photolithography process. In this process, the photoresist was first spin-coated on the metal bilayer (4000 rpm for 20 s) to give a layer of 1.7 μm. Afterward, the spin-coated resist was pre-baked at 120 C for 2 min, exposed to UV irradiation (Mask aligner EVG-620, 4 s exposure at 12 mw/cm 2 ), post-baked at 120 C for 1 min, and developed in a developer (OIR 907-17 developer) for 1 min and rinsed in demineralized water before hard-baking (120 C for 15 min) on a hotplate. Subsequently, the Au/Cr layer was patterned using Au-etchant (105043, Merck) and Cr-etchant (111547.2500, Merck), respectively, for a few seconds. This patterned Au/Cr layer behaved as a mask layer for the fabrication of the channels in glass. Microchannels were produced by wet-etching technique by immersion for 20 min in 25% hydrofluoric acid (VLSI Selectipur, BASF). It should be mentioned that as wetetching is isotropic, the glass was also etched laterally and it subsequently formed undercuts below the photoresist mask. As a consequence narrower microchannels had to be designed to compensate for these undercuts. The resulting wafer was rinsed in DI

water before stripping of the remaining photoresist in acetone (15 min; VLSI 100038, BASF) and removal of the Au/Cr layer using the same etchants as before. After rinsing in DI water, the process was finished. SU-8 channels. SU-8 microchannels were fabricated using photolithography techniques on a borosilicate glass substrate (borofloat 33, 4-inch, 500-μm thick, Schott Technical Glasses Germany). The fabrication process also started with similar cleaning of the glass wafer (100% HNO 3 immersion for 10 min). Following this, the glass substrate was dehydrated at 120 C for one hour and pre-treated by oxygen plasma (Tepla 300E, 350 W, 5 min) to ensure good adhesion of the SU-8 precursor on the substrate. A SU-8 5 precursor (Microchem., MA, USA), a negative photoresist, was firstly spin-coated on the glass substrates (500 rpm for 5 s followed by 1000 rpm for 20 s) to give a 14 μm resist layer. This spin-coated photoresist was subsequently pre-baked at 65 C for 2 min and 95 C for 5 min, patterned by photolithography techniques (Mask aligner EVG-620) at 12 mw/cm 2 for 12 s, post-baked at 65 C for 2 min and 80 C for 5 min, developed in RER600 for 10 min and hard baked for 20 min at 180 C. The resulting microchannels were rinsed for 2 min in isopropanol (technical grade, BASF) and stored until dicing. UV-curable adhesive microchannels. NOA 81 microchannels were produced using a combination of UV-exposure and casting techniques against a PDMS-based mold, using the same procedure as published elsewhere. 35 The fabrication of NOA microchannels proceeded via the fabrication of a silicon-based master to produce PDMS molds before actual channel fabrication.

In a first step a silicon-based master was fabricated and structures were produced from SU-8 using a similar process as described above. These structures are identical to the final microchannels fabricated in the UV-curable adhesive NOA 81. The primary master was fabricated on a silicon wafer (100-oriented, p-type, resistivity 5-10 Ω cm, 100 mm diameter, thickness 525 µm, single side polished, Okmetic, Finland) on which SU-8 5 precursor (Microchem., MA, USA) is spin-coated (500 rpm for 5 s followed by 1000 rpm for 20 s) to give a layer of 14 μm. This SU-8 layer underwent the same treatment as before (pre-bake, UV exposure, post-bake, development in RER 600 and hard-bake). This master was subsequently used for the realization of a PDMS mold. A twocomponent kit (Sylgard 184, Dow Corning, Midland, Michigan, USA) was used for PDMS fabrication; it includes a pre-polymer of PDMS as well as curing agent which are mixed in a 10:1 weight ratio. The resulting mixture was thoroughly degassed in vacuum, subsequently poured into the silicon-su8 master, anew degassed in vacuum and cured for 3 h at 80 C. After cooling back to room temperature, the PDMS mould was peeled-off from the master, thoroughly cleaned with ethanol in an ultrasonic bath for 15 min and dried using compressed air before further utilization. As the devices are fabricated at the chip level, this PDMS mould was cut in individual chips using a sharp knife. The resulting chips were subsequently cleaned again in ethanol in an ultrasonic bath for 15 min and carefully dried using compressed air before being used for the channel fabrication. Finally, NOA 81 microstructures were produced using PDMS chips as molds. A small amount of UV-curable adhesive (NOA 81, Norland Product) was placed onto a PDMS mold before pressing against a glass substrate. The adhesive was cured by UV irradiation (5 min, 365 nm) at room temperature. The PDMS chip was peeled-off to

release NOA 81 structures on a glass substrate. It should be noted that the presence of oxygen in the PDMS prevents full curing of the adhesive in the vicinity of the PDMS mold and consequently, a thin layer of uncured material remained on the top of the structures. 35 This can be exploited for straightforward bonding of the NOA 81 structures on a second substrate; the resulting structures were pressed against a cover lid and irradiated again (5 min, 365 nm) to fully cure the adhesive and bond it to a cover lid. Reservoirs Fabrication For some chips, we added inlet and outlet reservoirs to the design to facilitate fluidic connections between the chip and the outer world. These reservoirs were fabricated using powder-blasting technique in the glass substrate at the bottom side of the wafers. In a first step, a photosensitive foil (BF410, Ordyl) was laminated on the backside of the glass wafer. The reservoir pattern was defined using standard photolithography technique, and developed in a 0.2% sodium carbonate solution. Afterwards, the front side of the wafer was covered with a Riston foil to protect the microstructures on that side of the substrate during the powder blasting step and while exposing the substrate to Al 2 O 3 powder (29 µm grain size). Finally, the photosensitive foil was removed using a 0.2% sodium carbonate solution (room temperature, few hours) and the resulting substrate was ultrasonically rinsed in acetone (VLSI 100038, BASF) for 15 min. Chip Preparation Bonding of the chips is performed at the chip level so that individual chips (8 mm x 8 mm) must be released after the channel fabrication before the bonding step. This applies

to glass and SU-8 channels whereas NOA 81 channels were already fabricated at the chip level. Bonding was demonstrated using two types of substrates (glass and parylenecoated silicon), and these also had to be released as 8 mm x 8 mm chips before bonding. Glass substrates (Borofloat 33, 500-μm thick) were diced using dedicated equipment (Disco DAD-321, blade type TC 300, spindle rev. 25,000 rpm). Parylene-coated silicon substrates were kindly provided by IMEC (Leuven, Belgium). Using Chemical Vapor Deposition (CVD) technique, a 10-micron parylene layer was deposited onto silicon substrate. In this process, the solid-state parylene which was heated up to 690 C from a furnace evaporates and flew into a vacuum chamber (100 mtorr) before depositing onto the silicon substrate. Finally, parylene-coated silicon substrates were diced as individual chips with the dimensions of 8 mm x 8 mm. Before bonding, all microfluidic chips and cover substrates were ultrasonically cleaned in ethanol for 15 min and dried at 60 C for 30 min. Subsequently, parylene surfaces were activated by plasma treatment (400 mtorr O 2 pressure, 30 W, Plasma Cleaner, Harrick Plasma, USA) for 5 min; this helped spreading the gluing material between the two layers to be bonded.