Maxim > App Notes > GENERAL ENGINEERING TOPICS PROTOTYPING AND PC BOARD LAYOUT WIRELESS, RF, AND CABLE Keywords: chip scale package, flip chip, CSP, UCSP, U-CSP, BGA, WLCSP May 01, 2008 APPLICATION NOTE 1891 Understanding the Basics of the Wafer-Level Chip-Scale Package (WL-CSP) Abstract: This application note discusses Maxim's wafer-level chip-scale package (WL-CSP). Topics include: wafer construction, tape-and-reel packaging, PCB layout, and assembly and reflow. The article supplies reliability stress-test data per the IPC and JEDEC standards. Note: Ultimately, it is the responsibility of the end user and assembler to abide by their own design and the assembly documents required by their industry standards. Industry standards documents can include, but are not limited to: Association Connecting Electronics Industries (IPC) Joint Electronic Device Engineering Council (JEDEC) Electronic Industries Alliance (EIA) International Electronics Manufacturing Initiative (inemi) International Electrotechnical Commission (IEC) American National Standards Institute (ANSI) Jisso International Council (JIC) Japan Printed Circuit Association (JPCA) Wiring and Harness Manufacturers Association (WHMA) Introduction The wafer-level (WL) chip-scale package (CSP) is a type of CSP, which enables the IC to be attached face down to the printed circuit board (PCB) using conventional SMT assembly methods. The chip's pads connect directly to the PCB pads through individual solder balls, and do not require additional underfill encapsulation material (Figure 1). WL-CSP technology differs from other ball-grid-array, leaded, and laminate-based CSPs because no bond wires or interposer connections are required. Page 1 of 12
Figure 1. Photo of a 4 x 4 WL-CSP with two depopulated grid-array locations, circuit side view. The principle advantage of the WL-CSP is that IC-to-PCB inductance is minimized. As secondary benefits, both package size and manufacturing cycle time are reduced, while thermal conduction characteristics are enhanced. WL-CSP Construction Maxim's WL-CSP area-array chip structure is manufactured by building up the package interconnect structure directly on the silicon circuit wafer substrate. A dielectric repassivation polymer film is applied over the active wafer surface. This film provides both mechanical stress relief for the ball attachment, and electrical isolation at the die surface. Vias are imaged within the polymer film, providing electrical contact to the IC bond pad. WL-CSP ball arrays are configured based on a rectangular grid with uniform grid pitch. The WL-CSP area array can contain any number of rows (2 through 6) and any number of columns (2 through 6). The solder bump material is identified by the A1 indicator in the top mark (see Figure 3 for the location of A1 in top mark). The A1 indicator for eutectic SnPb solder is a laser overlay of dual concentric circles,. For Pb-free solders, the lasered A1 indicator is a plus sign,. Backside wafer lamination, protective polymer film is standard for all Pb-free WL-CSP products. This polymer material is included for both mechanical contact and UV light protection to the backside silicon surface. WL-CSP Area Array Designs and Dimensions Maxim's WL-CSP 0.5mm pitch area array packages are currently designed from 2 x 2 up to 6 x 6 ball array sizes (Figure 2). Detailed WL-CSP drawings are available at: Maxim Package Outlines. Based on the design of a particular device, ball arrays can be populated with fewer than the maximum ball array count. Page 2 of 12
Figure 2. Example of the standard convention for a WL-CSP package outline drawing, 6 x 6 array. WL-CSP Carrier Tape References: ANSI/EIA-481-1-A 8mm and 12mm Taping of Surface-Mount Components for Automatic Handling EIA/IS-763 Bare Die and Chip-Scale Packages Taped in 8mm & 12mm Carrier Tape for Automatic Handling IEC60286-3 Packaging of Components for Automatic Handling Part 3: Packaging of Surface-Mount Components on Continuous Tapes Maxim ships all WL-CSPs in component carrier tape-and-reel (T&R) format only. WL-CSP tape-and-reel requirements are based on the EIA-481 standard. Detailed tape-and-reel construction information is available at: SMD Tape & Reel Data. This page shows packaging diagrams and links to a Tape and Reel Packaging Table (PDF), which includes the WL-CSP reference orientation for the packaging diagram shown there as Figure 4. Another link goes to Tape and Reel Data for Additional Packages (PDF), which provides all the dimensional variables for the packages. 1. The tape pocket cavity shall be configured to provide sufficient clearance surrounding the component so that: The component does not protrude beyond either surface of the carrier tape. The component can be removed from the cavity in a vertical direction without mechanical restriction after the top cover tape has been removed. The rotation of the component is limited to ±10 (max) See Figure 3. Page 3 of 12
2. Radius R minimum is a mechanical bending radius characteristic of the tape design and materials. Actual reel hub radius must be greater than R minimum. Tape with components in normal orientation shall pass around radius R minimum without damaging tape or components. Tape feeders and any other tape handling, shipping, or storage conditions should be configured by the user so that the actual bending radius is always greater than R minimum. 3. Bar code labeling (if required) shall be on the side of the reel opposite the sprocket holes. Refer to EIA556. 4. If the tape pocket pitch equals 2.0mm, the tape may not properly index in all tape feeders. 5. Balls are facing down in the tape-and-reel carrier. Pin A1 orientation is consistent in each pocket in the carrier tape. Mark layout will have Pin A1 ID on the top left corner (Figure 2). 6. The cover tape shall have a total peel strength of from 0.1 N to 1.0 N (i.e., 10 grams to 100 grams calibrated scale reading). The direction of pull shall be opposite the direction of carrier tape travel, so that the cover tape makes an angle of 165 to 180 with the top of the carrier tape. The carrier and/or cover tape shall be pulled with a velocity of 300mm ±10mm/min during peeling. Figure 3. Maximum allowable rotation of a CSP inside the tape-and-reel pocket. PCB Assembly Process Design and Implementation for WL-CSP Reference: IPC-7094 Design and Assembly Process Implementation for Flip-Chip and Die-Size Components PCB Design Criteria References: IPC-A-600 Acceptability of Printed Boards IPC-6011 Generic Performance Specification for Printed Boards IPC-6012 Qualification and Performance Specification for Rigid Printed Boards IPC-6013 Qualification and Performance Specification for Flexible Printed Boards IPC-6016 Qualification and Performance Specification for High-Density Interconnect (HDI) Layers or Boards IPC-D-279 Design Guidelines for Reliable Surface-Mount Technology Printed Board Assemblies IPC-2221 Generic Standard on Printed Board Design IPC-2222 Sectional Design Standard for Rigid Organic Printed Boards IPC-2223 Sectional Design Standard for Flexible Printed Boards IPC-2226 Design Standard for High-Density Array or Peripheral Leaded Component Mounting Structures 1. The design layout for the WL-CSP component should be at the most neutral location of mechanical stress Page 4 of 12
and strain; it should be shrouded by much taller adjacent components, wherever possible. 2. For all two-sided PCB assembly designs, align a much larger compliant package on the opposite side at the WL-CSP centroid location. Land Pattern Design Reference: IPC-7351 Generic Requirements for Surface-Mount Design and Land Pattern Standard Two types of land patterns are used for surface-mount packages (see Figure 4 and Table 1). 1. Solder Mask Defined (SMD) SMD pads are open metal surfaces with defined solder mask openings. The solder mask opening is smaller than the metalized feature. Solder mask material used to define the opening is commonly LPI (liquid photoimageable), and must have suitable material properties to survive all SMT processing requirements. 2. Nonsolder Mask Defined (NSMD) NSMD pads (Figure 5) are metal-defined pads that have an associated solder mask clearance around the pad. The solder mask opening is larger than the metalized pad. The solder mask material used to define the opening is commonly LPI, and must have suitable material properties to survive all SMT processing requirements. Figure 4. SMD vs. NSMD PCB land pad design for WL-CSP. Page 5 of 12
Figure 5. Illustration of a microsection of a PCB nonsolder mask defined pad (NSMD). 1. To choose between NSMD and SMD pads, all power, ground, and signal-routing requirements must be understood. 2. Due to component pitch, NSMD pads can eliminate layout issues. Using microsized vias is another approach to reduce layout issues. 3. Special microvia designs can eliminate surface spacing requirements, e.g., a "via in pad" design. 4. Placing a via next to the pad, if spacing permits, will also help reduce layout issues, e.g., the "dog-bone" feature. 5. Do not mix pad styles in a PCB design for the same package type. 6. Solder mask is recommended between all pads. 7. Trace widths connected to pads should be < ½ pad diameter, with symmetry on all sides of the WL-CSP grid array land pattern. Table 1. Selection of WL-CSP Land Pad Design (microns) WL-CSP Ball Pitch Nominal Ball Size Diameter Standard Land Size Reduction Nominal Land Size Diameter Land Size Diameter Range 500 350 20% 275 225 to 325 500 300 20% 250 200 to 300 400 250 20% 200 175 to 225 Page 6 of 12
Metal Surface Coating 1. Organic solderability preservative (OSP) 2. Electroless nickel/immersion gold (ENIG) 3. Immersion tin plating: hot-air solder level (HASL) tin plating is not recommended. Pb-Free Assembly PCB Material 1. High-temperature FR4-FR5 glass-epoxy laminate, Tg (glass transition temperature), of 170 C for Pbfree/RoHS solder reflow assembly process. 2. Optional BT laminate material. 3. Phenolic-cured glass epoxy laminate material: dicyandiamide ("dicy") cured FR4 material is not recommended for multiple-pass Pb-free reflow assembly. Solder Paste Print Stencil Aperture Design Reference: IPC-7525 Guidelines for Stencil Design Maxim performs solder paste printing for all 0.5mm pitch WL-CSP assembly. Aperture Shape 1. Square is preferred over round for improved solder paste release from the stencil. 2. Trapezoidal sidewalls with bottom surface opening larger than at the top. 3. Square angles in the aperture can be slightly rounded to prevent residual solder paste from remaining in aperture corners. PCB Solder Attach Material 1. Use solder and flux materials that are compatible with the solder ball alloy. 2. Use low halide material. 3. No-clean flux resin/rosin system for elimination of postassembly cleaning process. 4. Type 3 or Type 4 size solder paste. Page 7 of 12
SMT Process Flow Solder Stencil Fabrication Use laser-cut stainless-steel foil with electropolishing or nickel-base electroformed (E-form) metal foil processes. The nickel E-form process is more expensive, but offers the most repeatable solder paste deposition from ultrasmall apertures. It also has the advantage of being formed to any customer-required stencil thickness. Automated Component Placement 1. Stationary Tape-and-Reel feeder bases are required. Sliding feeder bases can result in excessive component loss. 2. Use only vacuum pickup nozzles with camera vision or laser alignment component-centering methods. Mechanical centering options may not be used. 3. Placement height must be accurately determined at the PCB surface, with Z-axis overtravel set to zero or slightly negative. The same applies to the component pickup position on the tape-and-reel feeder. 4. All WL-CSP silicon die component, vertical compression forces should be controlled and monitored. It is suggested that the placement force be programmed towards the machine's lower spec limit and with reduced placement head speed. It is recommended that component placement force measurement verification be performed as a requirement of the machine setup procedure for all silicon die packages. Component placement machine manufacturers may offer special low-force nozzle options and compliant tip materials for silicon-die package assembly. 5. Tooling may be required to prevent PCB deflection during placement. Option 1: Custom-designed rigid PCB panel carrier/pallet for all second-pass assembly operations is recommended as the most reliable method to eliminate potentially damaging PCB deflection to all bottomside component interconnections, including at subsequent assembly operations. Option 2: Adjustable-pin bottomside PCB supports can be utilized for all second-pass assembly pick-and-place machine operations, and should be required wherever high-force or high-mass component placements operations are required. These inexpensive tools may be provided as standard equipment with the original machine purchase, and can also be purchased directly from the machine manufacturer. Page 8 of 12
6. Only use vacuum pencil whenever special manual handling of any silicon die package is required. Solder Paste Reflow Reference: IPC J-STD-020 Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface Mount Devices, Moisture Sensitivity Level 1. 1. All Maxim WL-CSPs are compatible with industry-standard solder reflow processes. 2. Nitrogen inert-atmosphere reflow soldering is optional. However, the use of nitrogen inert-atmosphere reflow has demonstrated increased Pb-free WL-CSP component centering forces to PCB pads vs. airatmosphere reflow. (See Figures 6 and 7.) 3. Forced gas-convection reflow ovens are recommended. 4. WL-CSP solder-bump components are qualified for up to three standard reflow cycles. Figure 6. Typical reflow temperature profile for eutectic SnPb solder ball WL-CSP. Page 9 of 12
Figure 7. Typical reflow temperature profile for Pb-free SAC solder-ball WL-CSP. Note: 1) Soak for 150s to 210s over region bounded by green lines; 2) time above 220 C is 60s to 90s; 3) time above 235 C is 10s to 30s; 4) time to peak temperature is 240s to 360s. Reference: J-STD-202 Rev D, Tables 4.1-4.2, and 5.2. NOTE: The above profiles are provided for reference only. Actual reflow profiles should be optimized for specific reflow furnace, solder paste, component(s), and PCB assembly process. 5. 2D tansmission X-ray or 3D X-ray laminography is recommended as a postreflow solder-joint inspection monitoring method for solder shorts, insufficient solder, voids, and potential solder opens. Rework of WL-CSP Rework should only be performed using a controlled and qualified process which prevents mechanical and ESD damage to the silicon-die circuit package. Focused infrared technology is recommended for ball-array-package rework over traditional hot gas BGA rework systems. Focused IR allows for pin-point accuracy, reflow removal, and replacement of even the smallest CSP on a high-density circuit assembly without adjacent component contact heating. Pack and Ship To prevent damage to the WL-CSP package, care must be taken in the packing and shipping of all WL-CSP assemblies and subassemblies. Page 10 of 12
Maxim WL-CSP Reliability Data Maxim WL-CSP Qualification Requirements Reference: JESD47 Stress-Test-Driven Qualification of Integrated Circuits Reliability tests detailed in Tables 2 and 3 were performed to qualify Maxim WL-CSPs. Optional tests can also be performed as needed. Table 2. Wafer-Level Tests Reliability Test High-Temperature Storage Life (HTSL) Moisture Sensitivity Level 1 Solder Reflow (MSL 1) Test Condition and Sampling Plan JESD22-A103 (150 C/1000 hours, no bias; three lots with 0/77 per lot) J-STD-20 (three reflow passes at 260 C max peak temperature; three lots with 0/150 per lot) Table 3. Board-Level Tests (WL-CSP Mounted on 1.0mm Thick FR4 FR5 Board) Reliability Test Test Condition and Sampling Plan High-Temperature Operating Life (HTOL) Drop Test (DT) Temperature Cycling (TC) Test Temperature Humidity and Bias (THB) Steady State JESD22-A108 (135 C ambient, with bias, 1000 hrs; three lots with 0/77 per lot) JESD22-B111 (1500Gs, 0.5msec, half sine pulse; one lot with 0/60, 150 drops min) JESD22-A104 condition G (-40 C to +125 C, 1000 cycles, ramp rate 11 C/minute, dwell = 15 minutes, one cycle/hour; three lots with 0/77 per lot) JESD22-A101 (85 C, 85% RH, max operating voltage; three lots with 0/77 per lot) The results of Maxim's WL-CSP product reliability tests are listed below in Tables 4 through 8. Pb-free WL-CSP products on 0.5mm bump pitch up to 6 x 6 bump arrays have been fully qualified. Maxim Pb-Free (SAC305) WL-CSP Reliability Test Data NOTE: SAC305 solder ball (LF45), Sn96.5/Ag3.0/Cu0.5 metals composition by weight. Table 4. Wafer-Level High-Temperature Storage Life (HTSL) Test Data (Three Lots) High-Temp Storage (HTS) 500hr 1000hr 6 x 6 array 0/240 0/240 5 x 4 array 0/154 0/154 3 x 3 array 0/180 0/180 3 x 4 array 0/231 0/231 Table 5. Wafer-Level Moisture-Sensitivity Level 1 Reflow Preconditioning Test Data (Three Lots) Moisture Sensitivity Level 1 Conditions Results 6 x 6 array 3x reflow passes, 260 C max 0/150 5 x 4 array 3x reflow passes, 260 C max 0/150 3 x 3 array 3x reflow passes, 260 C max 0/90 (two Lots) 3 x 4 array 3x reflow passes, 260 C max 0/450 Page 11 of 12
Table 6. Board-Level Drop-Test Data (Cumulative Fails) Drop Test 30x 50x 100x 150x 200x 300x 400x 500x 6 x 6 array 0/120 0/120 0/120 0/120 0/120 0/120 0/120 0/120 Table 7. Board-Level Accelerated Temperature Cycling (TC) Test Data (Three Lots) Temperature Cycle Test 250x 500x 750x 1000x 6 x 6 array 0/231 0/231 0/231 0/231 5 x 4 array 0/231 0/231 0/231 0/231 3 x 3 array 0/135 0/135 0/135 0/135 3 x 4 array 0/231 0/231 0/231 0/231 Table 8. Board-Level High-Temperature Operating Life (HTOL) Test Data (Three Lots Each) HTOL Test 500hr 1000hr 6 x 6 array 0/45 0/45 5 x 4 array 0/45 0/45 3 x 3 array 0/40 0/40 UCSP is a trademark of Maxim Integrated Products, Inc. Application Note 1891: www.maxim-ic.com/an1891 More Information For technical support: www.maxim-ic.com/support For samples: www.maxim-ic.com/samples Other questions and comments: www.maxim-ic.com/contact Automatic Updates Would you like to be automatically notified when new application notes are published in your areas of interest? Sign up for EE-Mail. AN1891, AN 1891, APP1891, Appnote1891, Appnote 1891 Copyright by Maxim Integrated Products Additional legal notices: www.maxim-ic.com/legal Page 12 of 12