ECEN454 Digital Integrated Circuit Design Fabrication and Layout ECEN 454 3.1 A Glimpse at MOS Device Polysilicon Aluminum ECEN 475 4.2 1
Material Classification Insulators Glass, diamond, silicon oxide Semiconductors Germanium (Ge), Silicon (Si), Gallium Arsenide (GaAs) Conductors Aluminum, copper, gold I n c r e a s i n g c o n d u c t i v i t y ECEN 475 4.3 Czochralski method Melt pure polycrystalline silicon in a pot (1400C) A seed crystal is dipped to determine the crystal orientation Single-crystal ingot is made as polycrystalline silicon is slowly pulled out and freezes Wafer Processing ECEN 475 4.4 2
Wafer Processing Silicon ingots have a diameter of 8-12 inches Ingots are carefully cut into thin disks (wafers) A wafer is typically 200-500um thick ECEN 475 4.5 A single die Wafer From http://www.amd.com ECEN 475 4.6 3
IC fabrication Process Consists of a sequence of processing steps: Various conducting, semi-conducting and insulating material layers are fabricated to form appropriate 3d device structures Major processing steps are: Lithography Oxidation Layer deposition Etching Diffusion Implantation ECEN 475 4.7 Inverter Cross-section Typically use p-type substrate for nmos transistors Require n-well for body of pmos transistors GND A Y 00 00 000 000 000 000 n+ n+ p+ p+ V DD 0 0 0 0 SiO 2 n+ diffusion p+ diffusion polysilicon metal1 nmos transistor pmos transistor ECEN 475 4.8 4
Well and Substrate Taps Substrate must be tied to GND and n-well to V DD Metal to lightly-doped semiconductor forms poor connection called Shottky Diode Use heavily doped well and substrate contacts / taps A GND 0 0 000 0 000 0 00 0 0 p+ n+ n+ p+ p+ n+ Y V DD 0 substrate tap well tap ECEN 475 4.9 Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line GND 00 00 00 A 00 Y V DD substrate tap nmos transistor pmos transistor well tap ECEN 475 4.10 5
Detailed Mask Views Six masks n-well Polysilicon n+ diffusion p+ diffusion Contact Metal 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 00 00 Polysilicon n+ Diffusion p+ Diffusion 0 0 0 0 0 0 00 00 00 Contact 00 00 Metal ECEN 475 4.11 Fabrication Steps Start with blank wafer Build inverter from bottom up First step will be to form the n-well Cover wafer with protective layer of SiO 2 (oxide) Remove layer where n-well should be built Implant or diffuse n dopants into exposed wafer Strip off SiO 2 ECEN 475 4.12 6
Oxidation Grow SiO 2 on top of Si wafer 900 1200 C with H 2 O or O 2 in oxidation furnace SiO 2 ECEN 475 4.13 Photoresist Spin on photoresist Photoresist is a light-sensitive organic polymer Softens where exposed to light Photoresist SiO 2 ECEN 475 4.14 7
Lithography Expose photoresist through n-well mask Strip off exposed photoresist Photoresist SiO 2 ECEN 475 4.15 Etch Etch oxide with hydrofluoric acid (HF) Only attacks oxide where resist has been exposed Photoresist SiO 2 ECEN 475 4.16 8
Strip Photoresist Strip off remaining photoresist Use mixture of acids called piranah etch Necessary so resist doesn t melt in next step 000 0 SiO 2 ECEN 475 4.17 n-well n-well is formed with diffusion or ion implantation Diffusion Place wafer in furnace with arsenic gas Heat until As atoms diffuse into exposed Si Ion Implanatation Blast wafer with beam of As ions Ions blocked by SiO 2, only enter exposed Si SiO 2 ECEN 475 4.18 9
Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps ECEN 475 4.19 Polysilicon Deposit very thin layer of gate oxide < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer Place wafer in furnace with Silane gas (SiH 4 ) Forms many small crystals called polysilicon Heavily doped to be good conductor 00 Polysilicon Thin gate oxide ECEN 475 4.20 10
Polysilicon Patterning Use same lithography process to pattern polysilicon Polysilicon Polysilicon Thin gate oxide ECEN 475 4.21 Self-Aligned Process Use oxide and masking to expose where n+ dopants should be diffused or implanted N-diffusion forms nmos source, drain, and n-well contact 00 00 ECEN 475 4.22 11
N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates because it doesn t melt during later processing n+ Diffusion 0 00 0 ECEN 475 4.23 N-diffusion cont. Historically dopants were diffused Now ion implantation is used But the resulting regions are still called diffusion 0 00 00 n+ n+ n+ ECEN 475 4.24 12
N-diffusion cont. Strip off oxide to complete patterning step n+ n+ n+ ECEN 475 4.25 P-Diffusion Similar set of steps form p+ diffusion regions for pmos source and drain and substrate contact p+ Diffusion p+ n+ n+ p+ p+ n+ ECEN 475 4.26 13
Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed 00 00 00 00 00 Thick field oxide p+ n+ n+ p+ p+ n+ Contact ECEN 475 4.27 Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires 0 0 0 0 0 0 00 00 p+ 00 00 00 00 00 n+ n+ p+ p+ n+ Metal Metal Thick field oxide ECEN 475 4.28 14
Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor size (and hence speed, cost, and power) Feature size f = distance between source and drain Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Express rules in terms of λ = f/2 E.g. λ = 0.3 µm in 0.6 µm process ECEN 475 4.29 Simplified Design Rules Conservative rules to get you started ECEN 475 4.30 15
Inverter Layout Transistor dimensions specified as Width / Length Minimum size is 4λ / 2λ, sometimes called 1 unit In f = 0.6 µm process, this is 1.2 µm wide, 0.6 µm long ECEN 475 4.31 Gate Layout Layout design can be very time consuming Design gates to fit together nicely Build a library of standard cells Standard cell design methodology V DD and GND should abut (standard height) Adjacent gates should satisfy design rules nmos at bottom and pmos at top All gates include well and substrate contacts ECEN 475 4.32 16
Example: Inverter ECEN 475 4.33 Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 V DD rail at top Metal1 GND rail at bottom 32 λ by 40 λ ECEN 475 4.34 17
Stick Diagrams Stick diagrams help plan layout quickly Need not be in scale Draw with color pencils or dry-erase markers ECEN 475 4.35 Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C ) D ECEN 475 4.36 18
Example: O3AI Sketch a stick diagram for O3AI and estimate area Y = ( A + B + C ) D ECEN 475 4.37 Photolithography ECEN 475 4.38 19
Reticle Pattern Transfer to Resist UV light source Shutter Alignment laser Shutter is closed during focus and alignment and removed during wafer exposure Reticle (may contain one or more die in the reticle field) Single field exposure, includes: focus, align, expose, step, and repeat process Projection lens (reduces the size of reticle field for presentation to the wafer surface) Wafer stage controls position of wafer in X, Y, Z, θ ECEN 475 4.39 Stepper Exposure Field UV light Reticle field size 20 mm 15mm, 4 die per field 5:1 reduction lens Serpentine stepping pattern Image exposure on wafer 1/5 of reticle field 4 mm 3 mm, 4 die per exposure Wafer ECEN 475 4.40 20
Photo-resist Negative Resist Wafer image is opposite of mask image Exposed resist hardens and is insoluble Developer removes unexposed resist Positive Resist Mask image is same as wafer image Exposed resist softens and is soluble Developer removes exposed resist ECEN 475 4.41 Negative Lithography Chrome island on glass mask Shadow on photoresist Ultraviolet light Exposed area of photoresist Areas exposed to light become crosslinked and resist the developer chemical. Island Photoresist Window Photoresist Oxide Silicon substrate Oxide Silicon substrate Resulting pattern after the resist is developed. ECEN 475 4.42 21
Positive Lithography Chrome island on glass mask Ultraviolet light Shadow on photoresist Areas exposed to light are dissolved. Island Window Exposed area of photoresist photoresist Photoresist Photoresist photoresist Oxide oxide Silicon silicon substrate Oxide oxide Silicon silicon substrate Resulting pattern after the resist is developed. ECEN 475 4.43 Lens Capturing Diffracted Light Quartz UV Mask Chrome Diffraction patterns 4 4 3 2 1 1 2 3 0 Lens ECEN 475 4.44 22
Effect of Numerical Aperture (NA) Pinhole masks Lens NA Image results Bad Poor Good Diffracted light ECEN 475 4.45 Optical Proximity Effects Rounded corners Nonuniform CDs Shortened lines ECEN 475 4.46 23
Optical Proximity Correction (OPC) (a) Uncorrected design (b) Corrected with feature biasing (c) Feature assisting technique ECEN 475 4.47 24