Mastering the Tolerances Required by New PCB Designs Brad Hammack Multek Doumen, China Abstract The packaging industry is driving the Printed Circuit Board (PCB) technology level in the direction of semiconductor requirements. High density PCB s are becoming commonplace in the network routers, automated test equipment, servers, and PDA sectors. The need for high density is becoming a common requirement. In order to fan out the high density packages, many layers are being added as finer lines, spacing and via diameters are approaching conventional manufacturing limits. These attributes are driving changes in base materials, imaging, etching, plating, soldermask, testing processes, and registration systems. This paper examines trends in PCB attributes, utilitizes a registration model and the Rayleigh distribution to predict capability for advanced registration requirements, and examines factor significance in achieving the exacting requirements for new PCB designs. Introduction There are multiple drivers for the increasing need for more function in less space. The drivers include added functions for character data, voice data, and image data. Additional drivers include increased memory and hard disk data transfer rates, bandwidth increase, surface area shrinks which increases the wattage required, increased use of ultra-small high speed circuits, increased number of high density components for speed acceleration, shorter distance between components, and reduced propagation delay. The rapid pace of change in packaging that has occurred in order to accommodate higher performance requirements, has posed several challenges in both PCB manufacturing and assembly processes. The increased density has lead to higher layer PCB designs, demanding improved registration tolerances in both manufacturing equipment and PCB processes. The improved registration tolerances are needed not only because of tolerance build up, but also due to reliability. PCB designs have experienced similar trends in line width and finished via diameter reduction. The reduction in line width is approaching current carrying limitations needed to support ASICS and CPU requirements. Available equipment and material sets are approaching conventional limits for volume production processes. Technology Drivers Several technology drivers are converging at the PCB level, dictating more demanding requirements for base materials, design, and reduction in manufacturing process variation. The need for improved thermal stability due to lead free is leading fabricators to phenolic cured resin systems versus dicyandiamide. Interconnect speeds are increasing, eventually exceeding 1000Mb/sec. This will limit trace length in order to manage attenuation losses. When we examine the trends for line width figure 1, drilled hole diameter figure 2, and pad attachment density figure 3, coupled with the dynamics of emerging product requirements, there is only one conclusion. PCB designs will have to increase in layer count. In order to predict the amount of manufacturing variation that is allowable, registration modeling can be useful. It is important to identify all of the factors that effect registration during the PCB fabrication process. For purposes of this paper, not all factors will be examined, but a critical few will be incorporated into the analysis. 1 / 5
Figure 1: Line Width Reduction Figure 2: Via Size Reduction 2 / 5
While PCB photolithography, and drilling processes have been utilized to demonstrate the trends over the past two decades, the packaging trend of pad attachment density continues to accelerate. This trend is a contributing factor for the addition of layers to PCB s and the more exacting tolerance requirements for fine pitch components. Figure 3: PCB Attachment Pad Density Registration Modeling A simple registration capability model can be used to determine your current registration budget. The significant factors affecting registration are photo plotting, artwork dimensional stability, base material dimensional stability, post etch punch variation, drilling set up and hole location. Process Variable Std Dv Artwork Plotting 0.814 Artwork Front-Back 1.400 Post Etch Punch 0.383 Dimensional Stability 1.620 Inner Layer Std Dev 2.322 Inner layer +/- 3 s 6.967 Drill Set Up 0.500 Hole Location 0.530 Drill s 0.729 Drill +/- 3s 2.186 Overall 's' 2.434 Overall +/- 3s 7.302 Drill + (?) Capability (2 x Overall +/- 3s) 14.604 Figure4: Registration Capability Model Source (Format): American Testing Corporation 3 / 5
Taking the capability model a step further, and utlilizing a weibull distribution (Rayleigh) in this case, one can predict the success rate for a given registration requirement. Assume that the drill diameter is.0098, the pad is.0188, and there is a one mil annular ring requirement. Using the overall standard deviation from Figure 5 (2.434) With.001" Annular Ring, Clearance per side =.0035" 0.0045" Accuracy radius =.0035" Pad Dia ==>.0188" Drill Dia 0.0098" Figure 5: Drill + 9 And the cumulative distribution function F(x) = 1-e -(r*2/(2*sigma2)) Solving for F(x) = 0.6443. Given a PWB with 10,000 holes requiring the registration above, 6443 holes would be in tolerance. Figure 7 shows the effect of dimensional variability (standard deviation) and the requirement in order to achieve 100% success. Overall Std Dev F(x) r2/2*sigma2 c=sqrt(2*sigma) 2.434 0.6443 1.0339 2.2064 2.20 0.7179 1.2655 2.0976 2.10 0.7506 1.3889 2.0494 2.00 0.7837 1.5313 2.0000 1.90 0.8167 1.6967 1.9494 1.80 0.8489 1.8904 1.8974 1.70 0.8798 2.1194 1.8439 1.60 0.9086 2.3926 1.7889 1.50 0.9342 2.7222 1.7321 1.40 0.9560 3.1250 1.6733 1.30 0.9733 3.6243 1.6125 1.20 0.9857 4.2535 1.5492 1.00 0.9978 6.1250 1.4142 0.90 0.9994 7.5617 1.3416 0.80 0.9999 9.5703 1.2649 0.70 0.9999 12.5000 1.1832 0.60 1.0000 17.0139 1.0954 Figure 6: Cumulative Distribution Function Size, pattern, and positional tolerances are continuing to increase as next generation PCB designers struggle to route out the packages driving these changes. Figure 7 illustrates these changing requirements. 4 / 5
Additional requirements for conductive-anodic-filament (CAF) and insulation resistance has increased the concern over registration capabilities. New base materials designed to withstand higher thermal processes, exhibit less Z-axis expansion, pass IST and T288 testing, with improved dimensional stability are rapidly being commercialized. M anufacturing Tolerences Positional Tolerences In n er L a y e r P attern O u ter L a y er P atte rn H o le P o sitio n A ccu rac y S o ld e rm ask R eg istratio n S iz e T o leran ces Line W idth (Inner Layer) L in e W id th (O u te r L a y e r) T o o lin g H o le D iam ete r B o w an d T w ist C u rrent 2003 2004 ±25 ±25 ±50 ±50 10 10 50 0.7% Short Term 2005 2006 ±12 ±12 5 5 50 0.5% Long Term 2007-2014 ±8 ±8 ±10 3 3 30 0.3% Figure 7: Manufacturing Tolerances Roadmap Source: Japan s Institute of Electronics Packaging (Modified) Factor Significance The primary factors affecting the registration tolerance build up are (1) Base Materials (2) Tooling (3) Drilling true position, (4) Front to Back image registration, and (5) Artwork dimensional stability. Within the base material alone there are several factors. Using the IPC 4101A 3.9.1.2 test method, the most significant factors affecting dimensional stability of the laminate are (1) Resin content lower is better, (2) Fiberglass diameter and weave balance larger is better, (3) Stabilization baking, and controlled cooling, (4) copper tooth profile lower is better, and (5) fiberglass cloth supplier. There are noticeable differences among different fiberglass cloth suppliers. Utilizing a single source for fiberglass helps minimize the variation. Choosing a supplier with the least amount of movement is not always the best. Selecting a fiberglass cloth supplier that has more consistent movement is recommended. Pin lamination is a must for next generation designs. While mass lamination systems are approaching the mid-teen layer count range, registration tolerances cannot be sustained for the higher layer designs. A regimented maintenance program is needed for maintaining pins, bushings, and registration plate tooling holes. Conclusion As semiconductor and PWB technologies converge, PWB fabricators, equipment manufacturers and material suppliers must work jointly to develop solutions for next generation products. The next generation designs will require tighter controls for front to back registration, drill hole true position, improved soldermask registration, and high speed electrical test equipment for fine pitch area testing. Future demand for products that have more functionality will continue at an accelerated pace. The use of conventional process technology will gradually yield more inefficacious results. Significant improvement in process control, variation reduction, and investment in process development will be a common focus among fabricators trying to maximize their return on technology investment. 5 / 5